From nobody Sun Nov 24 05:05:47 2024 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4BB4E216E1C; Thu, 7 Nov 2024 16:08:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.156.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730995740; cv=none; b=LdEIiGYVH0f2qZ+GEImEvFjOcNL14bu5d37i39Nbxe9xnXE/2S20jo7W+I47mmO2a8BxkrEuSQMP0dI7NT3JjlCP1raIhKnWFK/tXS0lNdtVAN95H6mE4LM5sTCkf/Ccrf2MSSgc/TB3qreXcmOstNQ4jI2xQLQp8zytlX7MNrQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730995740; c=relaxed/simple; bh=V2WDajORA8NZTuPIVpUTKEMx6+F+UMAX2lLG+hNlvxM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=V9kXapOOxcldZvbKUJzDoUEWyhBuuVRRs6RagH/thB+LIBRGg9KpJ5UnG/cBbzsz98l7gZPD9LvL64cexSrbjeCjKINVHb6ZALNE41N/SDmD7SBRKlB8iLmYwZJV6FZMhJ8KC/bo1VcbnqV/s+4ZTeHM0CV8HyAUdl9LoPOq7es= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=iyWm3hM2; arc=none smtp.client-ip=67.231.156.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="iyWm3hM2" Received: from pps.filterd (m0431383.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4A7B7Ye1012527; Thu, 7 Nov 2024 08:08:50 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-type:date:from:in-reply-to:message-id:mime-version :references:subject:to; s=pfpt0220; bh=iXW3AXijVmIH0PhJHdAEbS6KS F0+Mps60E8gJyGgNwA=; b=iyWm3hM2IHRn9JHeZPZOgiYmTuhHwJjtjia7cxo37 qUDBp0v4J1PoVNgdX/9h3a+9EfmnWvUo1CfokDVbqQS3kSuLGB5gchuBDXPg2Lmc erxW0SioZrmoVsulVdq7RFUC3tRSDwcZa/E+DzlR9GgoHJlOGDi/XD1tVV2Wt1XL zuuWv0MMDWpM5nCcPL+ic9slVUbiVGfuID58T2z9ysoxvc9oVYdbu+3DqcZQGdK9 g3oBckYQrkm4+mTuHUMCLDhJjau2OFlbNAsA5wVmhnSf/GmskZ6qb6Kv4WVefzIq rvjrFDqf4WCXeJXbKNr/F1r0M3gxLV1ncFu2qo6zO7Ciw== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 42rvcw0pdg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 07 Nov 2024 08:08:49 -0800 (PST) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 7 Nov 2024 08:08:48 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 7 Nov 2024 08:08:48 -0800 Received: from hyd1soter3.marvell.com (unknown [10.29.37.12]) by maili.marvell.com (Postfix) with ESMTP id C99E03F7050; Thu, 7 Nov 2024 08:08:44 -0800 (PST) From: Geetha sowjanya To: , CC: , , , , , , , , Subject: [net-next PATCH v12 01/12] octeontx2-pf: RVU representor driver Date: Thu, 7 Nov 2024 21:38:28 +0530 Message-ID: <20241107160839.23707-2-gakula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241107160839.23707-1-gakula@marvell.com> References: <20241107160839.23707-1-gakula@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: qi7MZcc0O31FmbMlBaNA6Nx4wj6LKwB3 X-Proofpoint-GUID: qi7MZcc0O31FmbMlBaNA6Nx4wj6LKwB3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.687,Hydra:6.0.235,FMLib:17.0.607.475 definitions=2020-10-13_15,2020-10-13_02,2020-04-07_01 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Adds basic driver for the RVU representor. Driver on probe does pci specific initialization and does hw resources configuration. Introduces RVU_ESWITCH kernel config to enable/disable the driver. Representor and NIC shares the code but representors netdev support subset of NIC functionality. Hence "otx2_rep_dev" API helps to skip the features initialization that are not supported by the representors. Signed-off-by: Geetha sowjanya Reviewed-by: Simon Horman --- .../net/ethernet/marvell/octeontx2/Kconfig | 8 + .../ethernet/marvell/octeontx2/af/Makefile | 3 +- .../net/ethernet/marvell/octeontx2/af/mbox.h | 8 + .../net/ethernet/marvell/octeontx2/af/rvu.h | 11 ++ .../ethernet/marvell/octeontx2/af/rvu_nix.c | 22 ++- .../ethernet/marvell/octeontx2/af/rvu_rep.c | 48 +++++ .../ethernet/marvell/octeontx2/nic/Makefile | 2 + .../marvell/octeontx2/nic/otx2_common.h | 12 +- .../ethernet/marvell/octeontx2/nic/otx2_pf.c | 20 +- .../net/ethernet/marvell/octeontx2/nic/rep.c | 173 ++++++++++++++++++ .../net/ethernet/marvell/octeontx2/nic/rep.h | 31 ++++ 11 files changed, 326 insertions(+), 12 deletions(-) create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c create mode 100644 drivers/net/ethernet/marvell/octeontx2/nic/rep.c create mode 100644 drivers/net/ethernet/marvell/octeontx2/nic/rep.h diff --git a/drivers/net/ethernet/marvell/octeontx2/Kconfig b/drivers/net/e= thernet/marvell/octeontx2/Kconfig index a32d85d6f599..35c4f5f64f58 100644 --- a/drivers/net/ethernet/marvell/octeontx2/Kconfig +++ b/drivers/net/ethernet/marvell/octeontx2/Kconfig @@ -46,3 +46,11 @@ config OCTEONTX2_VF depends on OCTEONTX2_PF help This driver supports Marvell's OcteonTX2 NIC virtual function. + +config RVU_ESWITCH + tristate "Marvell RVU E-Switch support" + depends on OCTEONTX2_PF + default m + help + This driver supports Marvell's RVU E-Switch that + provides internal SRIOV packet steering and switching. diff --git a/drivers/net/ethernet/marvell/octeontx2/af/Makefile b/drivers/n= et/ethernet/marvell/octeontx2/af/Makefile index 3cf4c8285c90..ccea37847df8 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/Makefile +++ b/drivers/net/ethernet/marvell/octeontx2/af/Makefile @@ -11,4 +11,5 @@ rvu_mbox-y :=3D mbox.o rvu_trace.o rvu_af-y :=3D cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o \ rvu_reg.o rvu_npc.o rvu_debugfs.o ptp.o rvu_npc_fs.o \ rvu_cpt.o rvu_devlink.o rpm.o rvu_cn10k.o rvu_switch.o \ - rvu_sdp.o rvu_npc_hash.o mcs.o mcs_rvu_if.o mcs_cnf10kb.o + rvu_sdp.o rvu_npc_hash.o mcs.o mcs_rvu_if.o mcs_cnf10kb.o \ + rvu_rep.o diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net= /ethernet/marvell/octeontx2/af/mbox.h index 6ea2f3071fe8..e039d11d5ad1 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h @@ -144,6 +144,7 @@ M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_se= tup_req, \ msg_rsp) \ M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \ M(PTP_GET_CAP, 0x00c, ptp_get_cap, msg_req, ptp_get_cap_rsp) \ +M(GET_REP_CNT, 0x00d, get_rep_cnt, msg_req, get_rep_cnt_rsp) \ /* CGX mbox IDs (range 0x200 - 0x3FF) */ \ M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ @@ -1525,6 +1526,13 @@ struct ptp_get_cap_rsp { u64 cap; }; =20 +struct get_rep_cnt_rsp { + struct mbox_msghdr hdr; + u16 rep_cnt; + u16 rep_pf_map[64]; + u64 rsvd; +}; + struct flow_msg { unsigned char dmac[6]; unsigned char smac[6]; diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/= ethernet/marvell/octeontx2/af/rvu.h index 5016ba82e142..425954d26d79 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h @@ -594,6 +594,9 @@ struct rvu { spinlock_t cpt_intr_lock; =20 struct mutex mbox_lock; /* Serialize mbox up and down msgs */ + u16 rep_pcifunc; + int rep_cnt; + u16 *rep2pfvf_map; }; =20 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64= val) @@ -852,6 +855,14 @@ bool is_sdp_pfvf(u16 pcifunc); bool is_sdp_pf(u16 pcifunc); bool is_sdp_vf(struct rvu *rvu, u16 pcifunc); =20 +static inline bool is_rep_dev(struct rvu *rvu, u16 pcifunc) +{ + if (rvu->rep_pcifunc && rvu->rep_pcifunc =3D=3D pcifunc) + return true; + + return false; +} + /* CGX APIs */ static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf) { diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_nix.c index da69350c6f76..723c550dd3cd 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c @@ -31,6 +31,7 @@ static int nix_free_all_bandprof(struct rvu *rvu, u16 pci= func); static void nix_clear_ratelimit_aggr(struct rvu *rvu, struct nix_hw *nix_h= w, u32 leaf_prof); static const char *nix_get_ctx_name(int ctype); +static int nix_get_tx_link(struct rvu *rvu, u16 pcifunc); =20 enum mc_tbl_sz { MC_TBL_SZ_256, @@ -312,7 +313,9 @@ static bool is_valid_txschq(struct rvu *rvu, int blkadd= r, =20 /* TLs aggegating traffic are shared across PF and VFs */ if (lvl >=3D hw->cap.nix_tx_aggr_lvl) { - if (rvu_get_pf(map_func) !=3D rvu_get_pf(pcifunc)) + if ((nix_get_tx_link(rvu, map_func) !=3D + nix_get_tx_link(rvu, pcifunc)) && + (rvu_get_pf(map_func) !=3D rvu_get_pf(pcifunc))) return false; else return true; @@ -1614,6 +1617,12 @@ int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu, cfg =3D NPC_TX_DEF_PKIND; rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_PARSE_CFG(nixlf), cfg); =20 + if (is_rep_dev(rvu, pcifunc)) { + pfvf->tx_chan_base =3D RVU_SWITCH_LBK_CHAN; + pfvf->tx_chan_cnt =3D 1; + goto exit; + } + intf =3D is_lbk_vf(rvu, pcifunc) ? NIX_INTF_TYPE_LBK : NIX_INTF_TYPE_CGX; if (is_sdp_pfvf(pcifunc)) intf =3D NIX_INTF_TYPE_SDP; @@ -1684,6 +1693,9 @@ int rvu_mbox_handler_nix_lf_free(struct rvu *rvu, str= uct nix_lf_free_req *req, if (nixlf < 0) return NIX_AF_ERR_AF_LF_INVALID; =20 + if (is_rep_dev(rvu, pcifunc)) + goto free_lf; + if (req->flags & NIX_LF_DISABLE_FLOWS) rvu_npc_disable_mcam_entries(rvu, pcifunc, nixlf); else @@ -1695,6 +1707,7 @@ int rvu_mbox_handler_nix_lf_free(struct rvu *rvu, str= uct nix_lf_free_req *req, =20 nix_interface_deinit(rvu, pcifunc, nixlf); =20 +free_lf: /* Reset this NIX LF */ err =3D rvu_lf_reset(rvu, block, nixlf); if (err) { @@ -2007,7 +2020,8 @@ static void nix_get_txschq_range(struct rvu *rvu, u16= pcifunc, struct rvu_hwinfo *hw =3D rvu->hw; int pf =3D rvu_get_pf(pcifunc); =20 - if (is_lbk_vf(rvu, pcifunc)) { /* LBK links */ + /* LBK links */ + if (is_lbk_vf(rvu, pcifunc) || is_rep_dev(rvu, pcifunc)) { *start =3D hw->cap.nix_txsch_per_cgx_lmac * link; *end =3D *start + hw->cap.nix_txsch_per_lbk_lmac; } else if (is_pf_cgxmapped(rvu, pf)) { /* CGX links */ @@ -4555,7 +4569,7 @@ int rvu_mbox_handler_nix_set_hw_frs(struct rvu *rvu, = struct nix_frs_cfg *req, if (!nix_hw) return NIX_AF_ERR_INVALID_NIXBLK; =20 - if (is_lbk_vf(rvu, pcifunc)) + if (is_lbk_vf(rvu, pcifunc) || is_rep_dev(rvu, pcifunc)) rvu_get_lbk_link_max_frs(rvu, &max_mtu); else rvu_get_lmac_link_max_frs(rvu, &max_mtu); @@ -4583,6 +4597,8 @@ int rvu_mbox_handler_nix_set_hw_frs(struct rvu *rvu, = struct nix_frs_cfg *req, /* For VFs of PF0 ingress is LBK port, so config LBK link */ pfvf =3D rvu_get_pfvf(rvu, pcifunc); link =3D hw->cgx_links + pfvf->lbkid; + } else if (is_rep_dev(rvu, pcifunc)) { + link =3D hw->cgx_links + 0; } =20 if (link < 0) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_rep.c new file mode 100644 index 000000000000..48410df71e47 --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Marvell RVU Admin Function driver + * + * Copyright (C) 2024 Marvell. + * + */ + +#include +#include +#include +#include +#include + +#include "rvu.h" +#include "rvu_reg.h" + +int rvu_mbox_handler_get_rep_cnt(struct rvu *rvu, struct msg_req *req, + struct get_rep_cnt_rsp *rsp) +{ + int pf, vf, numvfs, hwvf, rep =3D 0; + u16 pcifunc; + + rvu->rep_pcifunc =3D req->hdr.pcifunc; + rsp->rep_cnt =3D rvu->cgx_mapped_pfs + rvu->cgx_mapped_vfs; + rvu->rep_cnt =3D rsp->rep_cnt; + + rvu->rep2pfvf_map =3D devm_kzalloc(rvu->dev, rvu->rep_cnt * + sizeof(u16), GFP_KERNEL); + if (!rvu->rep2pfvf_map) + return -ENOMEM; + + for (pf =3D 0; pf < rvu->hw->total_pfs; pf++) { + if (!is_pf_cgxmapped(rvu, pf)) + continue; + pcifunc =3D pf << RVU_PFVF_PF_SHIFT; + rvu->rep2pfvf_map[rep] =3D pcifunc; + rsp->rep_pf_map[rep] =3D pcifunc; + rep++; + rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); + for (vf =3D 0; vf < numvfs; vf++) { + rvu->rep2pfvf_map[rep] =3D pcifunc | + ((vf + 1) & RVU_PFVF_FUNC_MASK); + rsp->rep_pf_map[rep] =3D rvu->rep2pfvf_map[rep]; + rep++; + } + } + return 0; +} diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/Makefile b/drivers/= net/ethernet/marvell/octeontx2/nic/Makefile index 64a97a0a10ed..dbc971266865 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/Makefile +++ b/drivers/net/ethernet/marvell/octeontx2/nic/Makefile @@ -5,11 +5,13 @@ =20 obj-$(CONFIG_OCTEONTX2_PF) +=3D rvu_nicpf.o otx2_ptp.o obj-$(CONFIG_OCTEONTX2_VF) +=3D rvu_nicvf.o otx2_ptp.o +obj-$(CONFIG_RVU_ESWITCH) +=3D rvu_rep.o =20 rvu_nicpf-y :=3D otx2_pf.o otx2_common.o otx2_txrx.o otx2_ethtool.o \ otx2_flows.o otx2_tc.o cn10k.o otx2_dmac_flt.o \ otx2_devlink.o qos_sq.o qos.o rvu_nicvf-y :=3D otx2_vf.o +rvu_rep-y :=3D rep.o =20 rvu_nicpf-$(CONFIG_DCB) +=3D otx2_dcbnl.o rvu_nicpf-$(CONFIG_MACSEC) +=3D cn10k_macsec.o diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/dri= vers/net/ethernet/marvell/octeontx2/nic/otx2_common.h index 327254e578d5..ed2bbe72647a 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h @@ -29,6 +29,7 @@ #include "otx2_devlink.h" #include #include "qos.h" +#include "rep.h" =20 /* IPv4 flag more fragment bit */ #define IPV4_FLAG_MORE 0x20 @@ -466,6 +467,7 @@ struct otx2_nic { #define OTX2_FLAG_PTP_ONESTEP_SYNC BIT_ULL(15) #define OTX2_FLAG_ADPTV_INT_COAL_ENABLED BIT_ULL(16) #define OTX2_FLAG_TC_MARK_ENABLED BIT_ULL(17) +#define OTX2_FLAG_REP_MODE_ENABLED BIT_ULL(18) u64 flags; u64 *cq_op_addr; =20 @@ -533,11 +535,19 @@ struct otx2_nic { #if IS_ENABLED(CONFIG_MACSEC) struct cn10k_mcs_cfg *macsec_cfg; #endif + +#if IS_ENABLED(CONFIG_RVU_ESWITCH) + struct rep_dev **reps; + int rep_cnt; + u16 rep_pf_map[RVU_MAX_REP]; + u16 esw_mode; +#endif }; =20 static inline bool is_otx2_lbkvf(struct pci_dev *pdev) { - return pdev->device =3D=3D PCI_DEVID_OCTEONTX2_RVU_AFVF; + return (pdev->device =3D=3D PCI_DEVID_OCTEONTX2_RVU_AFVF) || + (pdev->device =3D=3D PCI_DEVID_RVU_REP); } =20 static inline bool is_96xx_A0(struct pci_dev *pdev) diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers= /net/ethernet/marvell/octeontx2/nic/otx2_pf.c index e6b03bad2dba..8905cc6413ac 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c @@ -1016,6 +1016,7 @@ void otx2_disable_mbox_intr(struct otx2_nic *pf) otx2_write64(pf, RVU_PF_INT_ENA_W1C, BIT_ULL(0)); free_irq(vector, pf); } +EXPORT_SYMBOL(otx2_disable_mbox_intr); =20 int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af) { @@ -1076,6 +1077,7 @@ void otx2_pfaf_mbox_destroy(struct otx2_nic *pf) otx2_mbox_destroy(&mbox->mbox); otx2_mbox_destroy(&mbox->mbox_up); } +EXPORT_SYMBOL(otx2_pfaf_mbox_destroy); =20 int otx2_pfaf_mbox_init(struct otx2_nic *pf) { @@ -1496,10 +1498,11 @@ int otx2_init_hw_resources(struct otx2_nic *pf) hw->sqpool_cnt =3D otx2_get_total_tx_queues(pf); hw->pool_cnt =3D hw->rqpool_cnt + hw->sqpool_cnt; =20 - /* Maximum hardware supported transmit length */ - pf->tx_max_pktlen =3D pf->netdev->max_mtu + OTX2_ETH_HLEN; - - pf->rbsize =3D otx2_get_rbuf_size(pf, pf->netdev->mtu); + if (!otx2_rep_dev(pf->pdev)) { + /* Maximum hardware supported transmit length */ + pf->tx_max_pktlen =3D pf->netdev->max_mtu + OTX2_ETH_HLEN; + pf->rbsize =3D otx2_get_rbuf_size(pf, pf->netdev->mtu); + } =20 mutex_lock(&mbox->lock); /* NPA init */ @@ -1627,11 +1630,12 @@ void otx2_free_hw_resources(struct otx2_nic *pf) otx2_pfc_txschq_stop(pf); #endif =20 - otx2_clean_qos_queues(pf); + if (!otx2_rep_dev(pf->pdev)) + otx2_clean_qos_queues(pf); =20 mutex_lock(&mbox->lock); /* Disable backpressure */ - if (!(pf->pcifunc & RVU_PFVF_FUNC_MASK)) + if (!is_otx2_lbkvf(pf->pdev)) otx2_nix_config_bp(pf, false); mutex_unlock(&mbox->lock); =20 @@ -1663,7 +1667,8 @@ void otx2_free_hw_resources(struct otx2_nic *pf) otx2_free_cq_res(pf); =20 /* Free all ingress bandwidth profiles allocated */ - cn10k_free_all_ipolicers(pf); + if (!otx2_rep_dev(pf->pdev)) + cn10k_free_all_ipolicers(pf); =20 mutex_lock(&mbox->lock); /* Reset NIX LF */ @@ -2976,6 +2981,7 @@ int otx2_init_rsrc(struct pci_dev *pdev, struct otx2_= nic *pf) =20 return err; } +EXPORT_SYMBOL(otx2_init_rsrc); =20 static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id) { diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/rep.c b/drivers/net= /ethernet/marvell/octeontx2/nic/rep.c new file mode 100644 index 000000000000..284bceef448a --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/nic/rep.c @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Marvell RVU representor driver + * + * Copyright (C) 2024 Marvell. + * + */ + +#include +#include +#include +#include + +#include "otx2_common.h" +#include "cn10k.h" +#include "otx2_reg.h" +#include "rep.h" + +#define DRV_NAME "rvu_rep" +#define DRV_STRING "Marvell RVU Representor Driver" + +static const struct pci_device_id rvu_rep_id_table[] =3D { + { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_RVU_REP) }, + { } +}; + +MODULE_AUTHOR("Marvell International Ltd."); +MODULE_DESCRIPTION(DRV_STRING); +MODULE_LICENSE("GPL"); +MODULE_DEVICE_TABLE(pci, rvu_rep_id_table); + +static int rvu_get_rep_cnt(struct otx2_nic *priv) +{ + struct get_rep_cnt_rsp *rsp; + struct mbox_msghdr *msghdr; + struct msg_req *req; + int err, rep; + + mutex_lock(&priv->mbox.lock); + req =3D otx2_mbox_alloc_msg_get_rep_cnt(&priv->mbox); + if (!req) { + mutex_unlock(&priv->mbox.lock); + return -ENOMEM; + } + err =3D otx2_sync_mbox_msg(&priv->mbox); + if (err) + goto exit; + + msghdr =3D otx2_mbox_get_rsp(&priv->mbox.mbox, 0, &req->hdr); + if (IS_ERR(msghdr)) { + err =3D PTR_ERR(msghdr); + goto exit; + } + + rsp =3D (struct get_rep_cnt_rsp *)msghdr; + priv->hw.tx_queues =3D rsp->rep_cnt; + priv->hw.rx_queues =3D rsp->rep_cnt; + priv->rep_cnt =3D rsp->rep_cnt; + for (rep =3D 0; rep < priv->rep_cnt; rep++) + priv->rep_pf_map[rep] =3D rsp->rep_pf_map[rep]; + +exit: + mutex_unlock(&priv->mbox.lock); + return err; +} + +static int rvu_rep_probe(struct pci_dev *pdev, const struct pci_device_id = *id) +{ + struct device *dev =3D &pdev->dev; + struct otx2_nic *priv; + struct otx2_hw *hw; + int err; + + err =3D pcim_enable_device(pdev); + if (err) { + dev_err(dev, "Failed to enable PCI device\n"); + return err; + } + + err =3D pci_request_regions(pdev, DRV_NAME); + if (err) { + dev_err(dev, "PCI request regions failed 0x%x\n", err); + return err; + } + + err =3D dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); + if (err) { + dev_err(dev, "DMA mask config failed, abort\n"); + goto err_release_regions; + } + + pci_set_master(pdev); + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) { + err =3D -ENOMEM; + goto err_release_regions; + } + + pci_set_drvdata(pdev, priv); + priv->pdev =3D pdev; + priv->dev =3D dev; + priv->flags |=3D OTX2_FLAG_INTF_DOWN; + priv->flags |=3D OTX2_FLAG_REP_MODE_ENABLED; + + hw =3D &priv->hw; + hw->pdev =3D pdev; + hw->max_queues =3D OTX2_MAX_CQ_CNT; + hw->rbuf_len =3D OTX2_DEFAULT_RBUF_LEN; + hw->xqe_size =3D 128; + + err =3D otx2_init_rsrc(pdev, priv); + if (err) + goto err_release_regions; + + priv->iommu_domain =3D iommu_get_domain_for_dev(dev); + + err =3D rvu_get_rep_cnt(priv); + if (err) + goto err_detach_rsrc; + + return 0; + +err_detach_rsrc: + if (priv->hw.lmt_info) + free_percpu(priv->hw.lmt_info); + if (test_bit(CN10K_LMTST, &priv->hw.cap_flag)) + qmem_free(priv->dev, priv->dync_lmt); + otx2_detach_resources(&priv->mbox); + otx2_disable_mbox_intr(priv); + otx2_pfaf_mbox_destroy(priv); + pci_free_irq_vectors(pdev); +err_release_regions: + pci_set_drvdata(pdev, NULL); + pci_release_regions(pdev); + return err; +} + +static void rvu_rep_remove(struct pci_dev *pdev) +{ + struct otx2_nic *priv =3D pci_get_drvdata(pdev); + + otx2_detach_resources(&priv->mbox); + if (priv->hw.lmt_info) + free_percpu(priv->hw.lmt_info); + if (test_bit(CN10K_LMTST, &priv->hw.cap_flag)) + qmem_free(priv->dev, priv->dync_lmt); + otx2_disable_mbox_intr(priv); + otx2_pfaf_mbox_destroy(priv); + pci_free_irq_vectors(priv->pdev); + pci_set_drvdata(pdev, NULL); + pci_release_regions(pdev); +} + +static struct pci_driver rvu_rep_driver =3D { + .name =3D DRV_NAME, + .id_table =3D rvu_rep_id_table, + .probe =3D rvu_rep_probe, + .remove =3D rvu_rep_remove, + .shutdown =3D rvu_rep_remove, +}; + +static int __init rvu_rep_init_module(void) +{ + return pci_register_driver(&rvu_rep_driver); +} + +static void __exit rvu_rep_cleanup_module(void) +{ + pci_unregister_driver(&rvu_rep_driver); +} + +module_init(rvu_rep_init_module); +module_exit(rvu_rep_cleanup_module); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/rep.h b/drivers/net= /ethernet/marvell/octeontx2/nic/rep.h new file mode 100644 index 000000000000..565e75628df2 --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/nic/rep.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Marvell RVU REPRESENTOR driver + * + * Copyright (C) 2024 Marvell. + * + */ + +#ifndef REP_H +#define REP_H + +#include + +#include "otx2_reg.h" +#include "otx2_txrx.h" +#include "otx2_common.h" + +#define PCI_DEVID_RVU_REP 0xA0E0 + +#define RVU_MAX_REP OTX2_MAX_CQ_CNT +struct rep_dev { + struct otx2_nic *mdev; + struct net_device *netdev; + u16 rep_id; + u16 pcifunc; +}; + +static inline bool otx2_rep_dev(struct pci_dev *pdev) +{ + return pdev->device =3D=3D PCI_DEVID_RVU_REP; +} +#endif /* REP_H */ --=20 2.25.1