From nobody Sun Nov 24 03:06:22 2024 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4BB4E216E1C; Thu, 7 Nov 2024 16:08:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.156.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730995740; cv=none; b=LdEIiGYVH0f2qZ+GEImEvFjOcNL14bu5d37i39Nbxe9xnXE/2S20jo7W+I47mmO2a8BxkrEuSQMP0dI7NT3JjlCP1raIhKnWFK/tXS0lNdtVAN95H6mE4LM5sTCkf/Ccrf2MSSgc/TB3qreXcmOstNQ4jI2xQLQp8zytlX7MNrQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730995740; c=relaxed/simple; bh=V2WDajORA8NZTuPIVpUTKEMx6+F+UMAX2lLG+hNlvxM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=V9kXapOOxcldZvbKUJzDoUEWyhBuuVRRs6RagH/thB+LIBRGg9KpJ5UnG/cBbzsz98l7gZPD9LvL64cexSrbjeCjKINVHb6ZALNE41N/SDmD7SBRKlB8iLmYwZJV6FZMhJ8KC/bo1VcbnqV/s+4ZTeHM0CV8HyAUdl9LoPOq7es= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=iyWm3hM2; arc=none smtp.client-ip=67.231.156.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="iyWm3hM2" Received: from pps.filterd (m0431383.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4A7B7Ye1012527; Thu, 7 Nov 2024 08:08:50 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-type:date:from:in-reply-to:message-id:mime-version :references:subject:to; s=pfpt0220; bh=iXW3AXijVmIH0PhJHdAEbS6KS F0+Mps60E8gJyGgNwA=; b=iyWm3hM2IHRn9JHeZPZOgiYmTuhHwJjtjia7cxo37 qUDBp0v4J1PoVNgdX/9h3a+9EfmnWvUo1CfokDVbqQS3kSuLGB5gchuBDXPg2Lmc erxW0SioZrmoVsulVdq7RFUC3tRSDwcZa/E+DzlR9GgoHJlOGDi/XD1tVV2Wt1XL zuuWv0MMDWpM5nCcPL+ic9slVUbiVGfuID58T2z9ysoxvc9oVYdbu+3DqcZQGdK9 g3oBckYQrkm4+mTuHUMCLDhJjau2OFlbNAsA5wVmhnSf/GmskZ6qb6Kv4WVefzIq rvjrFDqf4WCXeJXbKNr/F1r0M3gxLV1ncFu2qo6zO7Ciw== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 42rvcw0pdg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 07 Nov 2024 08:08:49 -0800 (PST) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 7 Nov 2024 08:08:48 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 7 Nov 2024 08:08:48 -0800 Received: from hyd1soter3.marvell.com (unknown [10.29.37.12]) by maili.marvell.com (Postfix) with ESMTP id C99E03F7050; Thu, 7 Nov 2024 08:08:44 -0800 (PST) From: Geetha sowjanya To: , CC: , , , , , , , , Subject: [net-next PATCH v12 01/12] octeontx2-pf: RVU representor driver Date: Thu, 7 Nov 2024 21:38:28 +0530 Message-ID: <20241107160839.23707-2-gakula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241107160839.23707-1-gakula@marvell.com> References: <20241107160839.23707-1-gakula@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: qi7MZcc0O31FmbMlBaNA6Nx4wj6LKwB3 X-Proofpoint-GUID: qi7MZcc0O31FmbMlBaNA6Nx4wj6LKwB3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.687,Hydra:6.0.235,FMLib:17.0.607.475 definitions=2020-10-13_15,2020-10-13_02,2020-04-07_01 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Adds basic driver for the RVU representor. Driver on probe does pci specific initialization and does hw resources configuration. Introduces RVU_ESWITCH kernel config to enable/disable the driver. Representor and NIC shares the code but representors netdev support subset of NIC functionality. Hence "otx2_rep_dev" API helps to skip the features initialization that are not supported by the representors. Signed-off-by: Geetha sowjanya Reviewed-by: Simon Horman --- .../net/ethernet/marvell/octeontx2/Kconfig | 8 + .../ethernet/marvell/octeontx2/af/Makefile | 3 +- .../net/ethernet/marvell/octeontx2/af/mbox.h | 8 + .../net/ethernet/marvell/octeontx2/af/rvu.h | 11 ++ .../ethernet/marvell/octeontx2/af/rvu_nix.c | 22 ++- .../ethernet/marvell/octeontx2/af/rvu_rep.c | 48 +++++ .../ethernet/marvell/octeontx2/nic/Makefile | 2 + .../marvell/octeontx2/nic/otx2_common.h | 12 +- .../ethernet/marvell/octeontx2/nic/otx2_pf.c | 20 +- .../net/ethernet/marvell/octeontx2/nic/rep.c | 173 ++++++++++++++++++ .../net/ethernet/marvell/octeontx2/nic/rep.h | 31 ++++ 11 files changed, 326 insertions(+), 12 deletions(-) create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c create mode 100644 drivers/net/ethernet/marvell/octeontx2/nic/rep.c create mode 100644 drivers/net/ethernet/marvell/octeontx2/nic/rep.h diff --git a/drivers/net/ethernet/marvell/octeontx2/Kconfig b/drivers/net/e= thernet/marvell/octeontx2/Kconfig index a32d85d6f599..35c4f5f64f58 100644 --- a/drivers/net/ethernet/marvell/octeontx2/Kconfig +++ b/drivers/net/ethernet/marvell/octeontx2/Kconfig @@ -46,3 +46,11 @@ config OCTEONTX2_VF depends on OCTEONTX2_PF help This driver supports Marvell's OcteonTX2 NIC virtual function. + +config RVU_ESWITCH + tristate "Marvell RVU E-Switch support" + depends on OCTEONTX2_PF + default m + help + This driver supports Marvell's RVU E-Switch that + provides internal SRIOV packet steering and switching. diff --git a/drivers/net/ethernet/marvell/octeontx2/af/Makefile b/drivers/n= et/ethernet/marvell/octeontx2/af/Makefile index 3cf4c8285c90..ccea37847df8 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/Makefile +++ b/drivers/net/ethernet/marvell/octeontx2/af/Makefile @@ -11,4 +11,5 @@ rvu_mbox-y :=3D mbox.o rvu_trace.o rvu_af-y :=3D cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o \ rvu_reg.o rvu_npc.o rvu_debugfs.o ptp.o rvu_npc_fs.o \ rvu_cpt.o rvu_devlink.o rpm.o rvu_cn10k.o rvu_switch.o \ - rvu_sdp.o rvu_npc_hash.o mcs.o mcs_rvu_if.o mcs_cnf10kb.o + rvu_sdp.o rvu_npc_hash.o mcs.o mcs_rvu_if.o mcs_cnf10kb.o \ + rvu_rep.o diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net= /ethernet/marvell/octeontx2/af/mbox.h index 6ea2f3071fe8..e039d11d5ad1 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h @@ -144,6 +144,7 @@ M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_se= tup_req, \ msg_rsp) \ M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \ M(PTP_GET_CAP, 0x00c, ptp_get_cap, msg_req, ptp_get_cap_rsp) \ +M(GET_REP_CNT, 0x00d, get_rep_cnt, msg_req, get_rep_cnt_rsp) \ /* CGX mbox IDs (range 0x200 - 0x3FF) */ \ M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ @@ -1525,6 +1526,13 @@ struct ptp_get_cap_rsp { u64 cap; }; =20 +struct get_rep_cnt_rsp { + struct mbox_msghdr hdr; + u16 rep_cnt; + u16 rep_pf_map[64]; + u64 rsvd; +}; + struct flow_msg { unsigned char dmac[6]; unsigned char smac[6]; diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/= ethernet/marvell/octeontx2/af/rvu.h index 5016ba82e142..425954d26d79 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h @@ -594,6 +594,9 @@ struct rvu { spinlock_t cpt_intr_lock; =20 struct mutex mbox_lock; /* Serialize mbox up and down msgs */ + u16 rep_pcifunc; + int rep_cnt; + u16 *rep2pfvf_map; }; =20 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64= val) @@ -852,6 +855,14 @@ bool is_sdp_pfvf(u16 pcifunc); bool is_sdp_pf(u16 pcifunc); bool is_sdp_vf(struct rvu *rvu, u16 pcifunc); =20 +static inline bool is_rep_dev(struct rvu *rvu, u16 pcifunc) +{ + if (rvu->rep_pcifunc && rvu->rep_pcifunc =3D=3D pcifunc) + return true; + + return false; +} + /* CGX APIs */ static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf) { diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_nix.c index da69350c6f76..723c550dd3cd 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c @@ -31,6 +31,7 @@ static int nix_free_all_bandprof(struct rvu *rvu, u16 pci= func); static void nix_clear_ratelimit_aggr(struct rvu *rvu, struct nix_hw *nix_h= w, u32 leaf_prof); static const char *nix_get_ctx_name(int ctype); +static int nix_get_tx_link(struct rvu *rvu, u16 pcifunc); =20 enum mc_tbl_sz { MC_TBL_SZ_256, @@ -312,7 +313,9 @@ static bool is_valid_txschq(struct rvu *rvu, int blkadd= r, =20 /* TLs aggegating traffic are shared across PF and VFs */ if (lvl >=3D hw->cap.nix_tx_aggr_lvl) { - if (rvu_get_pf(map_func) !=3D rvu_get_pf(pcifunc)) + if ((nix_get_tx_link(rvu, map_func) !=3D + nix_get_tx_link(rvu, pcifunc)) && + (rvu_get_pf(map_func) !=3D rvu_get_pf(pcifunc))) return false; else return true; @@ -1614,6 +1617,12 @@ int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu, cfg =3D NPC_TX_DEF_PKIND; rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_PARSE_CFG(nixlf), cfg); =20 + if (is_rep_dev(rvu, pcifunc)) { + pfvf->tx_chan_base =3D RVU_SWITCH_LBK_CHAN; + pfvf->tx_chan_cnt =3D 1; + goto exit; + } + intf =3D is_lbk_vf(rvu, pcifunc) ? NIX_INTF_TYPE_LBK : NIX_INTF_TYPE_CGX; if (is_sdp_pfvf(pcifunc)) intf =3D NIX_INTF_TYPE_SDP; @@ -1684,6 +1693,9 @@ int rvu_mbox_handler_nix_lf_free(struct rvu *rvu, str= uct nix_lf_free_req *req, if (nixlf < 0) return NIX_AF_ERR_AF_LF_INVALID; =20 + if (is_rep_dev(rvu, pcifunc)) + goto free_lf; + if (req->flags & NIX_LF_DISABLE_FLOWS) rvu_npc_disable_mcam_entries(rvu, pcifunc, nixlf); else @@ -1695,6 +1707,7 @@ int rvu_mbox_handler_nix_lf_free(struct rvu *rvu, str= uct nix_lf_free_req *req, =20 nix_interface_deinit(rvu, pcifunc, nixlf); =20 +free_lf: /* Reset this NIX LF */ err =3D rvu_lf_reset(rvu, block, nixlf); if (err) { @@ -2007,7 +2020,8 @@ static void nix_get_txschq_range(struct rvu *rvu, u16= pcifunc, struct rvu_hwinfo *hw =3D rvu->hw; int pf =3D rvu_get_pf(pcifunc); =20 - if (is_lbk_vf(rvu, pcifunc)) { /* LBK links */ + /* LBK links */ + if (is_lbk_vf(rvu, pcifunc) || is_rep_dev(rvu, pcifunc)) { *start =3D hw->cap.nix_txsch_per_cgx_lmac * link; *end =3D *start + hw->cap.nix_txsch_per_lbk_lmac; } else if (is_pf_cgxmapped(rvu, pf)) { /* CGX links */ @@ -4555,7 +4569,7 @@ int rvu_mbox_handler_nix_set_hw_frs(struct rvu *rvu, = struct nix_frs_cfg *req, if (!nix_hw) return NIX_AF_ERR_INVALID_NIXBLK; =20 - if (is_lbk_vf(rvu, pcifunc)) + if (is_lbk_vf(rvu, pcifunc) || is_rep_dev(rvu, pcifunc)) rvu_get_lbk_link_max_frs(rvu, &max_mtu); else rvu_get_lmac_link_max_frs(rvu, &max_mtu); @@ -4583,6 +4597,8 @@ int rvu_mbox_handler_nix_set_hw_frs(struct rvu *rvu, = struct nix_frs_cfg *req, /* For VFs of PF0 ingress is LBK port, so config LBK link */ pfvf =3D rvu_get_pfvf(rvu, pcifunc); link =3D hw->cgx_links + pfvf->lbkid; + } else if (is_rep_dev(rvu, pcifunc)) { + link =3D hw->cgx_links + 0; } =20 if (link < 0) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_rep.c new file mode 100644 index 000000000000..48410df71e47 --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Marvell RVU Admin Function driver + * + * Copyright (C) 2024 Marvell. + * + */ + +#include +#include +#include +#include +#include + +#include "rvu.h" +#include "rvu_reg.h" + +int rvu_mbox_handler_get_rep_cnt(struct rvu *rvu, struct msg_req *req, + struct get_rep_cnt_rsp *rsp) +{ + int pf, vf, numvfs, hwvf, rep =3D 0; + u16 pcifunc; + + rvu->rep_pcifunc =3D req->hdr.pcifunc; + rsp->rep_cnt =3D rvu->cgx_mapped_pfs + rvu->cgx_mapped_vfs; + rvu->rep_cnt =3D rsp->rep_cnt; + + rvu->rep2pfvf_map =3D devm_kzalloc(rvu->dev, rvu->rep_cnt * + sizeof(u16), GFP_KERNEL); + if (!rvu->rep2pfvf_map) + return -ENOMEM; + + for (pf =3D 0; pf < rvu->hw->total_pfs; pf++) { + if (!is_pf_cgxmapped(rvu, pf)) + continue; + pcifunc =3D pf << RVU_PFVF_PF_SHIFT; + rvu->rep2pfvf_map[rep] =3D pcifunc; + rsp->rep_pf_map[rep] =3D pcifunc; + rep++; + rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf); + for (vf =3D 0; vf < numvfs; vf++) { + rvu->rep2pfvf_map[rep] =3D pcifunc | + ((vf + 1) & RVU_PFVF_FUNC_MASK); + rsp->rep_pf_map[rep] =3D rvu->rep2pfvf_map[rep]; + rep++; + } + } + return 0; +} diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/Makefile b/drivers/= net/ethernet/marvell/octeontx2/nic/Makefile index 64a97a0a10ed..dbc971266865 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/Makefile +++ b/drivers/net/ethernet/marvell/octeontx2/nic/Makefile @@ -5,11 +5,13 @@ =20 obj-$(CONFIG_OCTEONTX2_PF) +=3D rvu_nicpf.o otx2_ptp.o obj-$(CONFIG_OCTEONTX2_VF) +=3D rvu_nicvf.o otx2_ptp.o +obj-$(CONFIG_RVU_ESWITCH) +=3D rvu_rep.o =20 rvu_nicpf-y :=3D otx2_pf.o otx2_common.o otx2_txrx.o otx2_ethtool.o \ otx2_flows.o otx2_tc.o cn10k.o otx2_dmac_flt.o \ otx2_devlink.o qos_sq.o qos.o rvu_nicvf-y :=3D otx2_vf.o +rvu_rep-y :=3D rep.o =20 rvu_nicpf-$(CONFIG_DCB) +=3D otx2_dcbnl.o rvu_nicpf-$(CONFIG_MACSEC) +=3D cn10k_macsec.o diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/dri= vers/net/ethernet/marvell/octeontx2/nic/otx2_common.h index 327254e578d5..ed2bbe72647a 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h @@ -29,6 +29,7 @@ #include "otx2_devlink.h" #include #include "qos.h" +#include "rep.h" =20 /* IPv4 flag more fragment bit */ #define IPV4_FLAG_MORE 0x20 @@ -466,6 +467,7 @@ struct otx2_nic { #define OTX2_FLAG_PTP_ONESTEP_SYNC BIT_ULL(15) #define OTX2_FLAG_ADPTV_INT_COAL_ENABLED BIT_ULL(16) #define OTX2_FLAG_TC_MARK_ENABLED BIT_ULL(17) +#define OTX2_FLAG_REP_MODE_ENABLED BIT_ULL(18) u64 flags; u64 *cq_op_addr; =20 @@ -533,11 +535,19 @@ struct otx2_nic { #if IS_ENABLED(CONFIG_MACSEC) struct cn10k_mcs_cfg *macsec_cfg; #endif + +#if IS_ENABLED(CONFIG_RVU_ESWITCH) + struct rep_dev **reps; + int rep_cnt; + u16 rep_pf_map[RVU_MAX_REP]; + u16 esw_mode; +#endif }; =20 static inline bool is_otx2_lbkvf(struct pci_dev *pdev) { - return pdev->device =3D=3D PCI_DEVID_OCTEONTX2_RVU_AFVF; + return (pdev->device =3D=3D PCI_DEVID_OCTEONTX2_RVU_AFVF) || + (pdev->device =3D=3D PCI_DEVID_RVU_REP); } =20 static inline bool is_96xx_A0(struct pci_dev *pdev) diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers= /net/ethernet/marvell/octeontx2/nic/otx2_pf.c index e6b03bad2dba..8905cc6413ac 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c @@ -1016,6 +1016,7 @@ void otx2_disable_mbox_intr(struct otx2_nic *pf) otx2_write64(pf, RVU_PF_INT_ENA_W1C, BIT_ULL(0)); free_irq(vector, pf); } +EXPORT_SYMBOL(otx2_disable_mbox_intr); =20 int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af) { @@ -1076,6 +1077,7 @@ void otx2_pfaf_mbox_destroy(struct otx2_nic *pf) otx2_mbox_destroy(&mbox->mbox); otx2_mbox_destroy(&mbox->mbox_up); } +EXPORT_SYMBOL(otx2_pfaf_mbox_destroy); =20 int otx2_pfaf_mbox_init(struct otx2_nic *pf) { @@ -1496,10 +1498,11 @@ int otx2_init_hw_resources(struct otx2_nic *pf) hw->sqpool_cnt =3D otx2_get_total_tx_queues(pf); hw->pool_cnt =3D hw->rqpool_cnt + hw->sqpool_cnt; =20 - /* Maximum hardware supported transmit length */ - pf->tx_max_pktlen =3D pf->netdev->max_mtu + OTX2_ETH_HLEN; - - pf->rbsize =3D otx2_get_rbuf_size(pf, pf->netdev->mtu); + if (!otx2_rep_dev(pf->pdev)) { + /* Maximum hardware supported transmit length */ + pf->tx_max_pktlen =3D pf->netdev->max_mtu + OTX2_ETH_HLEN; + pf->rbsize =3D otx2_get_rbuf_size(pf, pf->netdev->mtu); + } =20 mutex_lock(&mbox->lock); /* NPA init */ @@ -1627,11 +1630,12 @@ void otx2_free_hw_resources(struct otx2_nic *pf) otx2_pfc_txschq_stop(pf); #endif =20 - otx2_clean_qos_queues(pf); + if (!otx2_rep_dev(pf->pdev)) + otx2_clean_qos_queues(pf); =20 mutex_lock(&mbox->lock); /* Disable backpressure */ - if (!(pf->pcifunc & RVU_PFVF_FUNC_MASK)) + if (!is_otx2_lbkvf(pf->pdev)) otx2_nix_config_bp(pf, false); mutex_unlock(&mbox->lock); =20 @@ -1663,7 +1667,8 @@ void otx2_free_hw_resources(struct otx2_nic *pf) otx2_free_cq_res(pf); =20 /* Free all ingress bandwidth profiles allocated */ - cn10k_free_all_ipolicers(pf); + if (!otx2_rep_dev(pf->pdev)) + cn10k_free_all_ipolicers(pf); =20 mutex_lock(&mbox->lock); /* Reset NIX LF */ @@ -2976,6 +2981,7 @@ int otx2_init_rsrc(struct pci_dev *pdev, struct otx2_= nic *pf) =20 return err; } +EXPORT_SYMBOL(otx2_init_rsrc); =20 static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id) { diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/rep.c b/drivers/net= /ethernet/marvell/octeontx2/nic/rep.c new file mode 100644 index 000000000000..284bceef448a --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/nic/rep.c @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Marvell RVU representor driver + * + * Copyright (C) 2024 Marvell. + * + */ + +#include +#include +#include +#include + +#include "otx2_common.h" +#include "cn10k.h" +#include "otx2_reg.h" +#include "rep.h" + +#define DRV_NAME "rvu_rep" +#define DRV_STRING "Marvell RVU Representor Driver" + +static const struct pci_device_id rvu_rep_id_table[] =3D { + { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_RVU_REP) }, + { } +}; + +MODULE_AUTHOR("Marvell International Ltd."); +MODULE_DESCRIPTION(DRV_STRING); +MODULE_LICENSE("GPL"); +MODULE_DEVICE_TABLE(pci, rvu_rep_id_table); + +static int rvu_get_rep_cnt(struct otx2_nic *priv) +{ + struct get_rep_cnt_rsp *rsp; + struct mbox_msghdr *msghdr; + struct msg_req *req; + int err, rep; + + mutex_lock(&priv->mbox.lock); + req =3D otx2_mbox_alloc_msg_get_rep_cnt(&priv->mbox); + if (!req) { + mutex_unlock(&priv->mbox.lock); + return -ENOMEM; + } + err =3D otx2_sync_mbox_msg(&priv->mbox); + if (err) + goto exit; + + msghdr =3D otx2_mbox_get_rsp(&priv->mbox.mbox, 0, &req->hdr); + if (IS_ERR(msghdr)) { + err =3D PTR_ERR(msghdr); + goto exit; + } + + rsp =3D (struct get_rep_cnt_rsp *)msghdr; + priv->hw.tx_queues =3D rsp->rep_cnt; + priv->hw.rx_queues =3D rsp->rep_cnt; + priv->rep_cnt =3D rsp->rep_cnt; + for (rep =3D 0; rep < priv->rep_cnt; rep++) + priv->rep_pf_map[rep] =3D rsp->rep_pf_map[rep]; + +exit: + mutex_unlock(&priv->mbox.lock); + return err; +} + +static int rvu_rep_probe(struct pci_dev *pdev, const struct pci_device_id = *id) +{ + struct device *dev =3D &pdev->dev; + struct otx2_nic *priv; + struct otx2_hw *hw; + int err; + + err =3D pcim_enable_device(pdev); + if (err) { + dev_err(dev, "Failed to enable PCI device\n"); + return err; + } + + err =3D pci_request_regions(pdev, DRV_NAME); + if (err) { + dev_err(dev, "PCI request regions failed 0x%x\n", err); + return err; + } + + err =3D dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); + if (err) { + dev_err(dev, "DMA mask config failed, abort\n"); + goto err_release_regions; + } + + pci_set_master(pdev); + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) { + err =3D -ENOMEM; + goto err_release_regions; + } + + pci_set_drvdata(pdev, priv); + priv->pdev =3D pdev; + priv->dev =3D dev; + priv->flags |=3D OTX2_FLAG_INTF_DOWN; + priv->flags |=3D OTX2_FLAG_REP_MODE_ENABLED; + + hw =3D &priv->hw; + hw->pdev =3D pdev; + hw->max_queues =3D OTX2_MAX_CQ_CNT; + hw->rbuf_len =3D OTX2_DEFAULT_RBUF_LEN; + hw->xqe_size =3D 128; + + err =3D otx2_init_rsrc(pdev, priv); + if (err) + goto err_release_regions; + + priv->iommu_domain =3D iommu_get_domain_for_dev(dev); + + err =3D rvu_get_rep_cnt(priv); + if (err) + goto err_detach_rsrc; + + return 0; + +err_detach_rsrc: + if (priv->hw.lmt_info) + free_percpu(priv->hw.lmt_info); + if (test_bit(CN10K_LMTST, &priv->hw.cap_flag)) + qmem_free(priv->dev, priv->dync_lmt); + otx2_detach_resources(&priv->mbox); + otx2_disable_mbox_intr(priv); + otx2_pfaf_mbox_destroy(priv); + pci_free_irq_vectors(pdev); +err_release_regions: + pci_set_drvdata(pdev, NULL); + pci_release_regions(pdev); + return err; +} + +static void rvu_rep_remove(struct pci_dev *pdev) +{ + struct otx2_nic *priv =3D pci_get_drvdata(pdev); + + otx2_detach_resources(&priv->mbox); + if (priv->hw.lmt_info) + free_percpu(priv->hw.lmt_info); + if (test_bit(CN10K_LMTST, &priv->hw.cap_flag)) + qmem_free(priv->dev, priv->dync_lmt); + otx2_disable_mbox_intr(priv); + otx2_pfaf_mbox_destroy(priv); + pci_free_irq_vectors(priv->pdev); + pci_set_drvdata(pdev, NULL); + pci_release_regions(pdev); +} + +static struct pci_driver rvu_rep_driver =3D { + .name =3D DRV_NAME, + .id_table =3D rvu_rep_id_table, + .probe =3D rvu_rep_probe, + .remove =3D rvu_rep_remove, + .shutdown =3D rvu_rep_remove, +}; + +static int __init rvu_rep_init_module(void) +{ + return pci_register_driver(&rvu_rep_driver); +} + +static void __exit rvu_rep_cleanup_module(void) +{ + pci_unregister_driver(&rvu_rep_driver); +} + +module_init(rvu_rep_init_module); +module_exit(rvu_rep_cleanup_module); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/rep.h b/drivers/net= /ethernet/marvell/octeontx2/nic/rep.h new file mode 100644 index 000000000000..565e75628df2 --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/nic/rep.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Marvell RVU REPRESENTOR driver + * + * Copyright (C) 2024 Marvell. + * + */ + +#ifndef REP_H +#define REP_H + +#include + +#include "otx2_reg.h" +#include "otx2_txrx.h" +#include "otx2_common.h" + +#define PCI_DEVID_RVU_REP 0xA0E0 + +#define RVU_MAX_REP OTX2_MAX_CQ_CNT +struct rep_dev { + struct otx2_nic *mdev; + struct net_device *netdev; + u16 rep_id; + u16 pcifunc; +}; + +static inline bool otx2_rep_dev(struct pci_dev *pdev) +{ + return pdev->device =3D=3D PCI_DEVID_RVU_REP; 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Thu, 07 Nov 2024 08:08:53 -0800 (PST) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 7 Nov 2024 08:08:52 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 7 Nov 2024 08:08:52 -0800 Received: from hyd1soter3.marvell.com (unknown [10.29.37.12]) by maili.marvell.com (Postfix) with ESMTP id 00CAC3F7050; Thu, 7 Nov 2024 08:08:48 -0800 (PST) From: Geetha sowjanya To: , CC: , , , , , , , , Subject: [net-next PATCH v12 02/12] octeontx2-pf: Create representor netdev Date: Thu, 7 Nov 2024 21:38:29 +0530 Message-ID: <20241107160839.23707-3-gakula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241107160839.23707-1-gakula@marvell.com> References: <20241107160839.23707-1-gakula@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: b9tS6RVIjd1oQILEU_ZAQ_0oj-1swGd0 X-Proofpoint-ORIG-GUID: b9tS6RVIjd1oQILEU_ZAQ_0oj-1swGd0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.687,Hydra:6.0.235,FMLib:17.0.607.475 definitions=2020-10-13_15,2020-10-13_02,2020-04-07_01 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Adds initial devlink support to set/get the switchdev mode. Representor netdevs are created for each rvu devices when the switch mode is set to 'switchdev'. These netdevs are be used to control and configure VFs. Signed-off-by: Geetha sowjanya --- .../marvell/octeontx2/nic/otx2_common.c | 2 + .../marvell/octeontx2/nic/otx2_devlink.c | 49 ++++ .../ethernet/marvell/octeontx2/nic/otx2_pf.c | 7 + .../marvell/octeontx2/nic/otx2_txrx.c | 1 + .../net/ethernet/marvell/octeontx2/nic/rep.c | 223 ++++++++++++++++++ .../net/ethernet/marvell/octeontx2/nic/rep.h | 3 + 6 files changed, 285 insertions(+) diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c b/dri= vers/net/ethernet/marvell/octeontx2/nic/otx2_common.c index 6e0183f0d5a1..8b6e60dde684 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c @@ -246,6 +246,7 @@ int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu) mutex_unlock(&pfvf->mbox.lock); return err; } +EXPORT_SYMBOL(otx2_hw_set_mtu); =20 int otx2_config_pause_frm(struct otx2_nic *pfvf) { @@ -1782,6 +1783,7 @@ void otx2_free_cints(struct otx2_nic *pfvf, int n) free_irq(vector, &qset->napi[qidx]); } } +EXPORT_SYMBOL(otx2_free_cints); =20 void otx2_set_cints_affinity(struct otx2_nic *pfvf) { diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_devlink.c b/dr= ivers/net/ethernet/marvell/octeontx2/nic/otx2_devlink.c index 53f14aa944bd..33ec9a7f7c03 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_devlink.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_devlink.c @@ -141,7 +141,56 @@ static const struct devlink_param otx2_dl_params[] =3D= { otx2_dl_ucast_flt_cnt_validate), }; =20 +#ifdef CONFIG_RVU_ESWITCH +static int otx2_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mod= e) +{ + struct otx2_devlink *otx2_dl =3D devlink_priv(devlink); + struct otx2_nic *pfvf =3D otx2_dl->pfvf; + + if (!otx2_rep_dev(pfvf->pdev)) + return -EOPNOTSUPP; + + *mode =3D pfvf->esw_mode; + + return 0; +} + +static int otx2_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode, + struct netlink_ext_ack *extack) +{ + struct otx2_devlink *otx2_dl =3D devlink_priv(devlink); + struct otx2_nic *pfvf =3D otx2_dl->pfvf; + int ret =3D 0; + + if (!otx2_rep_dev(pfvf->pdev)) + return -EOPNOTSUPP; + + if (pfvf->esw_mode =3D=3D mode) + return 0; + + switch (mode) { + case DEVLINK_ESWITCH_MODE_LEGACY: + rvu_rep_destroy(pfvf); + break; + case DEVLINK_ESWITCH_MODE_SWITCHDEV: + ret =3D rvu_rep_create(pfvf, extack); + break; + default: + return -EINVAL; + } + + if (!ret) + pfvf->esw_mode =3D mode; + + return ret; +} +#endif + static const struct devlink_ops otx2_devlink_ops =3D { +#ifdef CONFIG_RVU_ESWITCH + .eswitch_mode_get =3D otx2_devlink_eswitch_mode_get, + .eswitch_mode_set =3D otx2_devlink_eswitch_mode_set, +#endif }; =20 int otx2_register_dl(struct otx2_nic *pfvf) diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers= /net/ethernet/marvell/octeontx2/nic/otx2_pf.c index 8905cc6413ac..c35327a10bc9 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c @@ -1400,6 +1400,7 @@ irqreturn_t otx2_cq_intr_handler(int irq, void *cq_ir= q) =20 return IRQ_HANDLED; } +EXPORT_SYMBOL(otx2_cq_intr_handler); =20 void otx2_disable_napi(struct otx2_nic *pf) { @@ -1417,6 +1418,7 @@ void otx2_disable_napi(struct otx2_nic *pf) netif_napi_del(&cq_poll->napi); } } +EXPORT_SYMBOL(otx2_disable_napi); =20 static void otx2_free_cq_res(struct otx2_nic *pf) { @@ -1607,6 +1609,7 @@ int otx2_init_hw_resources(struct otx2_nic *pf) mutex_unlock(&mbox->lock); return err; } +EXPORT_SYMBOL(otx2_init_hw_resources); =20 void otx2_free_hw_resources(struct otx2_nic *pf) { @@ -1696,6 +1699,7 @@ void otx2_free_hw_resources(struct otx2_nic *pf) } mutex_unlock(&mbox->lock); } +EXPORT_SYMBOL(otx2_free_hw_resources); =20 static bool otx2_promisc_use_mce_list(struct otx2_nic *pfvf) { @@ -1789,6 +1793,7 @@ void otx2_free_queue_mem(struct otx2_qset *qset) kfree(qset->napi); qset->napi =3D NULL; } +EXPORT_SYMBOL(otx2_free_queue_mem); =20 int otx2_alloc_queue_mem(struct otx2_nic *pf) { @@ -1835,6 +1840,7 @@ int otx2_alloc_queue_mem(struct otx2_nic *pf) otx2_free_queue_mem(qset); return -ENOMEM; } +EXPORT_SYMBOL(otx2_alloc_queue_mem); =20 int otx2_open(struct net_device *netdev) { @@ -2866,6 +2872,7 @@ int otx2_realloc_msix_vectors(struct otx2_nic *pf) =20 return otx2_register_mbox_intr(pf, false); } +EXPORT_SYMBOL(otx2_realloc_msix_vectors); =20 static int otx2_sriov_vfcfg_init(struct otx2_nic *pf) { diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c b/drive= rs/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c index 7aaf32e9aa95..9b4e4c5b1468 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c @@ -594,6 +594,7 @@ int otx2_napi_handler(struct napi_struct *napi, int bud= get) } return workdone; } +EXPORT_SYMBOL(otx2_napi_handler); =20 void otx2_sqe_flush(void *dev, struct otx2_snd_queue *sq, int size, int qidx) diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/rep.c b/drivers/net= /ethernet/marvell/octeontx2/nic/rep.c index 284bceef448a..fda01a485b61 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/rep.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/rep.c @@ -28,6 +28,222 @@ MODULE_DESCRIPTION(DRV_STRING); MODULE_LICENSE("GPL"); MODULE_DEVICE_TABLE(pci, rvu_rep_id_table); =20 +static int rvu_rep_napi_init(struct otx2_nic *priv, + struct netlink_ext_ack *extack) +{ + struct otx2_qset *qset =3D &priv->qset; + struct otx2_cq_poll *cq_poll =3D NULL; + struct otx2_hw *hw =3D &priv->hw; + int err =3D 0, qidx, vec; + char *irq_name; + + qset->napi =3D kcalloc(hw->cint_cnt, sizeof(*cq_poll), GFP_KERNEL); + if (!qset->napi) + return -ENOMEM; + + /* Register NAPI handler */ + for (qidx =3D 0; qidx < hw->cint_cnt; qidx++) { + cq_poll =3D &qset->napi[qidx]; + cq_poll->cint_idx =3D qidx; + cq_poll->cq_ids[CQ_RX] =3D + (qidx < hw->rx_queues) ? qidx : CINT_INVALID_CQ; + cq_poll->cq_ids[CQ_TX] =3D (qidx < hw->tx_queues) ? + qidx + hw->rx_queues : + CINT_INVALID_CQ; + cq_poll->cq_ids[CQ_XDP] =3D CINT_INVALID_CQ; + cq_poll->cq_ids[CQ_QOS] =3D CINT_INVALID_CQ; + + cq_poll->dev =3D (void *)priv; + netif_napi_add(priv->reps[qidx]->netdev, &cq_poll->napi, + otx2_napi_handler); + napi_enable(&cq_poll->napi); + } + /* Register CQ IRQ handlers */ + vec =3D hw->nix_msixoff + NIX_LF_CINT_VEC_START; + for (qidx =3D 0; qidx < hw->cint_cnt; qidx++) { + irq_name =3D &hw->irq_name[vec * NAME_SIZE]; + + snprintf(irq_name, NAME_SIZE, "rep%d-rxtx-%d", qidx, qidx); + + err =3D request_irq(pci_irq_vector(priv->pdev, vec), + otx2_cq_intr_handler, 0, irq_name, + &qset->napi[qidx]); + if (err) { + NL_SET_ERR_MSG_FMT_MOD(extack, + "RVU REP IRQ registration failed for CQ%d", + qidx); + goto err_free_cints; + } + vec++; + + /* Enable CQ IRQ */ + otx2_write64(priv, NIX_LF_CINTX_INT(qidx), BIT_ULL(0)); + otx2_write64(priv, NIX_LF_CINTX_ENA_W1S(qidx), BIT_ULL(0)); + } + priv->flags &=3D ~OTX2_FLAG_INTF_DOWN; + return 0; + +err_free_cints: + otx2_free_cints(priv, qidx); + otx2_disable_napi(priv); + return err; +} + +static void rvu_rep_free_cq_rsrc(struct otx2_nic *priv) +{ + struct otx2_qset *qset =3D &priv->qset; + struct otx2_cq_poll *cq_poll =3D NULL; + int qidx, vec; + + /* Cleanup CQ NAPI and IRQ */ + vec =3D priv->hw.nix_msixoff + NIX_LF_CINT_VEC_START; + for (qidx =3D 0; qidx < priv->hw.cint_cnt; qidx++) { + /* Disable interrupt */ + otx2_write64(priv, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); + + synchronize_irq(pci_irq_vector(priv->pdev, vec)); + + cq_poll =3D &qset->napi[qidx]; + napi_synchronize(&cq_poll->napi); + vec++; + } + otx2_free_cints(priv, priv->hw.cint_cnt); + otx2_disable_napi(priv); +} + +static void rvu_rep_rsrc_free(struct otx2_nic *priv) +{ + struct otx2_qset *qset =3D &priv->qset; + struct delayed_work *work; + int wrk; + + for (wrk =3D 0; wrk < priv->qset.cq_cnt; wrk++) { + work =3D &priv->refill_wrk[wrk].pool_refill_work; + cancel_delayed_work_sync(work); + } + devm_kfree(priv->dev, priv->refill_wrk); + + otx2_free_hw_resources(priv); + otx2_free_queue_mem(qset); +} + +static int rvu_rep_rsrc_init(struct otx2_nic *priv) +{ + struct otx2_qset *qset =3D &priv->qset; + int err; + + err =3D otx2_alloc_queue_mem(priv); + if (err) + return err; + + priv->hw.max_mtu =3D otx2_get_max_mtu(priv); + priv->tx_max_pktlen =3D priv->hw.max_mtu + OTX2_ETH_HLEN; + priv->rbsize =3D ALIGN(priv->hw.rbuf_len, OTX2_ALIGN) + OTX2_HEAD_ROOM; + + err =3D otx2_init_hw_resources(priv); + if (err) + goto err_free_rsrc; + + /* Set maximum frame size allowed in HW */ + err =3D otx2_hw_set_mtu(priv, priv->hw.max_mtu); + if (err) { + dev_err(priv->dev, "Failed to set HW MTU\n"); + goto err_free_rsrc; + } + return 0; + +err_free_rsrc: + otx2_free_hw_resources(priv); + otx2_free_queue_mem(qset); + return err; +} + +void rvu_rep_destroy(struct otx2_nic *priv) +{ + struct rep_dev *rep; + int rep_id; + + priv->flags |=3D OTX2_FLAG_INTF_DOWN; + rvu_rep_free_cq_rsrc(priv); + for (rep_id =3D 0; rep_id < priv->rep_cnt; rep_id++) { + rep =3D priv->reps[rep_id]; + unregister_netdev(rep->netdev); + free_netdev(rep->netdev); + } + kfree(priv->reps); + rvu_rep_rsrc_free(priv); +} + +int rvu_rep_create(struct otx2_nic *priv, struct netlink_ext_ack *extack) +{ + int rep_cnt =3D priv->rep_cnt; + struct net_device *ndev; + struct rep_dev *rep; + int rep_id, err; + u16 pcifunc; + + err =3D rvu_rep_rsrc_init(priv); + if (err) + return -ENOMEM; + + priv->reps =3D kcalloc(rep_cnt, sizeof(struct rep_dev *), GFP_KERNEL); + if (!priv->reps) + return -ENOMEM; + + for (rep_id =3D 0; rep_id < rep_cnt; rep_id++) { + ndev =3D alloc_etherdev(sizeof(*rep)); + if (!ndev) { + NL_SET_ERR_MSG_FMT_MOD(extack, + "PFVF representor:%d creation failed", + rep_id); + err =3D -ENOMEM; + goto exit; + } + + rep =3D netdev_priv(ndev); + priv->reps[rep_id] =3D rep; + rep->mdev =3D priv; + rep->netdev =3D ndev; + rep->rep_id =3D rep_id; + + ndev->min_mtu =3D OTX2_MIN_MTU; + ndev->max_mtu =3D priv->hw.max_mtu; + pcifunc =3D priv->rep_pf_map[rep_id]; + rep->pcifunc =3D pcifunc; + + snprintf(ndev->name, sizeof(ndev->name), "Rpf%dvf%d", + rvu_get_pf(pcifunc), (pcifunc & RVU_PFVF_FUNC_MASK)); + + ndev->hw_features =3D (NETIF_F_RXCSUM | NETIF_F_IP_CSUM | + NETIF_F_IPV6_CSUM | NETIF_F_RXHASH | + NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6); + + ndev->features |=3D ndev->hw_features; + eth_hw_addr_random(ndev); + err =3D register_netdev(ndev); + if (err) { + NL_SET_ERR_MSG_MOD(extack, + "PFVF reprentator registration failed"); + free_netdev(ndev); + goto exit; + } + } + err =3D rvu_rep_napi_init(priv, extack); + if (err) + goto exit; + + return 0; +exit: + while (--rep_id >=3D 0) { + rep =3D priv->reps[rep_id]; + unregister_netdev(rep->netdev); + free_netdev(rep->netdev); + } + kfree(priv->reps); + rvu_rep_rsrc_free(priv); + return err; +} + static int rvu_get_rep_cnt(struct otx2_nic *priv) { struct get_rep_cnt_rsp *rsp; @@ -118,6 +334,10 @@ static int rvu_rep_probe(struct pci_dev *pdev, const s= truct pci_device_id *id) if (err) goto err_detach_rsrc; =20 + err =3D otx2_register_dl(priv); + if (err) + goto err_detach_rsrc; + return 0; =20 err_detach_rsrc: @@ -139,6 +359,9 @@ static void rvu_rep_remove(struct pci_dev *pdev) { struct otx2_nic *priv =3D pci_get_drvdata(pdev); =20 + otx2_unregister_dl(priv); + if (!(priv->flags & OTX2_FLAG_INTF_DOWN)) + rvu_rep_destroy(priv); otx2_detach_resources(&priv->mbox); if (priv->hw.lmt_info) free_percpu(priv->hw.lmt_info); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/rep.h b/drivers/net= /ethernet/marvell/octeontx2/nic/rep.h index 565e75628df2..c04874c4d4c6 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/rep.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/rep.h @@ -28,4 +28,7 @@ static inline bool otx2_rep_dev(struct pci_dev *pdev) { return pdev->device =3D=3D PCI_DEVID_RVU_REP; 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Thu, 7 Nov 2024 08:08:56 -0800 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 7 Nov 2024 08:08:56 -0800 Received: from hyd1soter3.marvell.com (unknown [10.29.37.12]) by maili.marvell.com (Postfix) with ESMTP id E20343F7050; Thu, 7 Nov 2024 08:08:52 -0800 (PST) From: Geetha sowjanya To: , CC: , , , , , , , , Subject: [net-next PATCH v12 03/12] octeontx2-pf: Add basic net_device_ops Date: Thu, 7 Nov 2024 21:38:30 +0530 Message-ID: <20241107160839.23707-4-gakula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241107160839.23707-1-gakula@marvell.com> References: <20241107160839.23707-1-gakula@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: NCImYnXRvAYHVdt-l75o9SYaBvILWWI4 X-Proofpoint-ORIG-GUID: NCImYnXRvAYHVdt-l75o9SYaBvILWWI4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.687,Hydra:6.0.235,FMLib:17.0.607.475 definitions=2020-10-13_15,2020-10-13_02,2020-04-07_01 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Implements basic set of net_device_ops. Signed-off-by: Geetha sowjanya Reviewed-by: Simon Horman --- .../ethernet/marvell/octeontx2/nic/otx2_pf.c | 2 +- .../marvell/octeontx2/nic/otx2_txrx.c | 28 +++++++---- .../marvell/octeontx2/nic/otx2_txrx.h | 3 +- .../ethernet/marvell/octeontx2/nic/otx2_vf.c | 2 +- .../net/ethernet/marvell/octeontx2/nic/rep.c | 46 +++++++++++++++++++ 5 files changed, 70 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers= /net/ethernet/marvell/octeontx2/nic/otx2_pf.c index c35327a10bc9..41480e23ae4d 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c @@ -2116,7 +2116,7 @@ static netdev_tx_t otx2_xmit(struct sk_buff *skb, str= uct net_device *netdev) sq =3D &pf->qset.sq[sq_idx]; txq =3D netdev_get_tx_queue(netdev, qidx); =20 - if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) { + if (!otx2_sq_append_skb(pf, txq, sq, skb, qidx)) { netif_tx_stop_queue(txq); =20 /* Check again, incase SQBs got freed up */ diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c b/drive= rs/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c index 9b4e4c5b1468..04bc06a80e23 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c @@ -376,9 +376,11 @@ static void otx2_rcv_pkt_handler(struct otx2_nic *pfvf, } otx2_set_rxhash(pfvf, cqe, skb); =20 - skb_record_rx_queue(skb, cq->cq_idx); - if (pfvf->netdev->features & NETIF_F_RXCSUM) - skb->ip_summed =3D CHECKSUM_UNNECESSARY; + if (!(pfvf->flags & OTX2_FLAG_REP_MODE_ENABLED)) { + skb_record_rx_queue(skb, cq->cq_idx); + if (pfvf->netdev->features & NETIF_F_RXCSUM) + skb->ip_summed =3D CHECKSUM_UNNECESSARY; + } =20 if (pfvf->flags & OTX2_FLAG_TC_MARK_ENABLED) skb->mark =3D parse->match_id; @@ -453,6 +455,7 @@ static int otx2_tx_napi_handler(struct otx2_nic *pfvf, int tx_pkts =3D 0, tx_bytes =3D 0, qidx; struct otx2_snd_queue *sq; struct nix_cqe_tx_s *cqe; + struct net_device *ndev; int processed_cqe =3D 0; =20 if (cq->pend_cqe >=3D budget) @@ -493,6 +496,13 @@ static int otx2_tx_napi_handler(struct otx2_nic *pfvf, otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR, ((u64)cq->cq_idx << 32) | processed_cqe); =20 +#if IS_ENABLED(CONFIG_RVU_ESWITCH) + if (pfvf->flags & OTX2_FLAG_REP_MODE_ENABLED) + ndev =3D pfvf->reps[qidx]->netdev; + else +#endif + ndev =3D pfvf->netdev; + if (likely(tx_pkts)) { struct netdev_queue *txq; =20 @@ -500,12 +510,14 @@ static int otx2_tx_napi_handler(struct otx2_nic *pfvf, =20 if (qidx >=3D pfvf->hw.tx_queues) qidx -=3D pfvf->hw.xdp_queues; - txq =3D netdev_get_tx_queue(pfvf->netdev, qidx); + if (pfvf->flags & OTX2_FLAG_REP_MODE_ENABLED) + qidx =3D 0; + txq =3D netdev_get_tx_queue(ndev, qidx); netdev_tx_completed_queue(txq, tx_pkts, tx_bytes); /* Check if queue was stopped earlier due to ring full */ smp_mb(); if (netif_tx_queue_stopped(txq) && - netif_carrier_ok(pfvf->netdev)) + netif_carrier_ok(ndev)) netif_tx_wake_queue(txq); } return 0; @@ -1142,13 +1154,13 @@ static void otx2_set_txtstamp(struct otx2_nic *pfvf= , struct sk_buff *skb, } } =20 -bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *= sq, +bool otx2_sq_append_skb(void *dev, struct netdev_queue *txq, + struct otx2_snd_queue *sq, struct sk_buff *skb, u16 qidx) { - struct netdev_queue *txq =3D netdev_get_tx_queue(netdev, qidx); - struct otx2_nic *pfvf =3D netdev_priv(netdev); int offset, num_segs, free_desc; struct nix_sqe_hdr_s *sqe_hdr; + struct otx2_nic *pfvf =3D dev; =20 /* Check if there is enough room between producer * and consumer index. diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h b/drive= rs/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h index 3f1d2655ff77..e1db5f961877 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h @@ -167,7 +167,8 @@ static inline u64 otx2_iova_to_phys(void *iommu_domain,= dma_addr_t dma_addr) } =20 int otx2_napi_handler(struct napi_struct *napi, int budget); -bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *= sq, +bool otx2_sq_append_skb(void *dev, struct netdev_queue *txq, + struct otx2_snd_queue *sq, struct sk_buff *skb, u16 qidx); void cn10k_sqe_flush(void *dev, struct otx2_snd_queue *sq, int size, int qidx); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c b/drivers= /net/ethernet/marvell/octeontx2/nic/otx2_vf.c index c4e6c78a8deb..0486fca8b573 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c @@ -395,7 +395,7 @@ static netdev_tx_t otx2vf_xmit(struct sk_buff *skb, str= uct net_device *netdev) sq =3D &vf->qset.sq[qidx]; txq =3D netdev_get_tx_queue(netdev, qidx); =20 - if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) { + if (!otx2_sq_append_skb(vf, txq, sq, skb, qidx)) { netif_tx_stop_queue(txq); =20 /* Check again, incase SQBs got freed up */ diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/rep.c b/drivers/net= /ethernet/marvell/octeontx2/nic/rep.c index fda01a485b61..d32f685bb25e 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/rep.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/rep.c @@ -28,6 +28,51 @@ MODULE_DESCRIPTION(DRV_STRING); MODULE_LICENSE("GPL"); MODULE_DEVICE_TABLE(pci, rvu_rep_id_table); =20 +static netdev_tx_t rvu_rep_xmit(struct sk_buff *skb, struct net_device *de= v) +{ + struct rep_dev *rep =3D netdev_priv(dev); + struct otx2_nic *pf =3D rep->mdev; + struct otx2_snd_queue *sq; + struct netdev_queue *txq; + + sq =3D &pf->qset.sq[rep->rep_id]; + txq =3D netdev_get_tx_queue(dev, 0); + + if (!otx2_sq_append_skb(pf, txq, sq, skb, rep->rep_id)) { + netif_tx_stop_queue(txq); + + /* Check again, in case SQBs got freed up */ + smp_mb(); + if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb) + > sq->sqe_thresh) + netif_tx_wake_queue(txq); + + return NETDEV_TX_BUSY; + } + return NETDEV_TX_OK; +} + +static int rvu_rep_open(struct net_device *dev) +{ + netif_carrier_on(dev); + netif_tx_start_all_queues(dev); + return 0; +} + +static int rvu_rep_stop(struct net_device *dev) +{ + netif_carrier_off(dev); + netif_tx_disable(dev); + + return 0; +} + +static const struct net_device_ops rvu_rep_netdev_ops =3D { + .ndo_open =3D rvu_rep_open, + .ndo_stop =3D rvu_rep_stop, + .ndo_start_xmit =3D rvu_rep_xmit, +}; + static int rvu_rep_napi_init(struct otx2_nic *priv, struct netlink_ext_ack *extack) { @@ -208,6 +253,7 @@ int rvu_rep_create(struct otx2_nic *priv, struct netlin= k_ext_ack *extack) =20 ndev->min_mtu =3D OTX2_MIN_MTU; ndev->max_mtu =3D priv->hw.max_mtu; + ndev->netdev_ops =3D &rvu_rep_netdev_ops; pcifunc =3D priv->rep_pf_map[rep_id]; rep->pcifunc =3D pcifunc; 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Thu, 07 Nov 2024 08:09:02 -0800 (PST) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 7 Nov 2024 08:09:00 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 7 Nov 2024 08:09:00 -0800 Received: from hyd1soter3.marvell.com (unknown [10.29.37.12]) by maili.marvell.com (Postfix) with ESMTP id 18C873F7050; Thu, 7 Nov 2024 08:08:56 -0800 (PST) From: Geetha sowjanya To: , CC: , , , , , , , , Subject: [net-next PATCH v12 04/12] octeontx2-af: Add packet path between representor and VF Date: Thu, 7 Nov 2024 21:38:31 +0530 Message-ID: <20241107160839.23707-5-gakula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241107160839.23707-1-gakula@marvell.com> References: <20241107160839.23707-1-gakula@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: rcDp-K5g89hXKFVdTmeIhVXeHJ3E5L3- X-Proofpoint-GUID: rcDp-K5g89hXKFVdTmeIhVXeHJ3E5L3- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.687,Hydra:6.0.235,FMLib:17.0.607.475 definitions=2020-10-13_15,2020-10-13_02,2020-04-07_01 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Current HW, do not support in-built switch which will forward pkts between representee and representor. When representor is put under a bridge and pkts needs to be sent to representee, then pkts from representor are sent on a HW internal loopback channel, which again will be punted to ingress pkt parser. Now the rules that this patch installs are the MCAM filters/rules which will match against these pkts and forward them to representee. The rules that this patch installs are for basic representor <=3D> representee path similar to Tun/TAP between VM and Host. Signed-off-by: Geetha sowjanya Reviewed-by: Simon Horman --- .../net/ethernet/marvell/octeontx2/af/mbox.h | 8 + .../net/ethernet/marvell/octeontx2/af/rvu.h | 8 +- .../marvell/octeontx2/af/rvu_devlink.c | 3 + .../ethernet/marvell/octeontx2/af/rvu_nix.c | 7 +- .../ethernet/marvell/octeontx2/af/rvu_reg.h | 1 + .../ethernet/marvell/octeontx2/af/rvu_rep.c | 241 ++++++++++++++++++ .../marvell/octeontx2/af/rvu_switch.c | 20 +- .../net/ethernet/marvell/octeontx2/nic/rep.c | 18 ++ 8 files changed, 298 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net= /ethernet/marvell/octeontx2/af/mbox.h index e039d11d5ad1..10d5712b0077 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h @@ -145,6 +145,7 @@ M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_se= tup_req, \ M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \ M(PTP_GET_CAP, 0x00c, ptp_get_cap, msg_req, ptp_get_cap_rsp) \ M(GET_REP_CNT, 0x00d, get_rep_cnt, msg_req, get_rep_cnt_rsp) \ +M(ESW_CFG, 0x00e, esw_cfg, esw_cfg_req, msg_rsp) \ /* CGX mbox IDs (range 0x200 - 0x3FF) */ \ M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ @@ -1533,6 +1534,12 @@ struct get_rep_cnt_rsp { u64 rsvd; }; =20 +struct esw_cfg_req { + struct mbox_msghdr hdr; + u8 ena; + u64 rsvd; +}; + struct flow_msg { unsigned char dmac[6]; unsigned char smac[6]; @@ -1571,6 +1578,7 @@ struct flow_msg { u8 icmp_type; u8 icmp_code; __be16 tcp_flags; + u16 sq_id; }; =20 struct npc_install_flow_req { diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/= ethernet/marvell/octeontx2/af/rvu.h index 425954d26d79..ceca9b897336 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h @@ -597,6 +597,7 @@ struct rvu { u16 rep_pcifunc; int rep_cnt; u16 *rep2pfvf_map; + u8 rep_mode; }; =20 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64= val) @@ -1056,7 +1057,8 @@ int rvu_ndc_fix_locked_cacheline(struct rvu *rvu, int= blkaddr); /* RVU Switch */ void rvu_switch_enable(struct rvu *rvu); void rvu_switch_disable(struct rvu *rvu); -void rvu_switch_update_rules(struct rvu *rvu, u16 pcifunc); +void rvu_switch_update_rules(struct rvu *rvu, u16 pcifunc, bool ena); +void rvu_switch_enable_lbk_link(struct rvu *rvu, u16 pcifunc, bool ena); =20 int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir, u64 pkind, u8 var_len_off, u8 var_len_off_mask, @@ -1069,4 +1071,8 @@ int rvu_mcs_flr_handler(struct rvu *rvu, u16 pcifunc); void rvu_mcs_ptp_cfg(struct rvu *rvu, u8 rpm_id, u8 lmac_id, bool ena); void rvu_mcs_exit(struct rvu *rvu); =20 +/* Representor APIs */ +int rvu_rep_pf_init(struct rvu *rvu); +int rvu_rep_install_mcam_rules(struct rvu *rvu); +void rvu_rep_update_rules(struct rvu *rvu, u16 pcifunc, bool ena); #endif /* RVU_H */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c b/driv= ers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c index 7498ab429963..7a6a2f29f392 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c @@ -1468,6 +1468,9 @@ static int rvu_devlink_eswitch_mode_get(struct devlin= k *devlink, u16 *mode) struct rvu *rvu =3D rvu_dl->rvu; struct rvu_switch *rswitch; =20 + if (rvu->rep_mode) + return -EOPNOTSUPP; + rswitch =3D &rvu->rswitch; *mode =3D rswitch->mode; =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_nix.c index 723c550dd3cd..673e4991fe23 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c @@ -2774,7 +2774,7 @@ void rvu_nix_tx_tl2_cfg(struct rvu *rvu, int blkaddr,= u16 pcifunc, int schq; u64 cfg; =20 - if (!is_pf_cgxmapped(rvu, pf)) + if (!is_pf_cgxmapped(rvu, pf) && !is_rep_dev(rvu, pcifunc)) return; =20 cfg =3D enable ? (BIT_ULL(12) | RVU_SWITCH_LBK_CHAN) : 0; @@ -4407,8 +4407,6 @@ int rvu_mbox_handler_nix_set_mac_addr(struct rvu *rvu, if (test_bit(PF_SET_VF_TRUSTED, &pfvf->flags) && from_vf) ether_addr_copy(pfvf->default_mac, req->mac_addr); =20 - rvu_switch_update_rules(rvu, pcifunc); - return 0; } =20 @@ -5198,7 +5196,7 @@ int rvu_mbox_handler_nix_lf_start_rx(struct rvu *rvu,= struct msg_req *req, pfvf =3D rvu_get_pfvf(rvu, pcifunc); set_bit(NIXLF_INITIALIZED, &pfvf->flags); =20 - rvu_switch_update_rules(rvu, pcifunc); + rvu_switch_update_rules(rvu, pcifunc, true); =20 return rvu_cgx_start_stop_io(rvu, pcifunc, true); } @@ -5226,6 +5224,7 @@ int rvu_mbox_handler_nix_lf_stop_rx(struct rvu *rvu, = struct msg_req *req, if (err) return err; =20 + rvu_switch_update_rules(rvu, pcifunc, false); rvu_cgx_tx_enable(rvu, pcifunc, true); =20 return 0; diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_reg.h index 2b299fa85159..62cdc714ba57 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h @@ -445,6 +445,7 @@ =20 #define NIX_CONST_MAX_BPIDS GENMASK_ULL(23, 12) #define NIX_CONST_SDP_CHANS GENMASK_ULL(11, 0) +#define NIX_VLAN_ETYPE_MASK GENMASK_ULL(63, 48) =20 #define NIX_AF_MDQ_PARENT_MASK GENMASK_ULL(24, 16) #define NIX_AF_TL4_PARENT_MASK GENMASK_ULL(23, 16) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_rep.c index 48410df71e47..c1132d68259e 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c @@ -14,6 +14,247 @@ #include "rvu.h" #include "rvu_reg.h" =20 +static u16 rvu_rep_get_vlan_id(struct rvu *rvu, u16 pcifunc) +{ + int id; + + for (id =3D 0; id < rvu->rep_cnt; id++) + if (rvu->rep2pfvf_map[id] =3D=3D pcifunc) + return id; + return 0; +} + +static int rvu_rep_tx_vlan_cfg(struct rvu *rvu, u16 pcifunc, + u16 vlan_tci, int *vidx) +{ + struct nix_vtag_config_rsp rsp =3D {}; + struct nix_vtag_config req =3D {}; + u64 etype =3D ETH_P_8021Q; + int err; + + /* Insert vlan tag */ + req.hdr.pcifunc =3D pcifunc; + req.vtag_size =3D VTAGSIZE_T4; + req.cfg_type =3D 0; /* tx vlan cfg */ + req.tx.cfg_vtag0 =3D true; + req.tx.vtag0 =3D FIELD_PREP(NIX_VLAN_ETYPE_MASK, etype) | vlan_tci; + + err =3D rvu_mbox_handler_nix_vtag_cfg(rvu, &req, &rsp); + if (err) { + dev_err(rvu->dev, "Tx vlan config failed\n"); + return err; + } + *vidx =3D rsp.vtag0_idx; + return 0; +} + +static int rvu_rep_rx_vlan_cfg(struct rvu *rvu, u16 pcifunc) +{ + struct nix_vtag_config req =3D {}; + struct nix_vtag_config_rsp rsp; + + /* config strip, capture and size */ + req.hdr.pcifunc =3D pcifunc; + req.vtag_size =3D VTAGSIZE_T4; + req.cfg_type =3D 1; /* rx vlan cfg */ + req.rx.vtag_type =3D NIX_AF_LFX_RX_VTAG_TYPE0; + req.rx.strip_vtag =3D true; + req.rx.capture_vtag =3D false; + + return rvu_mbox_handler_nix_vtag_cfg(rvu, &req, &rsp); +} + +static int rvu_rep_install_rx_rule(struct rvu *rvu, u16 pcifunc, + u16 entry, bool rte) +{ + struct npc_install_flow_req req =3D {}; + struct npc_install_flow_rsp rsp =3D {}; + struct rvu_pfvf *pfvf; + u16 vlan_tci, rep_id; + + pfvf =3D rvu_get_pfvf(rvu, pcifunc); + + /* To steer the traffic from Representee to Representor */ + rep_id =3D rvu_rep_get_vlan_id(rvu, pcifunc); + if (rte) { + vlan_tci =3D rep_id | BIT_ULL(8); + req.vf =3D rvu->rep_pcifunc; + req.op =3D NIX_RX_ACTIONOP_UCAST; + req.index =3D rep_id; + } else { + vlan_tci =3D rep_id; + req.vf =3D pcifunc; + req.op =3D NIX_RX_ACTION_DEFAULT; + } + + rvu_rep_rx_vlan_cfg(rvu, req.vf); + req.entry =3D entry; + req.hdr.pcifunc =3D 0; /* AF is requester */ + req.features =3D BIT_ULL(NPC_OUTER_VID) | BIT_ULL(NPC_VLAN_ETYPE_CTAG); + req.vtag0_valid =3D true; + req.vtag0_type =3D NIX_AF_LFX_RX_VTAG_TYPE0; + req.packet.vlan_etype =3D cpu_to_be16(ETH_P_8021Q); + req.mask.vlan_etype =3D cpu_to_be16(ETH_P_8021Q); + req.packet.vlan_tci =3D cpu_to_be16(vlan_tci); + req.mask.vlan_tci =3D cpu_to_be16(0xffff); + + req.channel =3D RVU_SWITCH_LBK_CHAN; + req.chan_mask =3D 0xffff; + req.intf =3D pfvf->nix_rx_intf; + + return rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp); +} + +static int rvu_rep_install_tx_rule(struct rvu *rvu, u16 pcifunc, u16 entry, + bool rte) +{ + struct npc_install_flow_req req =3D {}; + struct npc_install_flow_rsp rsp =3D {}; + struct rvu_pfvf *pfvf; + int vidx, err; + u16 vlan_tci; + u8 lbkid; + + pfvf =3D rvu_get_pfvf(rvu, pcifunc); + vlan_tci =3D rvu_rep_get_vlan_id(rvu, pcifunc); + if (rte) + vlan_tci |=3D BIT_ULL(8); + + err =3D rvu_rep_tx_vlan_cfg(rvu, pcifunc, vlan_tci, &vidx); + if (err) + return err; + + lbkid =3D pfvf->nix_blkaddr =3D=3D BLKADDR_NIX0 ? 0 : 1; + req.hdr.pcifunc =3D 0; /* AF is requester */ + if (rte) { + req.vf =3D pcifunc; + } else { + req.vf =3D rvu->rep_pcifunc; + req.packet.sq_id =3D vlan_tci; + req.mask.sq_id =3D 0xffff; + } + + req.entry =3D entry; + req.intf =3D pfvf->nix_tx_intf; + req.op =3D NIX_TX_ACTIONOP_UCAST_CHAN; + req.index =3D (lbkid << 8) | RVU_SWITCH_LBK_CHAN; + req.set_cntr =3D 1; + req.vtag0_def =3D vidx; + req.vtag0_op =3D 1; + return rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp); +} + +int rvu_rep_install_mcam_rules(struct rvu *rvu) +{ + struct rvu_switch *rswitch =3D &rvu->rswitch; + u16 start =3D rswitch->start_entry; + struct rvu_hwinfo *hw =3D rvu->hw; + u16 pcifunc, entry =3D 0; + int pf, vf, numvfs; + int err, nixlf, i; + u8 rep; + + for (pf =3D 1; pf < hw->total_pfs; pf++) { + if (!is_pf_cgxmapped(rvu, pf)) + continue; + + pcifunc =3D pf << RVU_PFVF_PF_SHIFT; + rvu_get_nix_blkaddr(rvu, pcifunc); + rep =3D true; + for (i =3D 0; i < 2; i++) { + err =3D rvu_rep_install_rx_rule(rvu, pcifunc, + start + entry, rep); + if (err) + return err; + rswitch->entry2pcifunc[entry++] =3D pcifunc; + + err =3D rvu_rep_install_tx_rule(rvu, pcifunc, + start + entry, rep); + if (err) + return err; + rswitch->entry2pcifunc[entry++] =3D pcifunc; + rep =3D false; + } + + rvu_get_pf_numvfs(rvu, pf, &numvfs, NULL); + for (vf =3D 0; vf < numvfs; vf++) { + pcifunc =3D pf << RVU_PFVF_PF_SHIFT | + ((vf + 1) & RVU_PFVF_FUNC_MASK); + rvu_get_nix_blkaddr(rvu, pcifunc); + + /* Skip installimg rules if nixlf is not attached */ + err =3D nix_get_nixlf(rvu, pcifunc, &nixlf, NULL); + if (err) + continue; + rep =3D true; + for (i =3D 0; i < 2; i++) { + err =3D rvu_rep_install_rx_rule(rvu, pcifunc, + start + entry, + rep); + if (err) + return err; + rswitch->entry2pcifunc[entry++] =3D pcifunc; + + err =3D rvu_rep_install_tx_rule(rvu, pcifunc, + start + entry, + rep); + if (err) + return err; + rswitch->entry2pcifunc[entry++] =3D pcifunc; + rep =3D false; + } + } + } + return 0; +} + +void rvu_rep_update_rules(struct rvu *rvu, u16 pcifunc, bool ena) +{ + struct rvu_switch *rswitch =3D &rvu->rswitch; + struct npc_mcam *mcam =3D &rvu->hw->mcam; + u32 max =3D rswitch->used_entries; + int blkaddr; + u16 entry; + + if (!rswitch->used_entries) + return; + + blkaddr =3D rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); + + if (blkaddr < 0) + return; + + rvu_switch_enable_lbk_link(rvu, pcifunc, ena); + mutex_lock(&mcam->lock); + for (entry =3D 0; entry < max; entry++) { + if (rswitch->entry2pcifunc[entry] =3D=3D pcifunc) + npc_enable_mcam_entry(rvu, mcam, blkaddr, entry, ena); + } + mutex_unlock(&mcam->lock); +} + +int rvu_rep_pf_init(struct rvu *rvu) +{ + u16 pcifunc =3D rvu->rep_pcifunc; + struct rvu_pfvf *pfvf; + + pfvf =3D rvu_get_pfvf(rvu, pcifunc); + set_bit(NIXLF_INITIALIZED, &pfvf->flags); + rvu_switch_enable_lbk_link(rvu, pcifunc, true); + rvu_rep_rx_vlan_cfg(rvu, pcifunc); + return 0; +} + +int rvu_mbox_handler_esw_cfg(struct rvu *rvu, struct esw_cfg_req *req, + struct msg_rsp *rsp) +{ + if (req->hdr.pcifunc !=3D rvu->rep_pcifunc) + return 0; + + rvu->rep_mode =3D req->ena; + return 0; +} + int rvu_mbox_handler_get_rep_cnt(struct rvu *rvu, struct msg_req *req, struct get_rep_cnt_rsp *rsp) { diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_switch.c b/drive= rs/net/ethernet/marvell/octeontx2/af/rvu_switch.c index 854045ed3b06..268efb7c1c15 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_switch.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_switch.c @@ -8,7 +8,7 @@ #include #include "rvu.h" =20 -static void rvu_switch_enable_lbk_link(struct rvu *rvu, u16 pcifunc, bool = enable) +void rvu_switch_enable_lbk_link(struct rvu *rvu, u16 pcifunc, bool enable) { struct rvu_pfvf *pfvf =3D rvu_get_pfvf(rvu, pcifunc); struct nix_hw *nix_hw; @@ -166,6 +166,8 @@ void rvu_switch_enable(struct rvu *rvu) =20 alloc_req.contig =3D true; alloc_req.count =3D rvu->cgx_mapped_pfs + rvu->cgx_mapped_vfs; + if (rvu->rep_mode) + alloc_req.count =3D alloc_req.count * 4; ret =3D rvu_mbox_handler_npc_mcam_alloc_entry(rvu, &alloc_req, &alloc_rsp); if (ret) { @@ -189,7 +191,12 @@ void rvu_switch_enable(struct rvu *rvu) rswitch->used_entries =3D alloc_rsp.count; rswitch->start_entry =3D alloc_rsp.entry; =20 - ret =3D rvu_switch_install_rules(rvu); + if (rvu->rep_mode) { + rvu_rep_pf_init(rvu); + ret =3D rvu_rep_install_mcam_rules(rvu); + } else { + ret =3D rvu_switch_install_rules(rvu); + } if (ret) goto uninstall_rules; =20 @@ -222,6 +229,9 @@ void rvu_switch_disable(struct rvu *rvu) if (!rswitch->used_entries) return; =20 + if (rvu->rep_mode) + goto free_ents; + for (pf =3D 1; pf < hw->total_pfs; pf++) { if (!is_pf_cgxmapped(rvu, pf)) continue; @@ -249,6 +259,7 @@ void rvu_switch_disable(struct rvu *rvu) } } =20 +free_ents: uninstall_req.start =3D rswitch->start_entry; uninstall_req.end =3D rswitch->start_entry + rswitch->used_entries - 1; free_req.all =3D 1; @@ -258,12 +269,15 @@ void rvu_switch_disable(struct rvu *rvu) kfree(rswitch->entry2pcifunc); } =20 -void rvu_switch_update_rules(struct rvu *rvu, u16 pcifunc) +void rvu_switch_update_rules(struct rvu *rvu, u16 pcifunc, bool ena) { struct rvu_switch *rswitch =3D &rvu->rswitch; u32 max =3D rswitch->used_entries; u16 entry; =20 + if (rvu->rep_mode) + return rvu_rep_update_rules(rvu, pcifunc, ena); + if (!rswitch->used_entries) return; =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/rep.c b/drivers/net= /ethernet/marvell/octeontx2/nic/rep.c index d32f685bb25e..50cebd0af524 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/rep.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/rep.c @@ -28,6 +28,22 @@ MODULE_DESCRIPTION(DRV_STRING); MODULE_LICENSE("GPL"); MODULE_DEVICE_TABLE(pci, rvu_rep_id_table); =20 +static int rvu_eswitch_config(struct otx2_nic *priv, u8 ena) +{ + struct esw_cfg_req *req; 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Thu, 07 Nov 2024 08:09:05 -0800 (PST) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 7 Nov 2024 08:09:04 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 7 Nov 2024 08:09:04 -0800 Received: from hyd1soter3.marvell.com (unknown [10.29.37.12]) by maili.marvell.com (Postfix) with ESMTP id 035233F7050; Thu, 7 Nov 2024 08:09:00 -0800 (PST) From: Geetha sowjanya To: , CC: , , , , , , , , Subject: [net-next PATCH v12 05/12] octeontx2-pf: Get VF stats via representor Date: Thu, 7 Nov 2024 21:38:32 +0530 Message-ID: <20241107160839.23707-6-gakula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241107160839.23707-1-gakula@marvell.com> References: <20241107160839.23707-1-gakula@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: JzToMYiOujazRBsp8SCAC4vJBcbPe76I X-Proofpoint-ORIG-GUID: JzToMYiOujazRBsp8SCAC4vJBcbPe76I X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.687,Hydra:6.0.235,FMLib:17.0.607.475 definitions=2020-10-13_15,2020-10-13_02,2020-04-07_01 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Adds support to export VF port statistics via representor netdev. Defines new mbox "NIX_LF_STATS" to fetch VF hw stats. Signed-off-by: Geetha sowjanya Reviewed-by: Simon Horman --- v11-v12: - Moved nix_stat_lf_tx/rx structure to common file. .../net/ethernet/marvell/octeontx2/af/mbox.h | 32 +++++++++ .../marvell/octeontx2/af/rvu_debugfs.c | 27 -------- .../ethernet/marvell/octeontx2/af/rvu_rep.c | 43 ++++++++++++ .../marvell/octeontx2/af/rvu_struct.h | 26 ++++++++ .../marvell/octeontx2/nic/otx2_common.h | 27 -------- .../net/ethernet/marvell/octeontx2/nic/rep.c | 65 +++++++++++++++++++ .../net/ethernet/marvell/octeontx2/nic/rep.h | 14 ++++ 7 files changed, 180 insertions(+), 54 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net= /ethernet/marvell/octeontx2/af/mbox.h index 10d5712b0077..8fd4b585d3b4 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h @@ -321,6 +321,7 @@ M(NIX_MCAST_GRP_DESTROY, 0x802c, nix_mcast_grp_destroy,= nix_mcast_grp_destroy_re M(NIX_MCAST_GRP_UPDATE, 0x802d, nix_mcast_grp_update, \ nix_mcast_grp_update_req, \ nix_mcast_grp_update_rsp) \ +M(NIX_LF_STATS, 0x802e, nix_lf_stats, nix_stats_req, nix_stats_rsp) \ /* MCS mbox IDs (range 0xA000 - 0xBFFF) */ \ M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \ mcs_alloc_rsrc_rsp) \ @@ -1366,6 +1367,37 @@ struct nix_bandprof_get_hwinfo_rsp { u32 policer_timeunit; }; =20 +struct nix_stats_req { + struct mbox_msghdr hdr; + u8 reset; + u16 pcifunc; + u64 rsvd; +}; + +struct nix_stats_rsp { + struct mbox_msghdr hdr; + u16 pcifunc; + struct { + u64 octs; + u64 ucast; + u64 bcast; + u64 mcast; + u64 drop; + u64 drop_octs; + u64 drop_mcast; + u64 drop_bcast; + u64 err; + u64 rsvd[5]; + } rx; + struct { + u64 ucast; + u64 bcast; + u64 mcast; + u64 drop; + u64 octs; + } tx; +}; + /* NPC mbox message structs */ =20 #define NPC_MCAM_ENTRY_INVALID 0xFFFF diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c b/driv= ers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c index 8c700ee4a82b..148144f5b61d 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c @@ -45,33 +45,6 @@ enum { CGX_STAT18, }; =20 -/* NIX TX stats */ -enum nix_stat_lf_tx { - TX_UCAST =3D 0x0, - TX_BCAST =3D 0x1, - TX_MCAST =3D 0x2, - TX_DROP =3D 0x3, - TX_OCTS =3D 0x4, - TX_STATS_ENUM_LAST, -}; - -/* NIX RX stats */ -enum nix_stat_lf_rx { - RX_OCTS =3D 0x0, - RX_UCAST =3D 0x1, - RX_BCAST =3D 0x2, - RX_MCAST =3D 0x3, - RX_DROP =3D 0x4, - RX_DROP_OCTS =3D 0x5, - RX_FCS =3D 0x6, - RX_ERR =3D 0x7, - RX_DRP_BCAST =3D 0x8, - RX_DRP_MCAST =3D 0x9, - RX_DRP_L3BCAST =3D 0xa, - RX_DRP_L3MCAST =3D 0xb, - RX_STATS_ENUM_LAST, -}; - static char *cgx_rx_stats_fields[] =3D { [CGX_STAT0] =3D "Received packets", [CGX_STAT1] =3D "Octets of received packets", diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_rep.c index c1132d68259e..9ac663e05bb6 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c @@ -14,6 +14,49 @@ #include "rvu.h" #include "rvu_reg.h" =20 +#define RVU_LF_RX_STATS(reg) \ + rvu_read64(rvu, blkaddr, NIX_AF_LFX_RX_STATX(nixlf, reg)) + +#define RVU_LF_TX_STATS(reg) \ + rvu_read64(rvu, blkaddr, NIX_AF_LFX_TX_STATX(nixlf, reg)) + +int rvu_mbox_handler_nix_lf_stats(struct rvu *rvu, + struct nix_stats_req *req, + struct nix_stats_rsp *rsp) +{ + u16 pcifunc =3D req->pcifunc; + int nixlf, blkaddr, err; + struct msg_req rst_req; + struct msg_rsp rst_rsp; + + err =3D nix_get_nixlf(rvu, pcifunc, &nixlf, &blkaddr); + if (err) + return 0; + + if (req->reset) { + rst_req.hdr.pcifunc =3D pcifunc; + return rvu_mbox_handler_nix_stats_rst(rvu, &rst_req, &rst_rsp); + } + rsp->rx.octs =3D RVU_LF_RX_STATS(RX_OCTS); + rsp->rx.ucast =3D RVU_LF_RX_STATS(RX_UCAST); + rsp->rx.bcast =3D RVU_LF_RX_STATS(RX_BCAST); + rsp->rx.mcast =3D RVU_LF_RX_STATS(RX_MCAST); + rsp->rx.drop =3D RVU_LF_RX_STATS(RX_DROP); + rsp->rx.err =3D RVU_LF_RX_STATS(RX_ERR); + rsp->rx.drop_octs =3D RVU_LF_RX_STATS(RX_DROP_OCTS); + rsp->rx.drop_mcast =3D RVU_LF_RX_STATS(RX_DRP_MCAST); + rsp->rx.drop_bcast =3D RVU_LF_RX_STATS(RX_DRP_BCAST); + + rsp->tx.octs =3D RVU_LF_TX_STATS(TX_OCTS); + rsp->tx.ucast =3D RVU_LF_TX_STATS(TX_UCAST); + rsp->tx.bcast =3D RVU_LF_TX_STATS(TX_BCAST); + rsp->tx.mcast =3D RVU_LF_TX_STATS(TX_MCAST); + rsp->tx.drop =3D RVU_LF_TX_STATS(TX_DROP); + + rsp->pcifunc =3D req->pcifunc; + return 0; +} + static u16 rvu_rep_get_vlan_id(struct rvu *rvu, u16 pcifunc) { int id; diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h b/drive= rs/net/ethernet/marvell/octeontx2/af/rvu_struct.h index fc8da2090657..77ac94cb2ec4 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h @@ -823,4 +823,30 @@ enum nix_tx_vtag_op { #define VTAG_STRIP BIT_ULL(4) #define VTAG_CAPTURE BIT_ULL(5) =20 +/* NIX TX stats */ +enum nix_stat_lf_tx { + TX_UCAST =3D 0x0, + TX_BCAST =3D 0x1, + TX_MCAST =3D 0x2, + TX_DROP =3D 0x3, + TX_OCTS =3D 0x4, + TX_STATS_ENUM_LAST, +}; + +/* NIX RX stats */ +enum nix_stat_lf_rx { + RX_OCTS =3D 0x0, + RX_UCAST =3D 0x1, + RX_BCAST =3D 0x2, + RX_MCAST =3D 0x3, + RX_DROP =3D 0x4, + RX_DROP_OCTS =3D 0x5, + RX_FCS =3D 0x6, + RX_ERR =3D 0x7, + RX_DRP_BCAST =3D 0x8, + RX_DRP_MCAST =3D 0x9, + RX_DRP_L3BCAST =3D 0xa, + RX_DRP_L3MCAST =3D 0xb, + RX_STATS_ENUM_LAST, +}; #endif /* RVU_STRUCT_H */ diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/dri= vers/net/ethernet/marvell/octeontx2/nic/otx2_common.h index ed2bbe72647a..ae0eb08b276c 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h @@ -121,33 +121,6 @@ enum otx2_errcodes_re { ERRCODE_IL4_CSUM =3D 0x22, }; =20 -/* NIX TX stats */ -enum nix_stat_lf_tx { - TX_UCAST =3D 0x0, - TX_BCAST =3D 0x1, - TX_MCAST =3D 0x2, - TX_DROP =3D 0x3, - TX_OCTS =3D 0x4, - TX_STATS_ENUM_LAST, -}; - -/* NIX RX stats */ -enum nix_stat_lf_rx { - RX_OCTS =3D 0x0, - RX_UCAST =3D 0x1, - RX_BCAST =3D 0x2, - RX_MCAST =3D 0x3, - RX_DROP =3D 0x4, - RX_DROP_OCTS =3D 0x5, - RX_FCS =3D 0x6, - RX_ERR =3D 0x7, - RX_DRP_BCAST =3D 0x8, - RX_DRP_MCAST =3D 0x9, - RX_DRP_L3BCAST =3D 0xa, - RX_DRP_L3MCAST =3D 0xb, - RX_STATS_ENUM_LAST, -}; - struct otx2_dev_stats { u64 rx_bytes; u64 rx_frames; diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/rep.c b/drivers/net= /ethernet/marvell/octeontx2/nic/rep.c index 50cebd0af524..197aa21759b5 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/rep.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/rep.c @@ -28,6 +28,68 @@ MODULE_DESCRIPTION(DRV_STRING); MODULE_LICENSE("GPL"); MODULE_DEVICE_TABLE(pci, rvu_rep_id_table); =20 +static void rvu_rep_get_stats(struct work_struct *work) +{ + struct delayed_work *del_work =3D to_delayed_work(work); + struct nix_stats_req *req; + struct nix_stats_rsp *rsp; + struct rep_stats *stats; + struct otx2_nic *priv; + struct rep_dev *rep; + int err; + + rep =3D container_of(del_work, struct rep_dev, stats_wrk); + priv =3D rep->mdev; + + mutex_lock(&priv->mbox.lock); + req =3D otx2_mbox_alloc_msg_nix_lf_stats(&priv->mbox); + if (!req) { + mutex_unlock(&priv->mbox.lock); + return; + } + req->pcifunc =3D rep->pcifunc; + err =3D otx2_sync_mbox_msg_busy_poll(&priv->mbox); + if (err) + goto exit; + + rsp =3D (struct nix_stats_rsp *) + otx2_mbox_get_rsp(&priv->mbox.mbox, 0, &req->hdr); + + if (IS_ERR(rsp)) { + err =3D PTR_ERR(rsp); + goto exit; + } + + stats =3D &rep->stats; + stats->rx_bytes =3D rsp->rx.octs; + stats->rx_frames =3D rsp->rx.ucast + rsp->rx.bcast + + rsp->rx.mcast; + stats->rx_drops =3D rsp->rx.drop; + stats->rx_mcast_frames =3D rsp->rx.mcast; + stats->tx_bytes =3D rsp->tx.octs; + stats->tx_frames =3D rsp->tx.ucast + rsp->tx.bcast + rsp->tx.mcast; + stats->tx_drops =3D rsp->tx.drop; +exit: + mutex_unlock(&priv->mbox.lock); +} + +static void rvu_rep_get_stats64(struct net_device *dev, + struct rtnl_link_stats64 *stats) +{ + struct rep_dev *rep =3D netdev_priv(dev); + + stats->rx_packets =3D rep->stats.rx_frames; + stats->rx_bytes =3D rep->stats.rx_bytes; + stats->rx_dropped =3D rep->stats.rx_drops; + stats->multicast =3D rep->stats.rx_mcast_frames; + + stats->tx_packets =3D rep->stats.tx_frames; + stats->tx_bytes =3D rep->stats.tx_bytes; + stats->tx_dropped =3D rep->stats.tx_drops; + + schedule_delayed_work(&rep->stats_wrk, msecs_to_jiffies(100)); +} + static int rvu_eswitch_config(struct otx2_nic *priv, u8 ena) { struct esw_cfg_req *req; @@ -87,6 +149,7 @@ static const struct net_device_ops rvu_rep_netdev_ops = =3D { .ndo_open =3D rvu_rep_open, .ndo_stop =3D rvu_rep_stop, .ndo_start_xmit =3D rvu_rep_xmit, + .ndo_get_stats64 =3D rvu_rep_get_stats64, }; =20 static int rvu_rep_napi_init(struct otx2_nic *priv, @@ -290,6 +353,8 @@ int rvu_rep_create(struct otx2_nic *priv, struct netlin= k_ext_ack *extack) free_netdev(ndev); goto exit; } + + INIT_DELAYED_WORK(&rep->stats_wrk, rvu_rep_get_stats); } err =3D rvu_rep_napi_init(priv, extack); if (err) diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/rep.h b/drivers/net= /ethernet/marvell/octeontx2/nic/rep.h index c04874c4d4c6..5d39bf636655 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/rep.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/rep.h @@ -17,9 +17,23 @@ #define PCI_DEVID_RVU_REP 0xA0E0 =20 #define RVU_MAX_REP OTX2_MAX_CQ_CNT + +struct rep_stats { + u64 rx_bytes; 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Thu, 7 Nov 2024 08:09:08 -0800 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 7 Nov 2024 08:09:08 -0800 Received: from hyd1soter3.marvell.com (unknown [10.29.37.12]) by maili.marvell.com (Postfix) with ESMTP id E18D53F7050; Thu, 7 Nov 2024 08:09:04 -0800 (PST) From: Geetha sowjanya To: , CC: , , , , , , , , Subject: [net-next PATCH v12 06/12] octeontx2-pf: Add support to sync link state between representor and VFs Date: Thu, 7 Nov 2024 21:38:33 +0530 Message-ID: <20241107160839.23707-7-gakula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241107160839.23707-1-gakula@marvell.com> References: <20241107160839.23707-1-gakula@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: HXSImbVSPfuu60gdpxQ0weyMBTwkOGUg X-Proofpoint-ORIG-GUID: HXSImbVSPfuu60gdpxQ0weyMBTwkOGUg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Implements the below requirement mentioned in the representors documentation. " The representee's link state is controlled through the representor. Setting the representor administratively UP or DOWN should cause carrier ON or OFF at the representee. " This patch enables - Reflecting the link state of representor based on the VF state and link state of VF based on representor. - On VF interface up/down a notification is sent via mbox to representor to update the link state. eg: ip link set eth0 up/down will disable carrier on/off of the corresponding representor(r0p1) interface. - On representor interface up/down will cause the link state update of VF. eg: ip link set r0p1 up/down will disable carrier on/off of the corresponding representee(eth0) interface. Signed-off-by: Harman Kalra Signed-off-by: Geetha sowjanya Reviewed-by: Simon Horman --- .../net/ethernet/marvell/octeontx2/af/mbox.h | 25 ++++ .../net/ethernet/marvell/octeontx2/af/rvu.h | 11 ++ .../ethernet/marvell/octeontx2/af/rvu_nix.c | 15 +- .../ethernet/marvell/octeontx2/af/rvu_rep.c | 128 ++++++++++++++++++ .../marvell/octeontx2/nic/otx2_common.h | 2 + .../ethernet/marvell/octeontx2/nic/otx2_pf.c | 30 ++++ .../net/ethernet/marvell/octeontx2/nic/rep.c | 76 +++++++++++ .../net/ethernet/marvell/octeontx2/nic/rep.h | 3 + 8 files changed, 287 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net= /ethernet/marvell/octeontx2/af/mbox.h index 8fd4b585d3b4..b583c964d30c 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h @@ -146,6 +146,7 @@ M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rs= p) \ M(PTP_GET_CAP, 0x00c, ptp_get_cap, msg_req, ptp_get_cap_rsp) \ M(GET_REP_CNT, 0x00d, get_rep_cnt, msg_req, get_rep_cnt_rsp) \ M(ESW_CFG, 0x00e, esw_cfg, esw_cfg_req, msg_rsp) \ +M(REP_EVENT_NOTIFY, 0x00f, rep_event_notify, rep_event, msg_rsp) \ /* CGX mbox IDs (range 0x200 - 0x3FF) */ \ M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ @@ -383,12 +384,16 @@ M(CPT_INST_LMTST, 0xD00, cpt_inst_lmtst, cpt_inst_lmt= st_req, msg_rsp) #define MBOX_UP_MCS_MESSAGES \ M(MCS_INTR_NOTIFY, 0xE00, mcs_intr_notify, mcs_intr_info, msg_rsp) =20 +#define MBOX_UP_REP_MESSAGES \ +M(REP_EVENT_UP_NOTIFY, 0xEF0, rep_event_up_notify, rep_event, msg_rsp) \ + enum { #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name =3D _id, MBOX_MESSAGES MBOX_UP_CGX_MESSAGES MBOX_UP_CPT_MESSAGES MBOX_UP_MCS_MESSAGES +MBOX_UP_REP_MESSAGES #undef M }; =20 @@ -1572,6 +1577,26 @@ struct esw_cfg_req { u64 rsvd; }; =20 +struct rep_evt_data { + u8 port_state; + u8 vf_state; + u16 rx_mode; + u16 rx_flags; + u16 mtu; + u64 rsvd[5]; +}; + +struct rep_event { + struct mbox_msghdr hdr; + u16 pcifunc; +#define RVU_EVENT_PORT_STATE BIT_ULL(0) +#define RVU_EVENT_PFVF_STATE BIT_ULL(1) +#define RVU_EVENT_MTU_CHANGE BIT_ULL(2) +#define RVU_EVENT_RX_MODE_CHANGE BIT_ULL(3) + u16 event; + struct rep_evt_data evt_data; +}; + struct flow_msg { unsigned char dmac[6]; unsigned char smac[6]; diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/= ethernet/marvell/octeontx2/af/rvu.h index ceca9b897336..86bb87ae20ec 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h @@ -513,6 +513,11 @@ struct rvu_switch { u16 start_entry; }; =20 +struct rep_evtq_ent { + struct list_head node; + struct rep_event event; +}; + struct rvu { void __iomem *afreg_base; void __iomem *pfreg_base; @@ -598,6 +603,11 @@ struct rvu { int rep_cnt; u16 *rep2pfvf_map; u8 rep_mode; + struct work_struct rep_evt_work; + struct workqueue_struct *rep_evt_wq; + struct list_head rep_evtq_head; + /* Representor event lock */ + spinlock_t rep_evtq_lock; }; =20 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64= val) @@ -1075,4 +1085,5 @@ void rvu_mcs_exit(struct rvu *rvu); int rvu_rep_pf_init(struct rvu *rvu); int rvu_rep_install_mcam_rules(struct rvu *rvu); void rvu_rep_update_rules(struct rvu *rvu, u16 pcifunc, bool ena); +int rvu_rep_notify_pfvf_state(struct rvu *rvu, u16 pcifunc, bool enable); #endif /* RVU_H */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_nix.c index 673e4991fe23..26cf42adf109 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c @@ -363,7 +363,6 @@ static int nix_interface_init(struct rvu *rvu, u16 pcif= unc, int type, int nixlf, =20 cgx_set_pkind(rvu_cgx_pdata(cgx_id, rvu), lmac_id, pkind); rvu_npc_set_pkind(rvu, pkind, pfvf); - break; case NIX_INTF_TYPE_LBK: vf =3D (pcifunc & RVU_PFVF_FUNC_MASK) - 1; @@ -5180,7 +5179,7 @@ int rvu_mbox_handler_nix_lf_start_rx(struct rvu *rvu,= struct msg_req *req, { u16 pcifunc =3D req->hdr.pcifunc; struct rvu_pfvf *pfvf; - int nixlf, err; + int nixlf, err, pf; =20 err =3D nix_get_nixlf(rvu, pcifunc, &nixlf, NULL); if (err) @@ -5198,6 +5197,10 @@ int rvu_mbox_handler_nix_lf_start_rx(struct rvu *rvu= , struct msg_req *req, =20 rvu_switch_update_rules(rvu, pcifunc, true); =20 + pf =3D rvu_get_pf(pcifunc); + if (is_pf_cgxmapped(rvu, pf) && rvu->rep_mode) + rvu_rep_notify_pfvf_state(rvu, pcifunc, true); + return rvu_cgx_start_stop_io(rvu, pcifunc, true); } =20 @@ -5206,7 +5209,7 @@ int rvu_mbox_handler_nix_lf_stop_rx(struct rvu *rvu, = struct msg_req *req, { u16 pcifunc =3D req->hdr.pcifunc; struct rvu_pfvf *pfvf; - int nixlf, err; + int nixlf, err, pf; =20 err =3D nix_get_nixlf(rvu, pcifunc, &nixlf, NULL); if (err) @@ -5227,6 +5230,9 @@ int rvu_mbox_handler_nix_lf_stop_rx(struct rvu *rvu, = struct msg_req *req, rvu_switch_update_rules(rvu, pcifunc, false); rvu_cgx_tx_enable(rvu, pcifunc, true); =20 + pf =3D rvu_get_pf(pcifunc); + if (is_pf_cgxmapped(rvu, pf) && rvu->rep_mode) + rvu_rep_notify_pfvf_state(rvu, pcifunc, false); return 0; } =20 @@ -5254,6 +5260,9 @@ void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc= , int blkaddr, int nixlf) =20 clear_bit(NIXLF_INITIALIZED, &pfvf->flags); =20 + if (is_pf_cgxmapped(rvu, pf) && rvu->rep_mode) + rvu_rep_notify_pfvf_state(rvu, pcifunc, false); + rvu_cgx_start_stop_io(rvu, pcifunc, false); =20 if (pfvf->sq_ctx) { diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_rep.c index 9ac663e05bb6..80947fa28138 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c @@ -14,6 +14,124 @@ #include "rvu.h" #include "rvu_reg.h" =20 +#define M(_name, _id, _fn_name, _req_type, _rsp_type) \ +static struct _req_type __maybe_unused \ +*otx2_mbox_alloc_msg_ ## _fn_name(struct rvu *rvu, int devid) \ +{ \ + struct _req_type *req; \ + \ + req =3D (struct _req_type *)otx2_mbox_alloc_msg_rsp( \ + &rvu->afpf_wq_info.mbox_up, devid, sizeof(struct _req_type), \ + sizeof(struct _rsp_type)); \ + if (!req) \ + return NULL; \ + req->hdr.sig =3D OTX2_MBOX_REQ_SIG; \ + req->hdr.id =3D _id; \ + return req; \ +} + +MBOX_UP_REP_MESSAGES +#undef M + +static int rvu_rep_up_notify(struct rvu *rvu, struct rep_event *event) +{ + struct rep_event *msg; + int pf; + + pf =3D rvu_get_pf(event->pcifunc); + + mutex_lock(&rvu->mbox_lock); + msg =3D otx2_mbox_alloc_msg_rep_event_up_notify(rvu, pf); + if (!msg) { + mutex_unlock(&rvu->mbox_lock); + return -ENOMEM; + } + + msg->hdr.pcifunc =3D event->pcifunc; + msg->event =3D event->event; + + memcpy(&msg->evt_data, &event->evt_data, sizeof(struct rep_evt_data)); + + otx2_mbox_wait_for_zero(&rvu->afpf_wq_info.mbox_up, pf); + + otx2_mbox_msg_send_up(&rvu->afpf_wq_info.mbox_up, pf); + + mutex_unlock(&rvu->mbox_lock); + return 0; +} + +static void rvu_rep_wq_handler(struct work_struct *work) +{ + struct rvu *rvu =3D container_of(work, struct rvu, rep_evt_work); + struct rep_evtq_ent *qentry; + struct rep_event *event; + unsigned long flags; + + do { + spin_lock_irqsave(&rvu->rep_evtq_lock, flags); + qentry =3D list_first_entry_or_null(&rvu->rep_evtq_head, + struct rep_evtq_ent, + node); + if (qentry) + list_del(&qentry->node); + + spin_unlock_irqrestore(&rvu->rep_evtq_lock, flags); + if (!qentry) + break; /* nothing more to process */ + + event =3D &qentry->event; + + rvu_rep_up_notify(rvu, event); + kfree(qentry); + } while (1); +} + +int rvu_mbox_handler_rep_event_notify(struct rvu *rvu, struct rep_event *r= eq, + struct msg_rsp *rsp) +{ + struct rep_evtq_ent *qentry; + + qentry =3D kmalloc(sizeof(*qentry), GFP_ATOMIC); + if (!qentry) + return -ENOMEM; + + qentry->event =3D *req; + spin_lock(&rvu->rep_evtq_lock); + list_add_tail(&qentry->node, &rvu->rep_evtq_head); + spin_unlock(&rvu->rep_evtq_lock); + queue_work(rvu->rep_evt_wq, &rvu->rep_evt_work); + return 0; +} + +int rvu_rep_notify_pfvf_state(struct rvu *rvu, u16 pcifunc, bool enable) +{ + struct rep_event *req; + int pf; + + if (!is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))) + return 0; + + pf =3D rvu_get_pf(rvu->rep_pcifunc); + + mutex_lock(&rvu->mbox_lock); + req =3D otx2_mbox_alloc_msg_rep_event_up_notify(rvu, pf); + if (!req) { + mutex_unlock(&rvu->mbox_lock); + return -ENOMEM; + } + + req->hdr.pcifunc =3D rvu->rep_pcifunc; + req->event |=3D RVU_EVENT_PFVF_STATE; + req->pcifunc =3D pcifunc; + req->evt_data.vf_state =3D enable; + + otx2_mbox_wait_for_zero(&rvu->afpf_wq_info.mbox_up, pf); + otx2_mbox_msg_send_up(&rvu->afpf_wq_info.mbox_up, pf); + + mutex_unlock(&rvu->mbox_lock); + return 0; +} + #define RVU_LF_RX_STATS(reg) \ rvu_read64(rvu, blkaddr, NIX_AF_LFX_RX_STATX(nixlf, reg)) =20 @@ -248,6 +366,16 @@ int rvu_rep_install_mcam_rules(struct rvu *rvu) } } } + + /* Initialize the wq for handling REP events */ + spin_lock_init(&rvu->rep_evtq_lock); + INIT_LIST_HEAD(&rvu->rep_evtq_head); + INIT_WORK(&rvu->rep_evt_work, rvu_rep_wq_handler); + rvu->rep_evt_wq =3D alloc_workqueue("rep_evt_wq", 0, 0); + if (!rvu->rep_evt_wq) { + dev_err(rvu->dev, "REP workqueue allocation failed\n"); + return -ENOMEM; + } return 0; } =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/dri= vers/net/ethernet/marvell/octeontx2/nic/otx2_common.h index ae0eb08b276c..962b10f1583a 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h @@ -441,6 +441,7 @@ struct otx2_nic { #define OTX2_FLAG_ADPTV_INT_COAL_ENABLED BIT_ULL(16) #define OTX2_FLAG_TC_MARK_ENABLED BIT_ULL(17) #define OTX2_FLAG_REP_MODE_ENABLED BIT_ULL(18) +#define OTX2_FLAG_PORT_UP BIT_ULL(19) u64 flags; u64 *cq_op_addr; =20 @@ -1125,4 +1126,5 @@ u16 otx2_select_queue(struct net_device *netdev, stru= ct sk_buff *skb, int otx2_get_txq_by_classid(struct otx2_nic *pfvf, u16 classid); void otx2_qos_config_txschq(struct otx2_nic *pfvf); void otx2_clean_qos_queues(struct otx2_nic *pfvf); +int rvu_event_up_notify(struct otx2_nic *pf, struct rep_event *info); #endif /* OTX2_COMMON_H */ diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers= /net/ethernet/marvell/octeontx2/nic/otx2_pf.c index 41480e23ae4d..ea5183fc8414 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c @@ -519,6 +519,7 @@ static void otx2_pfvf_mbox_up_handler(struct work_struc= t *work) =20 switch (msg->id) { case MBOX_MSG_CGX_LINK_EVENT: + case MBOX_MSG_REP_EVENT_UP_NOTIFY: break; default: if (msg->rc) @@ -832,6 +833,9 @@ static void otx2_handle_link_event(struct otx2_nic *pf) struct cgx_link_user_info *linfo =3D &pf->linfo; struct net_device *netdev =3D pf->netdev; =20 + if (pf->flags & OTX2_FLAG_PORT_UP) + return; + pr_info("%s NIC Link is %s %d Mbps %s duplex\n", netdev->name, linfo->link_up ? "UP" : "DOWN", linfo->speed, linfo->full_duplex ? "Full" : "Half"); @@ -844,6 +848,30 @@ static void otx2_handle_link_event(struct otx2_nic *pf) } } =20 +static int otx2_mbox_up_handler_rep_event_up_notify(struct otx2_nic *pf, + struct rep_event *info, + struct msg_rsp *rsp) +{ + struct net_device *netdev =3D pf->netdev; + + if (info->event =3D=3D RVU_EVENT_PORT_STATE) { + if (info->evt_data.port_state) { + pf->flags |=3D OTX2_FLAG_PORT_UP; + netif_carrier_on(netdev); + netif_tx_start_all_queues(netdev); + } else { + pf->flags &=3D ~OTX2_FLAG_PORT_UP; + netif_tx_stop_all_queues(netdev); + netif_carrier_off(netdev); + } + return 0; + } +#ifdef CONFIG_RVU_ESWITCH + rvu_event_up_notify(pf, info); +#endif + return 0; +} + int otx2_mbox_up_handler_mcs_intr_notify(struct otx2_nic *pf, struct mcs_intr_info *event, struct msg_rsp *rsp) @@ -913,6 +941,7 @@ static int otx2_process_mbox_msg_up(struct otx2_nic *pf, } MBOX_UP_CGX_MESSAGES MBOX_UP_MCS_MESSAGES +MBOX_UP_REP_MESSAGES #undef M break; default: @@ -1974,6 +2003,7 @@ int otx2_open(struct net_device *netdev) } =20 pf->flags &=3D ~OTX2_FLAG_INTF_DOWN; + pf->flags &=3D ~OTX2_FLAG_PORT_UP; /* 'intf_down' may be checked on any cpu */ smp_wmb(); =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/rep.c b/drivers/net= /ethernet/marvell/octeontx2/nic/rep.c index 197aa21759b5..eec3e0dc7fdf 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/rep.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/rep.c @@ -28,6 +28,57 @@ MODULE_DESCRIPTION(DRV_STRING); MODULE_LICENSE("GPL"); MODULE_DEVICE_TABLE(pci, rvu_rep_id_table); =20 +static int rvu_rep_get_repid(struct otx2_nic *priv, u16 pcifunc) +{ + int rep_id; + + for (rep_id =3D 0; rep_id < priv->rep_cnt; rep_id++) + if (priv->rep_pf_map[rep_id] =3D=3D pcifunc) + return rep_id; + return -EINVAL; +} + +static int rvu_rep_notify_pfvf(struct otx2_nic *priv, u16 event, + struct rep_event *data) +{ + struct rep_event *req; + + mutex_lock(&priv->mbox.lock); + req =3D otx2_mbox_alloc_msg_rep_event_notify(&priv->mbox); + if (!req) { + mutex_unlock(&priv->mbox.lock); + return -ENOMEM; + } + req->event =3D event; + req->pcifunc =3D data->pcifunc; + + memcpy(&req->evt_data, &data->evt_data, sizeof(struct rep_evt_data)); + otx2_sync_mbox_msg(&priv->mbox); + mutex_unlock(&priv->mbox.lock); + return 0; +} + +static void rvu_rep_state_evt_handler(struct otx2_nic *priv, + struct rep_event *info) +{ + struct rep_dev *rep; + int rep_id; + + rep_id =3D rvu_rep_get_repid(priv, info->pcifunc); + rep =3D priv->reps[rep_id]; + if (info->evt_data.vf_state) + rep->flags |=3D RVU_REP_VF_INITIALIZED; + else + rep->flags &=3D ~RVU_REP_VF_INITIALIZED; +} + +int rvu_event_up_notify(struct otx2_nic *pf, struct rep_event *info) +{ + if (info->event & RVU_EVENT_PFVF_STATE) + rvu_rep_state_evt_handler(pf, info); + return 0; +} + static void rvu_rep_get_stats(struct work_struct *work) { struct delayed_work *del_work =3D to_delayed_work(work); @@ -78,6 +129,9 @@ static void rvu_rep_get_stats64(struct net_device *dev, { struct rep_dev *rep =3D netdev_priv(dev); =20 + if (!(rep->flags & RVU_REP_VF_INITIALIZED)) + return; + stats->rx_packets =3D rep->stats.rx_frames; stats->rx_bytes =3D rep->stats.rx_bytes; stats->rx_dropped =3D rep->stats.rx_drops; @@ -132,16 +186,38 @@ static netdev_tx_t rvu_rep_xmit(struct sk_buff *skb, = struct net_device *dev) =20 static int rvu_rep_open(struct net_device *dev) { + struct rep_dev *rep =3D netdev_priv(dev); + struct otx2_nic *priv =3D rep->mdev; + struct rep_event evt =3D {0}; + + if (!(rep->flags & RVU_REP_VF_INITIALIZED)) + return 0; + netif_carrier_on(dev); netif_tx_start_all_queues(dev); + + evt.event =3D RVU_EVENT_PORT_STATE; + evt.evt_data.port_state =3D 1; + evt.pcifunc =3D rep->pcifunc; + rvu_rep_notify_pfvf(priv, RVU_EVENT_PORT_STATE, &evt); return 0; } =20 static int rvu_rep_stop(struct net_device *dev) { + struct rep_dev *rep =3D netdev_priv(dev); + struct otx2_nic *priv =3D rep->mdev; + struct rep_event evt =3D {0}; + + if (!(rep->flags & RVU_REP_VF_INITIALIZED)) + return 0; + netif_carrier_off(dev); netif_tx_disable(dev); =20 + evt.event =3D RVU_EVENT_PORT_STATE; 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charset="utf-8" Adds support to manage the mtu configuration for VF through representor. On update of representor mtu a mbox notification is send to VF to update its mtu. This feature is implemented based on the "Network Function Representors" kernel documentation. " Setting an MTU on the representor should cause that same MTU to be reported to the representee. " Signed-off-by: Sai Krishna Signed-off-by: Geetha sowjanya Reviewed-by: Simon Horman --- .../ethernet/marvell/octeontx2/nic/otx2_pf.c | 5 +++++ .../net/ethernet/marvell/octeontx2/nic/rep.c | 17 +++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers= /net/ethernet/marvell/octeontx2/nic/otx2_pf.c index ea5183fc8414..0d62f16af68b 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c @@ -854,6 +854,11 @@ static int otx2_mbox_up_handler_rep_event_up_notify(st= ruct otx2_nic *pf, { struct net_device *netdev =3D pf->netdev; =20 + if (info->event =3D=3D RVU_EVENT_MTU_CHANGE) { + netdev->mtu =3D info->evt_data.mtu; + return 0; + } + if (info->event =3D=3D RVU_EVENT_PORT_STATE) { if (info->evt_data.port_state) { pf->flags |=3D OTX2_FLAG_PORT_UP; diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/rep.c b/drivers/net= /ethernet/marvell/octeontx2/nic/rep.c index eec3e0dc7fdf..d4e78015ef71 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/rep.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/rep.c @@ -79,6 +79,22 @@ int rvu_event_up_notify(struct otx2_nic *pf, struct rep_= event *info) return 0; } =20 +static int rvu_rep_change_mtu(struct net_device *dev, int new_mtu) +{ + struct rep_dev *rep =3D netdev_priv(dev); + struct otx2_nic *priv =3D rep->mdev; + struct rep_event evt =3D {0}; + + netdev_info(dev, "Changing MTU from %d to %d\n", + dev->mtu, new_mtu); + dev->mtu =3D new_mtu; + + evt.evt_data.mtu =3D new_mtu; + evt.pcifunc =3D rep->pcifunc; + rvu_rep_notify_pfvf(priv, RVU_EVENT_MTU_CHANGE, &evt); + return 0; +} + static void rvu_rep_get_stats(struct work_struct *work) { struct delayed_work *del_work =3D to_delayed_work(work); @@ -226,6 +242,7 @@ static const struct net_device_ops rvu_rep_netdev_ops = =3D { .ndo_stop =3D rvu_rep_stop, .ndo_start_xmit =3D rvu_rep_xmit, .ndo_get_stats64 =3D rvu_rep_get_stats64, + .ndo_change_mtu =3D rvu_rep_change_mtu, }; =20 static int rvu_rep_napi_init(struct otx2_nic *priv, --=20 2.25.1 From nobody Sun Nov 24 03:06:22 2024 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE714217668; 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Thu, 07 Nov 2024 08:09:17 -0800 (PST) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 7 Nov 2024 08:09:16 -0800 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 7 Nov 2024 08:09:16 -0800 Received: from hyd1soter3.marvell.com (unknown [10.29.37.12]) by maili.marvell.com (Postfix) with ESMTP id BC9FC3F7050; Thu, 7 Nov 2024 08:09:12 -0800 (PST) From: Geetha sowjanya To: , CC: , , , , , , , , Subject: [net-next PATCH v12 08/12] octeontx2-pf: Add representors for sdp MAC Date: Thu, 7 Nov 2024 21:38:35 +0530 Message-ID: <20241107160839.23707-9-gakula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241107160839.23707-1-gakula@marvell.com> References: <20241107160839.23707-1-gakula@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: ghPfrc2_UIc3tsY4exOPaRRT-n2B7gHR X-Proofpoint-GUID: ghPfrc2_UIc3tsY4exOPaRRT-n2B7gHR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.687,Hydra:6.0.235,FMLib:17.0.607.475 definitions=2020-10-13_15,2020-10-13_02,2020-04-07_01 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Hardware supports different types of MACs eg RPM, SDP, LBK. LBK is for internal Tx->Rx HW loopback path. RPM and SDP MACs support ingress/egress pkt IO on interfaces with different set of capabilities like interface modes. At the time of netdev driver registration PF will seek MAC related information from Admin function driver 'drivers/net/ethernet/marvell/octeontx2/af' and sets up ingress/egress queues etc such that pkt IO on the channels of these different MACs is possible. This patch add representors for SDP MAC. Signed-off-by: Geetha sowjanya Reviewed-by: Simon Horman --- .../ethernet/marvell/octeontx2/af/common.h | 1 + .../ethernet/marvell/octeontx2/af/rvu_nix.c | 5 +- .../ethernet/marvell/octeontx2/nic/cn10k.c | 4 +- .../ethernet/marvell/octeontx2/nic/cn10k.h | 2 +- .../marvell/octeontx2/nic/otx2_common.c | 50 +++++++++++++++---- .../marvell/octeontx2/nic/otx2_common.h | 27 +++++++--- .../ethernet/marvell/octeontx2/nic/otx2_pf.c | 13 +++-- .../ethernet/marvell/octeontx2/nic/otx2_vf.c | 12 ++++- 8 files changed, 88 insertions(+), 26 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/common.h b/drivers/n= et/ethernet/marvell/octeontx2/af/common.h index 2436c1ff9ba4..5d84386ed22d 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/common.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/common.h @@ -156,6 +156,7 @@ enum nix_scheduler { #define NIC_HW_MIN_FRS 40 #define NIC_HW_MAX_FRS 9212 #define SDP_HW_MAX_FRS 65535 +#define SDP_HW_MIN_FRS 16 #define CN10K_LMAC_LINK_MAX_FRS 16380 /* 16k - FCS */ #define CN10K_LBK_LINK_MAX_FRS 65535 /* 64k */ =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_nix.c index 26cf42adf109..5d5a01dbbca1 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c @@ -586,6 +586,9 @@ int rvu_mbox_handler_nix_bp_disable(struct rvu *rvu, if (!is_pf_cgxmapped(rvu, pf) && type !=3D NIX_INTF_TYPE_LBK) return 0; =20 + if (is_sdp_pfvf(pcifunc)) + type =3D NIX_INTF_TYPE_SDP; + pfvf =3D rvu_get_pfvf(rvu, pcifunc); err =3D nix_get_struct_ptrs(rvu, pcifunc, &nix_hw, &blkaddr); if (err) @@ -4687,7 +4690,7 @@ static void nix_link_config(struct rvu *rvu, int blka= ddr, if (hw->sdp_links) { link =3D hw->cgx_links + hw->lbk_links; rvu_write64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link), - SDP_HW_MAX_FRS << 16 | NIC_HW_MIN_FRS); + SDP_HW_MAX_FRS << 16 | SDP_HW_MIN_FRS); } =20 /* Get MCS external bypass status for CN10K-B */ diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/cn10k.c b/drivers/n= et/ethernet/marvell/octeontx2/nic/cn10k.c index 7417087b6db5..a15cc86635d6 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/cn10k.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/cn10k.c @@ -72,7 +72,7 @@ int cn10k_lmtst_init(struct otx2_nic *pfvf) } EXPORT_SYMBOL(cn10k_lmtst_init); =20 -int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura) +int cn10k_sq_aq_init(void *dev, u16 qidx, u8 chan_offset, u16 sqb_aura) { struct nix_cn10k_aq_enq_req *aq; struct otx2_nic *pfvf =3D dev; @@ -88,7 +88,7 @@ int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura) aq->sq.ena =3D 1; aq->sq.smq =3D otx2_get_smq_idx(pfvf, qidx); aq->sq.smq_rr_weight =3D mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen); - aq->sq.default_chan =3D pfvf->hw.tx_chan_base; + aq->sq.default_chan =3D pfvf->hw.tx_chan_base + chan_offset; aq->sq.sqe_stype =3D NIX_STYPE_STF; /* Cache SQB */ aq->sq.sqb_aura =3D sqb_aura; aq->sq.sq_int_ena =3D NIX_SQINT_BITS; diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/cn10k.h b/drivers/n= et/ethernet/marvell/octeontx2/nic/cn10k.h index c1861f7de254..e3f0bce9908f 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/cn10k.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/cn10k.h @@ -26,7 +26,7 @@ static inline int mtu_to_dwrr_weight(struct otx2_nic *pfv= f, int mtu) =20 int cn10k_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq); void cn10k_sqe_flush(void *dev, struct otx2_snd_queue *sq, int size, int q= idx); -int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura); +int cn10k_sq_aq_init(void *dev, u16 qidx, u8 chan_offset, u16 sqb_aura); int cn10k_lmtst_init(struct otx2_nic *pfvf); int cn10k_free_all_ipolicers(struct otx2_nic *pfvf); int cn10k_alloc_matchall_ipolicer(struct otx2_nic *pfvf); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c b/dri= vers/net/ethernet/marvell/octeontx2/nic/otx2_common.c index 8b6e60dde684..46a448030e64 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c @@ -253,7 +253,7 @@ int otx2_config_pause_frm(struct otx2_nic *pfvf) struct cgx_pause_frm_cfg *req; int err; =20 - if (is_otx2_lbkvf(pfvf->pdev)) + if (is_otx2_lbkvf(pfvf->pdev) || is_otx2_sdp_rep(pfvf->pdev)) return 0; =20 mutex_lock(&pfvf->mbox.lock); @@ -647,12 +647,22 @@ int otx2_txschq_config(struct otx2_nic *pfvf, int lvl= , int prio, bool txschq_for req->reg[2] =3D NIX_AF_MDQX_SCHEDULE(schq); req->regval[2] =3D dwrr_val; } else if (lvl =3D=3D NIX_TXSCH_LVL_TL4) { + int sdp_chan =3D hw->tx_chan_base + prio; + + if (is_otx2_sdp_rep(pfvf->pdev)) + prio =3D 0; parent =3D schq_list[NIX_TXSCH_LVL_TL3][prio]; req->reg[0] =3D NIX_AF_TL4X_PARENT(schq); req->regval[0] =3D (u64)parent << 16; req->num_regs++; req->reg[1] =3D NIX_AF_TL4X_SCHEDULE(schq); req->regval[1] =3D dwrr_val; + if (is_otx2_sdp_rep(pfvf->pdev)) { + req->num_regs++; + req->reg[2] =3D NIX_AF_TL4X_SDP_LINK_CFG(schq); + req->regval[2] =3D BIT_ULL(12) | BIT_ULL(13) | + (sdp_chan & 0xff); + } } else if (lvl =3D=3D NIX_TXSCH_LVL_TL3) { parent =3D schq_list[NIX_TXSCH_LVL_TL2][prio]; req->reg[0] =3D NIX_AF_TL3X_PARENT(schq); @@ -660,7 +670,8 @@ int otx2_txschq_config(struct otx2_nic *pfvf, int lvl, = int prio, bool txschq_for req->num_regs++; req->reg[1] =3D NIX_AF_TL3X_SCHEDULE(schq); req->regval[1] =3D dwrr_val; - if (lvl =3D=3D hw->txschq_link_cfg_lvl) { + if (lvl =3D=3D hw->txschq_link_cfg_lvl && + !is_otx2_sdp_rep(pfvf->pdev)) { req->num_regs++; req->reg[2] =3D NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link); /* Enable this queue and backpressure @@ -677,7 +688,8 @@ int otx2_txschq_config(struct otx2_nic *pfvf, int lvl, = int prio, bool txschq_for req->reg[1] =3D NIX_AF_TL2X_SCHEDULE(schq); req->regval[1] =3D (u64)hw->txschq_aggr_lvl_rr_prio << 24 | dwrr_val; =20 - if (lvl =3D=3D hw->txschq_link_cfg_lvl) { + if (lvl =3D=3D hw->txschq_link_cfg_lvl && + !is_otx2_sdp_rep(pfvf->pdev)) { req->num_regs++; req->reg[2] =3D NIX_AF_TL3_TL2X_LINKX_CFG(schq, hw->tx_link); /* Enable this queue and backpressure @@ -736,6 +748,7 @@ EXPORT_SYMBOL(otx2_smq_flush); =20 int otx2_txsch_alloc(struct otx2_nic *pfvf) { + int chan_cnt =3D pfvf->hw.tx_chan_cnt; struct nix_txsch_alloc_req *req; struct nix_txsch_alloc_rsp *rsp; int lvl, schq, rc; @@ -748,6 +761,12 @@ int otx2_txsch_alloc(struct otx2_nic *pfvf) /* Request one schq per level */ for (lvl =3D 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) req->schq[lvl] =3D 1; + + if (is_otx2_sdp_rep(pfvf->pdev) && chan_cnt > 1) { + req->schq[NIX_TXSCH_LVL_SMQ] =3D chan_cnt; + req->schq[NIX_TXSCH_LVL_TL4] =3D chan_cnt; + } + rc =3D otx2_sync_mbox_msg(&pfvf->mbox); if (rc) return rc; @@ -758,10 +777,12 @@ int otx2_txsch_alloc(struct otx2_nic *pfvf) return PTR_ERR(rsp); =20 /* Setup transmit scheduler list */ - for (lvl =3D 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) + for (lvl =3D 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { + pfvf->hw.txschq_cnt[lvl] =3D rsp->schq[lvl]; for (schq =3D 0; schq < rsp->schq[lvl]; schq++) pfvf->hw.txschq_list[lvl][schq] =3D rsp->schq_list[lvl][schq]; + } =20 pfvf->hw.txschq_link_cfg_lvl =3D rsp->link_cfg_lvl; pfvf->hw.txschq_aggr_lvl_rr_prio =3D rsp->aggr_lvl_rr_prio; @@ -799,12 +820,15 @@ EXPORT_SYMBOL(otx2_txschq_free_one); =20 void otx2_txschq_stop(struct otx2_nic *pfvf) { - int lvl, schq; + int lvl, schq, idx; =20 /* free non QOS TLx nodes */ - for (lvl =3D 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) - otx2_txschq_free_one(pfvf, lvl, - pfvf->hw.txschq_list[lvl][0]); + for (lvl =3D 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { + for (idx =3D 0; idx < pfvf->hw.txschq_cnt[lvl]; idx++) { + otx2_txschq_free_one(pfvf, lvl, + pfvf->hw.txschq_list[lvl][idx]); + } + } =20 /* Clear the txschq list */ for (lvl =3D 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { @@ -884,7 +908,7 @@ static int otx2_rq_init(struct otx2_nic *pfvf, u16 qidx= , u16 lpb_aura) return otx2_sync_mbox_msg(&pfvf->mbox); } =20 -int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura) +int otx2_sq_aq_init(void *dev, u16 qidx, u8 chan_offset, u16 sqb_aura) { struct otx2_nic *pfvf =3D dev; struct otx2_snd_queue *sq; @@ -903,7 +927,7 @@ int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura) aq->sq.ena =3D 1; aq->sq.smq =3D otx2_get_smq_idx(pfvf, qidx); aq->sq.smq_rr_quantum =3D mtu_to_dwrr_weight(pfvf, pfvf->tx_max_pktlen); - aq->sq.default_chan =3D pfvf->hw.tx_chan_base; + aq->sq.default_chan =3D pfvf->hw.tx_chan_base + chan_offset; aq->sq.sqe_stype =3D NIX_STYPE_STF; /* Cache SQB */ aq->sq.sqb_aura =3D sqb_aura; aq->sq.sq_int_ena =3D NIX_SQINT_BITS; @@ -926,6 +950,7 @@ int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 s= qb_aura) struct otx2_qset *qset =3D &pfvf->qset; struct otx2_snd_queue *sq; struct otx2_pool *pool; + u8 chan_offset; int err; =20 pool =3D &pfvf->qset.pool[sqb_aura]; @@ -972,7 +997,8 @@ int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 s= qb_aura) sq->stats.bytes =3D 0; sq->stats.pkts =3D 0; =20 - err =3D pfvf->hw_ops->sq_aq_init(pfvf, qidx, sqb_aura); + chan_offset =3D qidx % pfvf->hw.tx_chan_cnt; + err =3D pfvf->hw_ops->sq_aq_init(pfvf, qidx, chan_offset, sqb_aura); if (err) { kfree(sq->sg); sq->sg =3D NULL; @@ -1739,6 +1765,8 @@ void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, pfvf->hw.sqb_size =3D rsp->sqb_size; pfvf->hw.rx_chan_base =3D rsp->rx_chan_base; pfvf->hw.tx_chan_base =3D rsp->tx_chan_base; + pfvf->hw.rx_chan_cnt =3D rsp->rx_chan_cnt; + pfvf->hw.tx_chan_cnt =3D rsp->tx_chan_cnt; pfvf->hw.lso_tsov4_idx =3D rsp->lso_tsov4_idx; pfvf->hw.lso_tsov6_idx =3D rsp->lso_tsov6_idx; pfvf->hw.cgx_links =3D rsp->cgx_links; diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/dri= vers/net/ethernet/marvell/octeontx2/nic/otx2_common.h index 962b10f1583a..be28a19ec2d4 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h @@ -42,6 +42,8 @@ #define PCI_SUBSYS_DEVID_96XX_RVU_PFVF 0xB200 #define PCI_SUBSYS_DEVID_CN10K_B_RVU_PFVF 0xBD00 =20 +#define PCI_DEVID_OCTEONTX2_SDP_REP 0xA0F7 + /* PCI BAR nos */ #define PCI_CFG_REG_BAR_NUM 2 #define PCI_MBOX_BAR_NUM 4 @@ -198,6 +200,7 @@ struct otx2_hw { =20 /* NIX */ u8 txschq_link_cfg_lvl; + u8 txschq_cnt[NIX_TXSCH_LVL_CNT]; u8 txschq_aggr_lvl_rr_prio; u16 txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; u16 matchall_ipolicer; @@ -208,6 +211,8 @@ struct otx2_hw { /* HW settings, coalescing etc */ u16 rx_chan_base; u16 tx_chan_base; + u8 rx_chan_cnt; + u8 tx_chan_cnt; u16 cq_qcount_wait; u16 cq_ecount_wait; u16 rq_skid; @@ -342,7 +347,8 @@ struct otx2_flow_config { }; =20 struct dev_hw_ops { - int (*sq_aq_init)(void *dev, u16 qidx, u16 sqb_aura); + int (*sq_aq_init)(void *dev, u16 qidx, u8 chan_offset, + u16 sqb_aura); void (*sqe_flush)(void *dev, struct otx2_snd_queue *sq, int size, int qidx); int (*refill_pool_ptrs)(void *dev, struct otx2_cq_queue *cq); @@ -536,6 +542,11 @@ static inline bool is_96xx_B0(struct pci_dev *pdev) (pdev->subsystem_device =3D=3D PCI_SUBSYS_DEVID_96XX_RVU_PFVF); } =20 +static inline bool is_otx2_sdp_rep(struct pci_dev *pdev) +{ + return pdev->device =3D=3D PCI_DEVID_OCTEONTX2_SDP_REP; +} + /* REVID for PCIe devices. * Bits 0..1: minor pass, bit 3..2: major pass * bits 7..4: midr id @@ -898,15 +909,19 @@ static inline void otx2_dma_unmap_page(struct otx2_ni= c *pfvf, static inline u16 otx2_get_smq_idx(struct otx2_nic *pfvf, u16 qidx) { u16 smq; + int idx; + #ifdef CONFIG_DCB if (qidx < NIX_PF_PFC_PRIO_MAX && pfvf->pfc_alloc_status[qidx]) return pfvf->pfc_schq_list[NIX_TXSCH_LVL_SMQ][qidx]; #endif /* check if qidx falls under QOS queues */ - if (qidx >=3D pfvf->hw.non_qos_queues) + if (qidx >=3D pfvf->hw.non_qos_queues) { smq =3D pfvf->qos.qid_to_sqmap[qidx - pfvf->hw.non_qos_queues]; - else - smq =3D pfvf->hw.txschq_list[NIX_TXSCH_LVL_SMQ][0]; + } else { + idx =3D qidx % pfvf->hw.txschq_cnt[NIX_TXSCH_LVL_SMQ]; + smq =3D pfvf->hw.txschq_list[NIX_TXSCH_LVL_SMQ][idx]; + } =20 return smq; } @@ -973,8 +988,8 @@ int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enab= le); void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq,= int qidx); void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq); int otx2_sq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura); -int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura); -int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura); +int otx2_sq_aq_init(void *dev, u16 qidx, u8 chan_offset, u16 sqb_aura); +int cn10k_sq_aq_init(void *dev, u16 qidx, u8 chan_offset, u16 sqb_aura); int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, dma_addr_t *dma); int otx2_pool_init(struct otx2_nic *pfvf, u16 pool_id, diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers= /net/ethernet/marvell/octeontx2/nic/otx2_pf.c index 0d62f16af68b..e310f99b1736 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c @@ -1591,10 +1591,15 @@ int otx2_init_hw_resources(struct otx2_nic *pf) } =20 for (lvl =3D 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { - err =3D otx2_txschq_config(pf, lvl, 0, false); - if (err) { - mutex_unlock(&mbox->lock); - goto err_free_nix_queues; + int idx; + + for (idx =3D 0; idx < pf->hw.txschq_cnt[lvl]; idx++) { + err =3D otx2_txschq_config(pf, lvl, idx, false); + if (err) { + dev_err(pf->dev, "Failed to config TXSCH\n"); + mutex_unlock(&mbox->lock); + goto err_free_nix_queues; + } } } =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c b/drivers= /net/ethernet/marvell/octeontx2/nic/otx2_vf.c index 0486fca8b573..839fc77c11b2 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c @@ -21,6 +21,7 @@ static const struct pci_device_id otx2_vf_id_table[] =3D { { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AFVF) }, { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF) }, + { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_SDP_REP) }, { } }; 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Thu, 07 Nov 2024 08:09:21 -0800 (PST) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 7 Nov 2024 08:09:20 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 7 Nov 2024 08:09:20 -0800 Received: from hyd1soter3.marvell.com (unknown [10.29.37.12]) by maili.marvell.com (Postfix) with ESMTP id A74273F7050; Thu, 7 Nov 2024 08:09:16 -0800 (PST) From: Geetha sowjanya To: , CC: , , , , , , , , Subject: [net-next PATCH v12 09/12] octeontx2-pf: Add devlink port support Date: Thu, 7 Nov 2024 21:38:36 +0530 Message-ID: <20241107160839.23707-10-gakula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241107160839.23707-1-gakula@marvell.com> References: <20241107160839.23707-1-gakula@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: Pqoummvo8pC8CU0_FB_bYsO_qksl3Df0 X-Proofpoint-GUID: Pqoummvo8pC8CU0_FB_bYsO_qksl3Df0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.687,Hydra:6.0.235,FMLib:17.0.607.475 definitions=2020-10-13_15,2020-10-13_02,2020-04-07_01 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Register devlink port for the rvu representors. Signed-off-by: Geetha sowjanya Reviewed-by: Simon Horman --- v11-v2: - Used container_of to get rep_dev pointer. - Added code to forward the updated mac address to VF. =20 .../net/ethernet/marvell/octeontx2/af/mbox.h | 2 + .../ethernet/marvell/octeontx2/af/rvu_rep.c | 4 + .../net/ethernet/marvell/octeontx2/nic/rep.c | 90 +++++++++++++++++++ .../net/ethernet/marvell/octeontx2/nic/rep.h | 2 + 4 files changed, 98 insertions(+) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net= /ethernet/marvell/octeontx2/af/mbox.h index b583c964d30c..62c07407eb94 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h @@ -1583,6 +1583,7 @@ struct rep_evt_data { u16 rx_mode; u16 rx_flags; u16 mtu; + u8 mac[ETH_ALEN]; u64 rsvd[5]; }; =20 @@ -1593,6 +1594,7 @@ struct rep_event { #define RVU_EVENT_PFVF_STATE BIT_ULL(1) #define RVU_EVENT_MTU_CHANGE BIT_ULL(2) #define RVU_EVENT_RX_MODE_CHANGE BIT_ULL(3) +#define RVU_EVENT_MAC_ADDR_CHANGE BIT_ULL(4) u16 event; struct rep_evt_data evt_data; }; diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_rep.c index 80947fa28138..97b682291e3f 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c @@ -35,11 +35,15 @@ MBOX_UP_REP_MESSAGES =20 static int rvu_rep_up_notify(struct rvu *rvu, struct rep_event *event) { + struct rvu_pfvf *pfvf =3D rvu_get_pfvf(rvu, event->pcifunc); struct rep_event *msg; int pf; =20 pf =3D rvu_get_pf(event->pcifunc); =20 + if (event->event & RVU_EVENT_MAC_ADDR_CHANGE) + ether_addr_copy(pfvf->mac_addr, event->evt_data.mac); + mutex_lock(&rvu->mbox_lock); msg =3D otx2_mbox_alloc_msg_rep_event_up_notify(rvu, pf); if (!msg) { diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/rep.c b/drivers/net= /ethernet/marvell/octeontx2/nic/rep.c index d4e78015ef71..15e775027c38 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/rep.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/rep.c @@ -28,6 +28,89 @@ MODULE_DESCRIPTION(DRV_STRING); MODULE_LICENSE("GPL"); MODULE_DEVICE_TABLE(pci, rvu_rep_id_table); =20 +static int rvu_rep_notify_pfvf(struct otx2_nic *priv, u16 event, + struct rep_event *data); + +static int rvu_rep_dl_port_fn_hw_addr_get(struct devlink_port *port, + u8 *hw_addr, int *hw_addr_len, + struct netlink_ext_ack *extack) +{ + struct rep_dev *rep =3D container_of(port, struct rep_dev, dl_port); + + ether_addr_copy(hw_addr, rep->mac); + *hw_addr_len =3D ETH_ALEN; + return 0; +} + +static int rvu_rep_dl_port_fn_hw_addr_set(struct devlink_port *port, + const u8 *hw_addr, int hw_addr_len, + struct netlink_ext_ack *extack) +{ + struct rep_dev *rep =3D container_of(port, struct rep_dev, dl_port); + struct otx2_nic *priv =3D rep->mdev; + struct rep_event evt =3D {0}; + + eth_hw_addr_set(rep->netdev, hw_addr); + ether_addr_copy(rep->mac, hw_addr); + + ether_addr_copy(evt.evt_data.mac, hw_addr); + evt.pcifunc =3D rep->pcifunc; + rvu_rep_notify_pfvf(priv, RVU_EVENT_MAC_ADDR_CHANGE, &evt); + return 0; +} + +static const struct devlink_port_ops rvu_rep_dl_port_ops =3D { + .port_fn_hw_addr_get =3D rvu_rep_dl_port_fn_hw_addr_get, + .port_fn_hw_addr_set =3D rvu_rep_dl_port_fn_hw_addr_set, +}; + +static void +rvu_rep_devlink_set_switch_id(struct otx2_nic *priv, + struct netdev_phys_item_id *ppid) +{ + struct pci_dev *pdev =3D priv->pdev; + u64 id; + + id =3D pci_get_dsn(pdev); + + ppid->id_len =3D sizeof(id); + put_unaligned_be64(id, &ppid->id); +} + +static void rvu_rep_devlink_port_unregister(struct rep_dev *rep) +{ + devlink_port_unregister(&rep->dl_port); +} + +static int rvu_rep_devlink_port_register(struct rep_dev *rep) +{ + struct devlink_port_attrs attrs =3D {}; + struct otx2_nic *priv =3D rep->mdev; + struct devlink *dl =3D priv->dl->dl; + int err; + + if (!(rep->pcifunc & RVU_PFVF_FUNC_MASK)) { + attrs.flavour =3D DEVLINK_PORT_FLAVOUR_PHYSICAL; + attrs.phys.port_number =3D rvu_get_pf(rep->pcifunc); + } else { + attrs.flavour =3D DEVLINK_PORT_FLAVOUR_PCI_VF; + attrs.pci_vf.pf =3D rvu_get_pf(rep->pcifunc); + attrs.pci_vf.vf =3D rep->pcifunc & RVU_PFVF_FUNC_MASK; + } + + rvu_rep_devlink_set_switch_id(priv, &attrs.switch_id); + devlink_port_attrs_set(&rep->dl_port, &attrs); + + err =3D devl_port_register_with_ops(dl, &rep->dl_port, rep->rep_id, + &rvu_rep_dl_port_ops); + if (err) { + dev_err(rep->mdev->dev, "devlink_port_register failed: %d\n", + err); + return err; + } + return 0; +} + static int rvu_rep_get_repid(struct otx2_nic *priv, u16 pcifunc) { int rep_id; @@ -386,6 +469,7 @@ void rvu_rep_destroy(struct otx2_nic *priv) for (rep_id =3D 0; rep_id < priv->rep_cnt; rep_id++) { rep =3D priv->reps[rep_id]; unregister_netdev(rep->netdev); + rvu_rep_devlink_port_unregister(rep); free_netdev(rep->netdev); } kfree(priv->reps); @@ -439,6 +523,11 @@ int rvu_rep_create(struct otx2_nic *priv, struct netli= nk_ext_ack *extack) =20 ndev->features |=3D ndev->hw_features; eth_hw_addr_random(ndev); + err =3D rvu_rep_devlink_port_register(rep); + if (err) + goto exit; + + SET_NETDEV_DEVLINK_PORT(ndev, &rep->dl_port); err =3D register_netdev(ndev); if (err) { NL_SET_ERR_MSG_MOD(extack, @@ -459,6 +548,7 @@ int rvu_rep_create(struct otx2_nic *priv, struct netlin= k_ext_ack *extack) while (--rep_id >=3D 0) { rep =3D priv->reps[rep_id]; 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charset="utf-8" Implement the offload stat ndo by fetching the HW stats of rx/tx queues attached to the representor. Signed-off-by: Geetha sowjanya Reviewed-by: Simon Horman --- .../marvell/octeontx2/nic/otx2_common.c | 2 + .../net/ethernet/marvell/octeontx2/nic/rep.c | 41 +++++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c b/dri= vers/net/ethernet/marvell/octeontx2/nic/otx2_common.c index 46a448030e64..523ecb798a7a 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c @@ -83,6 +83,7 @@ int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx) otx2_nix_rq_op_stats(&rq->stats, pfvf, qidx); return 1; } +EXPORT_SYMBOL(otx2_update_rq_stats); =20 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx) { @@ -99,6 +100,7 @@ int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx) otx2_nix_sq_op_stats(&sq->stats, pfvf, qidx); return 1; } +EXPORT_SYMBOL(otx2_update_sq_stats); =20 void otx2_get_dev_stats(struct otx2_nic *pfvf) { diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/rep.c b/drivers/net= /ethernet/marvell/octeontx2/nic/rep.c index 15e775027c38..1806d050c143 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/rep.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/rep.c @@ -31,6 +31,45 @@ MODULE_DEVICE_TABLE(pci, rvu_rep_id_table); static int rvu_rep_notify_pfvf(struct otx2_nic *priv, u16 event, struct rep_event *data); =20 +static int +rvu_rep_sp_stats64(const struct net_device *dev, + struct rtnl_link_stats64 *stats) +{ + struct rep_dev *rep =3D netdev_priv(dev); + struct otx2_nic *priv =3D rep->mdev; + struct otx2_rcv_queue *rq; + struct otx2_snd_queue *sq; + u16 qidx =3D rep->rep_id; + + otx2_update_rq_stats(priv, qidx); + rq =3D &priv->qset.rq[qidx]; + + otx2_update_sq_stats(priv, qidx); + sq =3D &priv->qset.sq[qidx]; + + stats->tx_bytes =3D sq->stats.bytes; + stats->tx_packets =3D sq->stats.pkts; + stats->rx_bytes =3D rq->stats.bytes; + stats->rx_packets =3D rq->stats.pkts; + return 0; +} + +static bool +rvu_rep_has_offload_stats(const struct net_device *dev, int attr_id) +{ + return attr_id =3D=3D IFLA_OFFLOAD_XSTATS_CPU_HIT; +} + +static int +rvu_rep_get_offload_stats(int attr_id, const struct net_device *dev, + void *sp) +{ + if (attr_id =3D=3D IFLA_OFFLOAD_XSTATS_CPU_HIT) + return rvu_rep_sp_stats64(dev, (struct rtnl_link_stats64 *)sp); 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charset="utf-8" Implements tc offload support for rvu representors.=20 Usage example: - Add tc rule to drop packets with vlan id 3 using port representor(Rpf1vf0).=20 # tc filter add dev Rpf1vf0 protocol 802.1Q parent ffff: flower vlan_id 3 vlan_ethtype ipv4 skip_sw action drop - Redirect packets with vlan id 5 and IPv4 packets to eth1, after stripping vlan header. # tc filter add dev Rpf1vf0 ingress protocol 802.1Q flower vlan_id 5 vlan_ethtype ipv4 skip_sw action vlan pop action mirred ingress redirect dev eth1 Signed-off-by: Geetha sowjanya --- .../marvell/octeontx2/af/rvu_npc_fs.c | 14 ++- .../ethernet/marvell/octeontx2/af/rvu_rep.c | 4 + .../marvell/octeontx2/nic/otx2_common.h | 7 ++ .../marvell/octeontx2/nic/otx2_flows.c | 5 - .../ethernet/marvell/octeontx2/nic/otx2_tc.c | 25 ++-- .../net/ethernet/marvell/octeontx2/nic/rep.c | 115 ++++++++++++++++++ .../net/ethernet/marvell/octeontx2/nic/rep.h | 1 + 7 files changed, 154 insertions(+), 17 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c b/drive= rs/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c index 150635de2bd5..9d08fd466a43 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c @@ -1416,6 +1416,7 @@ int rvu_mbox_handler_npc_install_flow(struct rvu *rvu, struct npc_install_flow_rsp *rsp) { bool from_vf =3D !!(req->hdr.pcifunc & RVU_PFVF_FUNC_MASK); + bool from_rep_dev =3D !!is_rep_dev(rvu, req->hdr.pcifunc); struct rvu_switch *rswitch =3D &rvu->rswitch; int blkaddr, nixlf, err; struct rvu_pfvf *pfvf; @@ -1472,14 +1473,19 @@ int rvu_mbox_handler_npc_install_flow(struct rvu *r= vu, /* AF installing for a PF/VF */ if (!req->hdr.pcifunc) target =3D req->vf; + /* PF installing for its VF */ - else if (!from_vf && req->vf) { + if (!from_vf && req->vf && !from_rep_dev) { target =3D (req->hdr.pcifunc & ~RVU_PFVF_FUNC_MASK) | req->vf; pf_set_vfs_mac =3D req->default_rule && (req->features & BIT_ULL(NPC_DMAC)); } - /* msg received from PF/VF */ + + /* Representor device installing for a representee */ + if (from_rep_dev && req->vf) + target =3D req->vf; else + /* msg received from PF/VF */ target =3D req->hdr.pcifunc; =20 /* ignore chan_mask in case pf func is not AF, revisit later */ @@ -1492,8 +1498,10 @@ int rvu_mbox_handler_npc_install_flow(struct rvu *rv= u, =20 pfvf =3D rvu_get_pfvf(rvu, target); =20 + if (from_rep_dev) + req->channel =3D pfvf->rx_chan_base; /* PF installing for its VF */ - if (req->hdr.pcifunc && !from_vf && req->vf) + if (req->hdr.pcifunc && !from_vf && req->vf && !from_rep_dev) set_bit(PF_SET_VF_CFG, &pfvf->flags); =20 /* update req destination mac addr */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_rep.c index 97b682291e3f..052ae5923e3a 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c @@ -427,6 +427,10 @@ int rvu_mbox_handler_esw_cfg(struct rvu *rvu, struct e= sw_cfg_req *req, return 0; =20 rvu->rep_mode =3D req->ena; + + if (!rvu->rep_mode) + rvu_npc_free_mcam_entries(rvu, req->hdr.pcifunc, -1); + return 0; } =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/dri= vers/net/ethernet/marvell/octeontx2/nic/otx2_common.h index be28a19ec2d4..566848663fea 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h @@ -1142,4 +1142,11 @@ int otx2_get_txq_by_classid(struct otx2_nic *pfvf, u= 16 classid); void otx2_qos_config_txschq(struct otx2_nic *pfvf); void otx2_clean_qos_queues(struct otx2_nic *pfvf); int rvu_event_up_notify(struct otx2_nic *pf, struct rep_event *info); +int otx2_setup_tc_cls_flower(struct otx2_nic *nic, + struct flow_cls_offload *cls_flower); + +static inline int mcam_entry_cmp(const void *a, const void *b) +{ + return *(u16 *)a - *(u16 *)b; +} #endif /* OTX2_COMMON_H */ diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c b/driv= ers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c index 58720a161ee2..47bfd1fb37d4 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c @@ -64,11 +64,6 @@ static int otx2_free_ntuple_mcam_entries(struct otx2_nic= *pfvf) return 0; } =20 -static int mcam_entry_cmp(const void *a, const void *b) -{ - return *(u16 *)a - *(u16 *)b; -} - int otx2_alloc_mcam_entries(struct otx2_nic *pfvf, u16 count) { struct otx2_flow_config *flow_cfg =3D pfvf->flow_cfg; diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c b/drivers= /net/ethernet/marvell/octeontx2/nic/otx2_tc.c index e63cc1eb6d89..9a226ca74425 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c @@ -443,6 +443,7 @@ static int otx2_tc_parse_actions(struct otx2_nic *nic, struct flow_action_entry *act; struct net_device *target; struct otx2_nic *priv; + struct rep_dev *rdev; u32 burst, mark =3D 0; u8 nr_police =3D 0; u8 num_intf =3D 1; @@ -464,14 +465,18 @@ static int otx2_tc_parse_actions(struct otx2_nic *nic, return 0; case FLOW_ACTION_REDIRECT_INGRESS: target =3D act->dev; - priv =3D netdev_priv(target); - /* npc_install_flow_req doesn't support passing a target pcifunc */ - if (rvu_get_pf(nic->pcifunc) !=3D rvu_get_pf(priv->pcifunc)) { - NL_SET_ERR_MSG_MOD(extack, - "can't redirect to other pf/vf"); - return -EOPNOTSUPP; + if (target->dev.parent) { + priv =3D netdev_priv(target); + if (rvu_get_pf(nic->pcifunc) !=3D rvu_get_pf(priv->pcifunc)) { + NL_SET_ERR_MSG_MOD(extack, + "can't redirect to other pf/vf"); + return -EOPNOTSUPP; + } + req->vf =3D priv->pcifunc & RVU_PFVF_FUNC_MASK; + } else { + rdev =3D netdev_priv(target); + req->vf =3D rdev->pcifunc & RVU_PFVF_FUNC_MASK; } - req->vf =3D priv->pcifunc & RVU_PFVF_FUNC_MASK; =20 /* if op is already set; avoid overwriting the same */ if (!req->op) @@ -1300,6 +1305,7 @@ static int otx2_tc_add_flow(struct otx2_nic *nic, req->channel =3D nic->hw.rx_chan_base; req->entry =3D flow_cfg->flow_ent[mcam_idx]; req->intf =3D NIX_INTF_RX; + req->vf =3D nic->pcifunc; req->set_cntr =3D 1; new_node->entry =3D req->entry; =20 @@ -1400,8 +1406,8 @@ static int otx2_tc_get_flow_stats(struct otx2_nic *ni= c, return 0; } =20 -static int otx2_setup_tc_cls_flower(struct otx2_nic *nic, - struct flow_cls_offload *cls_flower) +int otx2_setup_tc_cls_flower(struct otx2_nic *nic, + struct flow_cls_offload *cls_flower) { switch (cls_flower->command) { case FLOW_CLS_REPLACE: @@ -1414,6 +1420,7 @@ static int otx2_setup_tc_cls_flower(struct otx2_nic *= nic, return -EOPNOTSUPP; } } +EXPORT_SYMBOL(otx2_setup_tc_cls_flower); =20 static int otx2_tc_ingress_matchall_install(struct otx2_nic *nic, struct tc_cls_matchall_offload *cls) diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/rep.c b/drivers/net= /ethernet/marvell/octeontx2/nic/rep.c index 1806d050c143..ae58d0601b45 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/rep.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/rep.c @@ -9,6 +9,7 @@ #include #include #include +#include =20 #include "otx2_common.h" #include "cn10k.h" @@ -31,6 +32,117 @@ MODULE_DEVICE_TABLE(pci, rvu_rep_id_table); static int rvu_rep_notify_pfvf(struct otx2_nic *priv, u16 event, struct rep_event *data); =20 +static int rvu_rep_mcam_flow_init(struct rep_dev *rep) +{ + struct npc_mcam_alloc_entry_req *req; + struct npc_mcam_alloc_entry_rsp *rsp; + struct otx2_nic *priv =3D rep->mdev; + int ent, allocated =3D 0; + int count; + + rep->flow_cfg =3D kcalloc(1, sizeof(struct otx2_flow_config), GFP_KERNEL); + + if (!rep->flow_cfg) + return -ENOMEM; + + count =3D OTX2_DEFAULT_FLOWCOUNT; + + rep->flow_cfg->flow_ent =3D kcalloc(count, sizeof(u16), GFP_KERNEL); + if (!rep->flow_cfg->flow_ent) + return -ENOMEM; + + while (allocated < count) { + req =3D otx2_mbox_alloc_msg_npc_mcam_alloc_entry(&priv->mbox); + if (!req) + goto exit; + + req->hdr.pcifunc =3D rep->pcifunc; + req->contig =3D false; + req->ref_entry =3D 0; + req->count =3D (count - allocated) > NPC_MAX_NONCONTIG_ENTRIES ? + NPC_MAX_NONCONTIG_ENTRIES : count - allocated; + + if (otx2_sync_mbox_msg(&priv->mbox)) + goto exit; + + rsp =3D (struct npc_mcam_alloc_entry_rsp *)otx2_mbox_get_rsp + (&priv->mbox.mbox, 0, &req->hdr); + + for (ent =3D 0; ent < rsp->count; ent++) + rep->flow_cfg->flow_ent[ent + allocated] =3D rsp->entry_list[ent]; + + allocated +=3D rsp->count; + + if (rsp->count !=3D req->count) + break; + } +exit: + /* Multiple MCAM entry alloc requests could result in non-sequential + * MCAM entries in the flow_ent[] array. Sort them in an ascending + * order, otherwise user installed ntuple filter index and MCAM entry + * index will not be in sync. + */ + if (allocated) + sort(&rep->flow_cfg->flow_ent[0], allocated, + sizeof(rep->flow_cfg->flow_ent[0]), mcam_entry_cmp, NULL); + + mutex_unlock(&priv->mbox.lock); + + rep->flow_cfg->max_flows =3D allocated; + + if (allocated) { + rep->flags |=3D OTX2_FLAG_MCAM_ENTRIES_ALLOC; + rep->flags |=3D OTX2_FLAG_NTUPLE_SUPPORT; + rep->flags |=3D OTX2_FLAG_TC_FLOWER_SUPPORT; + } + + INIT_LIST_HEAD(&rep->flow_cfg->flow_list); + INIT_LIST_HEAD(&rep->flow_cfg->flow_list_tc); + return 0; +} + +static int rvu_rep_setup_tc_cb(enum tc_setup_type type, + void *type_data, void *cb_priv) +{ + struct rep_dev *rep =3D cb_priv; + struct otx2_nic *priv =3D rep->mdev; + + if (!(rep->flags & RVU_REP_VF_INITIALIZED)) + return -EINVAL; + + if (!(rep->flags & OTX2_FLAG_TC_FLOWER_SUPPORT)) + rvu_rep_mcam_flow_init(rep); + + priv->netdev =3D rep->netdev; + priv->flags =3D rep->flags; + priv->pcifunc =3D rep->pcifunc; + priv->flow_cfg =3D rep->flow_cfg; + + switch (type) { + case TC_SETUP_CLSFLOWER: + return otx2_setup_tc_cls_flower(priv, type_data); + default: + return -EOPNOTSUPP; + } +} + +static LIST_HEAD(rvu_rep_block_cb_list); +static int rvu_rep_setup_tc(struct net_device *netdev, enum tc_setup_type = type, + void *type_data) +{ + struct rvu_rep *rep =3D netdev_priv(netdev); + + switch (type) { + case TC_SETUP_BLOCK: + return flow_block_cb_setup_simple(type_data, + &rvu_rep_block_cb_list, + rvu_rep_setup_tc_cb, + rep, rep, true); + default: + return -EOPNOTSUPP; + } +} + static int rvu_rep_sp_stats64(const struct net_device *dev, struct rtnl_link_stats64 *stats) @@ -367,6 +479,7 @@ static const struct net_device_ops rvu_rep_netdev_ops = =3D { .ndo_change_mtu =3D rvu_rep_change_mtu, .ndo_has_offload_stats =3D rvu_rep_has_offload_stats, .ndo_get_offload_stats =3D rvu_rep_get_offload_stats, + .ndo_setup_tc =3D rvu_rep_setup_tc, }; =20 static int rvu_rep_napi_init(struct otx2_nic *priv, @@ -512,6 +625,7 @@ void rvu_rep_destroy(struct otx2_nic *priv) unregister_netdev(rep->netdev); rvu_rep_devlink_port_unregister(rep); free_netdev(rep->netdev); + kfree(rep->flow_cfg); } kfree(priv->reps); rvu_rep_rsrc_free(priv); @@ -562,6 +676,7 @@ int rvu_rep_create(struct otx2_nic *priv, struct netlin= k_ext_ack *extack) NETIF_F_IPV6_CSUM | NETIF_F_RXHASH | NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6); =20 + ndev->hw_features |=3D NETIF_F_HW_TC; ndev->features |=3D ndev->hw_features; eth_hw_addr_random(ndev); err =3D rvu_rep_devlink_port_register(rep); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/rep.h b/drivers/net= /ethernet/marvell/octeontx2/nic/rep.h index 163913c3b30f..38446b3e4f13 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/rep.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/rep.h @@ -35,6 +35,7 @@ struct rep_dev { struct rep_stats stats; struct delayed_work stats_wrk; struct devlink_port dl_port; + struct otx2_flow_config *flow_cfg; #define RVU_REP_VF_INITIALIZED BIT_ULL(0) u64 flags; u16 rep_id; --=20 2.25.1 From nobody Sun Nov 24 03:06:22 2024 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A0B6215F58; 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Thu, 07 Nov 2024 08:09:33 -0800 (PST) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 7 Nov 2024 08:09:32 -0800 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 7 Nov 2024 08:09:32 -0800 Received: from hyd1soter3.marvell.com (unknown [10.29.37.12]) by maili.marvell.com (Postfix) with ESMTP id 67E433F7050; Thu, 7 Nov 2024 08:09:28 -0800 (PST) From: Geetha sowjanya To: , CC: , , , , , , , , Subject: [net-next PATCH v12 12/12] Documentation: octeontx2: Add Documentation for RVU representors Date: Thu, 7 Nov 2024 21:38:39 +0530 Message-ID: <20241107160839.23707-13-gakula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241107160839.23707-1-gakula@marvell.com> References: <20241107160839.23707-1-gakula@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: MhKRTfan-QLMpAFyvNjnbsIZmxD7unIy X-Proofpoint-ORIG-GUID: MhKRTfan-QLMpAFyvNjnbsIZmxD7unIy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Adds documentation for creating and configuring rvu port representors Signed-off-by: Geetha sowjanya --- .../ethernet/marvell/octeontx2.rst | 91 +++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/Documentation/networking/device_drivers/ethernet/marvell/octeo= ntx2.rst b/Documentation/networking/device_drivers/ethernet/marvell/octeont= x2.rst index 1e196cb9ce25..af7db0e91f6b 100644 --- a/Documentation/networking/device_drivers/ethernet/marvell/octeontx2.rst +++ b/Documentation/networking/device_drivers/ethernet/marvell/octeontx2.rst @@ -14,6 +14,7 @@ Contents - `Basic packet flow`_ - `Devlink health reporters`_ - `Quality of service`_ +- `RVU representors`_ =20 Overview =3D=3D=3D=3D=3D=3D=3D=3D @@ -340,3 +341,93 @@ Setup HTB offload # tc class add dev parent 1: classid 1:2 htb rate 10Gb= it prio 2 quantum 188416 =20 # tc class add dev parent 1: classid 1:3 htb rate 10Gb= it prio 2 quantum 32768 + + +RVU Representors +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +RVU representor driver adds support for creation of representor devices for +RVU PFs' VFs in the system. Representor devices are created when user enab= les +the switchdev mode. +Switchdev mode can be enabled either before or after setting up SRIOV numV= Fs. +All representor devices share a single NIXLF but each has a dedicated Rx/Tx +queues. RVU PF representor driver registers a separate netdev for each +Rx/Tx queue pair. + +Current HW does not support built-in switch which can do L2 learning and +forwarding packets between representee and representor. Hence, packet path +between representee and it's representor is achieved by setting up appropr= iate +NPC MCAM filters. +Transmit packets matching these filters will be loopbacked through hardware +loopback channel/interface (i.e, instead of sending them out of MAC interf= ace). +Which will again match the installed filters and will be forwarded. +This way representee =3D> representor and representor =3D> representee pac= ket +path is achieved. These rules get installed when representors are created +and gets active/deactivate based on the representor/representee interface = state. + +Usage example: + + - Change device to switchdev mode:: + + # devlink dev eswitch set pci/0002:1c:00.0 mode switchdev + + - List of representor devices on the system:: + + # ip link show + Rpf1vf0: mtu 1500 qdisc pfifo_fast stat= e DOWN mode DEFAULT group default qlen 1000 link/ether f6:43:83:ee:26:21 br= d ff:ff:ff:ff:ff:ff + Rpf1vf1: mtu 1500 qdisc pfifo_fast stat= e DOWN mode DEFAULT group default qlen 1000 link/ether 12:b2:54:0e:24:54 br= d ff:ff:ff:ff:ff:ff + Rpf1vf2: mtu 1500 qdisc pfifo_fast stat= e DOWN mode DEFAULT group default qlen 1000 link/ether 4a:12:c4:4c:32:62 br= d ff:ff:ff:ff:ff:ff + Rpf1vf3: mtu 1500 qdisc pfifo_fast stat= e DOWN mode DEFAULT group default qlen 1000 link/ether ca:cb:68:0e:e2:6e br= d ff:ff:ff:ff:ff:ff + Rpf2vf0: mtu 1500 qdisc pfifo_fast stat= e DOWN mode DEFAULT group default qlen 1000 link/ether 06:cc:ad:b4:f0:93 br= d ff:ff:ff:ff:ff:ff + + +To delete the representors devices from the system. Change the device to l= egacy mode. + + - Change device to legacy mode:: + + # devlink dev eswitch set pci/0002:1c:00.0 mode legacy + +RVU representors can be managed using devlink ports +(see :ref:`Documentation/networking/devlink/devlink-port.rst `) interface. + + - Show devlink ports of representors:: + + # devlink port + pci/0002:1c:00.0/0: type eth netdev Rpf1vf0 flavour physical port 0 split= table false + pci/0002:1c:00.0/1: type eth netdev Rpf1vf1 flavour pcivf controller 0 pf= num 1 vfnum 1 external false splittable false + pci/0002:1c:00.0/2: type eth netdev Rpf1vf2 flavour pcivf controller 0 pf= num 1 vfnum 2 external false splittable false + pci/0002:1c:00.0/3: type eth netdev Rpf1vf3 flavour pcivf controller 0 pf= num 1 vfnum 3 external false splittable false + +Function attributes +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The RVU representor support function attributes for representors. +Port function configuration of the representors are supported through devl= ink eswitch port. + +MAC address setup +----------------- + +RVU representor driver support devlink port function attr mechanism to set= up MAC +address. (refer to Documentation/networking/devlink/devlink-port.rst) + + - To setup MAC address for port 2:: + + # devlink port function set pci/0002:1c:00.0/2 hw_addr 5c:a1:1b:5e:43:11 + # devlink port show pci/0002:1c:00.0/2 + pci/0002:1c:00.0/2: type eth netdev Rpf1vf2 flavour pcivf controller 0 pf= num 1 vfnum 2 external false splittable false + function: + hw_addr 5c:a1:1b:5e:43:11 + + +TC offload +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The rvu representor driver implements support for offloading tc rules usin= g port representors. + + - Drop packets with vlan id 3:: + + # tc filter add dev Rpf1vf0 protocol 802.1Q parent ffff: flower vlan_id 3= vlan_ethtype ipv4 skip_sw action drop + + - Redirect packets with vlan id 5 and IPv4 packets to eth1, after strippi= ng vlan header.:: + + # tc filter add dev Rpf1vf0 ingress protocol 802.1Q flower vlan_id 5 vlan= _ethtype ipv4 skip_sw action vlan pop action mirred ingress redirect dev et= h1 --=20 2.25.1