From nobody Sun Nov 24 07:00:53 2024 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6573321218E for ; Thu, 7 Nov 2024 13:26:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730985996; cv=none; b=qHNB4w/y1rQzx4fDdrvPM7wVmH6byn56LnByiiAsbgHJRjtmOXvU3BbiLXoJdYcCHiLddzVDXakXRp8qXov+CsMUMC55IuTXCk4a6BMWjhkz+PvqLxbkt7ciJBdksro7Sko4QiLsSJRCGWNH8A5gUJCQF48iy/d8GnIRmaMNQhE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730985996; c=relaxed/simple; bh=2geMWtR1gyVZ3pH9RD9xPM3qBW5E9vn9pyoLUI63Cz0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=SBQGLQ9kyZ00cR69ZtOjEokDCSlzH7OopHm8r3efpYNPr2FX9ZdeC2CKJhCskigRZI3u++Kw92m7L6QT9pqjXRfnA8OUz190u+UL4Lo16EQ8GfW2Q5iRzioq+eOUGodFzl9GBtD5G1vem4JsvqvCbCLEzxLIdf63DNChOlBOFj0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=At4fWGX2; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="At4fWGX2" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730985995; x=1762521995; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2geMWtR1gyVZ3pH9RD9xPM3qBW5E9vn9pyoLUI63Cz0=; b=At4fWGX2rCze9woElZwqRibIuStg8CKicO/tjtQRithPQBXwpsG4tg/Q SvUHVR0P7wArfxvdVdlQUN5T5pUwzB/fzOeIMfpWBuipRsHcxvwUSmhbj bFeZlQFkf6BjHGLln5bPKcLIJxfVprlENPnPls2sjelB40bikAZiTzGxi pQ/H8UzkBezZAwTWpOMbDY+HJHclY628GZeA4ptDRPjeudOCrokI/5qLT 6HCkcp5QqOlJ7T7/FtNtmqUEZC9B+QZF3zS4gNkgKTi2BVO5kLdhAfLW+ zNgIXSW5G1y3eRzvwQeJyFwgHT66usBwNWl5/L/2xJuVMoWyg0PR2jnrJ Q==; X-CSE-ConnectionGUID: XFTfsdYaTc6ymCJssqG9uA== X-CSE-MsgGUID: xl7/P3qvQzqcM5nvIqWvKg== X-IronPort-AV: E=McAfee;i="6700,10204,11249"; a="34750801" X-IronPort-AV: E=Sophos;i="6.12,266,1728975600"; d="scan'208";a="34750801" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2024 05:26:35 -0800 X-CSE-ConnectionGUID: HHFEaR3FQOG3XdbS/smHvw== X-CSE-MsgGUID: cVfj+kOWQayJ5r2SICi7jQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,266,1728975600"; d="scan'208";a="89921755" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2024 05:26:31 -0800 From: Alexander Usyskin To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Rodrigo Vivi , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jani Nikula , Joonas Lahtinen , Tvrtko Ursulin Cc: Oren Weil , linux-mtd@lists.infradead.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Alexander Usyskin Subject: [PATCH v2 08/10] drm/i915/nvm: add support for access mode Date: Thu, 7 Nov 2024 15:13:54 +0200 Message-ID: <20241107131356.2796969-9-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241107131356.2796969-1-alexander.usyskin@intel.com> References: <20241107131356.2796969-1-alexander.usyskin@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Check NVM access mode from GSC FW status registers and overwrite access status read from SPI descriptor, if needed. Signed-off-by: Alexander Usyskin Reviewed-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_nvm.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_nvm.c b/drivers/gpu/drm/i915/intel_= nvm.c index 214c4d47a9cd..cbd776e667ad 100644 --- a/drivers/gpu/drm/i915/intel_nvm.c +++ b/drivers/gpu/drm/i915/intel_nvm.c @@ -10,6 +10,7 @@ #include "intel_nvm.h" =20 #define GEN12_GUNIT_NVM_SIZE 0x80 +#define HECI_FW_STATUS_2_NVM_ACCESS_MODE BIT(3) =20 static const struct intel_dg_nvm_region regions[INTEL_DG_NVM_REGIONS] =3D { [0] =3D { .name =3D "DESCRIPTOR", }, @@ -22,6 +23,28 @@ static void i915_nvm_release_dev(struct device *dev) { } =20 +static bool i915_nvm_writeable_override(struct drm_i915_private *i915) +{ + resource_size_t base; + bool writeable_override; + + if (IS_DG1(i915)) { + base =3D DG1_GSC_HECI2_BASE; + } else if (IS_DG2(i915)) { + base =3D DG2_GSC_HECI2_BASE; + } else { + drm_err(&i915->drm, "Unknown platform\n"); + return true; + } + + writeable_override =3D + !(intel_uncore_read(&i915->uncore, HECI_FWSTS(base, 2)) & + HECI_FW_STATUS_2_NVM_ACCESS_MODE); + if (writeable_override) + drm_info(&i915->drm, "NVM access overridden by jumper\n"); + return writeable_override; +} + void intel_nvm_init(struct drm_i915_private *i915) { struct pci_dev *pdev =3D to_pci_dev(i915->drm.dev); @@ -43,7 +66,7 @@ void intel_nvm_init(struct drm_i915_private *i915) =20 nvm =3D i915->nvm; =20 - nvm->writeable_override =3D true; + nvm->writeable_override =3D i915_nvm_writeable_override(i915); nvm->bar.parent =3D &pdev->resource[0]; nvm->bar.start =3D GEN12_GUNIT_NVM_BASE + pdev->resource[0].start; nvm->bar.end =3D nvm->bar.start + GEN12_GUNIT_NVM_SIZE - 1; --=20 2.43.0