From nobody Sun Nov 24 07:28:05 2024 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E73F212621 for ; Thu, 7 Nov 2024 13:26:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730985971; cv=none; b=nNiMAdqiJ1vK7+IKN71OYrV0Teb4J04uYjFF/YDWDV+tRdXwBYnFX2cd98s4zrcTAhGrj78kf/VCTw8os82eP18RJ4qzDIXWGIjJGFTrISYyc7965PEm+iFfpjdehF6lu3MsCjibpDlS7Hf7nSRnMRVtSvMN80cLyeOYu6x8uWs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730985971; c=relaxed/simple; bh=/oGYqTRoYrw0kJoOL+qCTK39HQpO/vcPi+VprpOcqgs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=k42PbmbuCgmJzHtAvKGvG9NiRLdN/xKYyz5NyJ46lX4jHZgqiV4ZjTNIP/Ab/cy6op1BBklpxYEpwLD8bVIOrf354m9bhVJxTKI4M+UuFUCwkndNFLW0rIWkk+h5WdcAbhrNot3oVZK9fL3bQb0vTm2qOag3MllWf8ZFXdoPBvI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Y1DoU2YS; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Y1DoU2YS" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730985970; x=1762521970; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/oGYqTRoYrw0kJoOL+qCTK39HQpO/vcPi+VprpOcqgs=; b=Y1DoU2YSB5A9mTxII+aC4WEqRG8ZFllTt8i2ZQ/yDAvZ6x5GeL64Usqx vLfnaIR3S6MHRf65zDLrGVg43HMzxnVZv7GekDp1H8+KYBrbP6C5I8meC Jw/TPg28QutspK30+0yLxxDvpeGBsFqj17/XNWlT2k58/qW91+s6V6+Ef r4cnE+1Z3OBhcwPE08HBZ88LpiRDl0Sn3wepZbVoAeDKKb9WsED4up2Ic 7VQmE1lrJyLIyWirrQmyo0pgsqSLgxyue3tnkRbEtAcG8ZDMNZdoyuhtG 5dJ0xTzkyj+d2vUYh0E757RP4o657lH1+P9BdX7l+UvV5UBgbLf7W3eGD g==; X-CSE-ConnectionGUID: DAO/IZavR1+Tq6jFTjEw4Q== X-CSE-MsgGUID: vXgwlO6aSFWBBurdvoB+9g== X-IronPort-AV: E=McAfee;i="6700,10204,11249"; a="34750743" X-IronPort-AV: E=Sophos;i="6.12,266,1728975600"; d="scan'208";a="34750743" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2024 05:26:09 -0800 X-CSE-ConnectionGUID: fdS8mftbTPaNiGjJFBjJNg== X-CSE-MsgGUID: DGMGRFdTQk6YQxPU2W9TUQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,266,1728975600"; d="scan'208";a="89921688" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2024 05:26:05 -0800 From: Alexander Usyskin To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Rodrigo Vivi , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jani Nikula , Joonas Lahtinen , Tvrtko Ursulin Cc: Oren Weil , linux-mtd@lists.infradead.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Alexander Usyskin , Tomas Winkler , Vitaly Lubart Subject: [PATCH v2 03/10] mtd: intel-dg: implement access functions Date: Thu, 7 Nov 2024 15:13:49 +0200 Message-ID: <20241107131356.2796969-4-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241107131356.2796969-1-alexander.usyskin@intel.com> References: <20241107131356.2796969-1-alexander.usyskin@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Implement read(), erase() and write() functions. CC: Lucas De Marchi CC: Rodrigo Vivi Co-developed-by: Tomas Winkler Signed-off-by: Tomas Winkler Co-developed-by: Vitaly Lubart Signed-off-by: Vitaly Lubart Signed-off-by: Alexander Usyskin --- drivers/mtd/devices/mtd-intel-dg.c | 197 +++++++++++++++++++++++++++++ 1 file changed, 197 insertions(+) diff --git a/drivers/mtd/devices/mtd-intel-dg.c b/drivers/mtd/devices/mtd-i= ntel-dg.c index 05e333771be0..915b9750ca62 100644 --- a/drivers/mtd/devices/mtd-intel-dg.c +++ b/drivers/mtd/devices/mtd-intel-dg.c @@ -5,13 +5,16 @@ =20 #include #include +#include #include #include #include +#include #include #include #include #include +#include #include =20 struct intel_dg_nvm { @@ -91,6 +94,33 @@ static inline u32 idg_nvm_read32(struct intel_dg_nvm *nv= m, u32 address) return ioread32(base + NVM_TRIGGER_REG); } =20 +static inline u64 idg_nvm_read64(struct intel_dg_nvm *nvm, u32 address) +{ + void __iomem *base =3D nvm->base; + + iowrite32(address, base + NVM_ADDRESS_REG); + + return readq(base + NVM_TRIGGER_REG); +} + +static void idg_nvm_write32(struct intel_dg_nvm *nvm, u32 address, u32 dat= a) +{ + void __iomem *base =3D nvm->base; + + iowrite32(address, base + NVM_ADDRESS_REG); + + iowrite32(data, base + NVM_TRIGGER_REG); +} + +static void idg_nvm_write64(struct intel_dg_nvm *nvm, u32 address, u64 dat= a) +{ + void __iomem *base =3D nvm->base; + + iowrite32(address, base + NVM_ADDRESS_REG); + + writeq(data, base + NVM_TRIGGER_REG); +} + static int idg_nvm_get_access_map(struct intel_dg_nvm *nvm, u32 *access_ma= p) { u32 flmap1; @@ -147,6 +177,173 @@ static int idg_nvm_is_valid(struct intel_dg_nvm *nvm) return 0; } =20 +__maybe_unused +static unsigned int idg_nvm_get_region(const struct intel_dg_nvm *nvm, lof= f_t from) +{ + unsigned int i; + + for (i =3D 0; i < nvm->nregions; i++) { + if ((nvm->regions[i].offset + nvm->regions[i].size - 1) > from && + nvm->regions[i].offset <=3D from && + nvm->regions[i].size !=3D 0) + break; + } + + return i; +} + +static ssize_t idg_nvm_rewrite_partial(struct intel_dg_nvm *nvm, loff_t to, + loff_t offset, size_t len, const u32 *newdata) +{ + u32 data =3D idg_nvm_read32(nvm, to); + + if (idg_nvm_error(nvm)) + return -EIO; + + memcpy((u8 *)&data + offset, newdata, len); + + idg_nvm_write32(nvm, to, data); + if (idg_nvm_error(nvm)) + return -EIO; + + return len; +} + +__maybe_unused +static ssize_t idg_write(struct intel_dg_nvm *nvm, u8 region, + loff_t to, size_t len, const unsigned char *buf) +{ + size_t i; + size_t len8; + size_t len4; + size_t to4; + size_t to_shift; + size_t len_s =3D len; + ssize_t ret; + + idg_nvm_set_region_id(nvm, region); + + to4 =3D ALIGN_DOWN(to, sizeof(u32)); + to_shift =3D min(sizeof(u32) - ((size_t)to - to4), len); + if (to - to4) { + ret =3D idg_nvm_rewrite_partial(nvm, to4, to - to4, to_shift, (uint32_t = *)&buf[0]); + if (ret < 0) + return ret; + + buf +=3D to_shift; + to +=3D to_shift; + len_s -=3D to_shift; + } + + len8 =3D ALIGN_DOWN(len_s, sizeof(u64)); + for (i =3D 0; i < len8; i +=3D sizeof(u64)) { + u64 data; + + memcpy(&data, &buf[i], sizeof(u64)); + idg_nvm_write64(nvm, to + i, data); + if (idg_nvm_error(nvm)) + return -EIO; + } + + len4 =3D len_s - len8; + if (len4 >=3D sizeof(u32)) { + u32 data; + + memcpy(&data, &buf[i], sizeof(u32)); + idg_nvm_write32(nvm, to + i, data); + if (idg_nvm_error(nvm)) + return -EIO; + i +=3D sizeof(u32); + len4 -=3D sizeof(u32); + } + + if (len4 > 0) { + ret =3D idg_nvm_rewrite_partial(nvm, to + i, 0, len4, (uint32_t *)&buf[i= ]); + if (ret < 0) + return ret; + } + + return len; +} + +__maybe_unused +static ssize_t idg_read(struct intel_dg_nvm *nvm, u8 region, + loff_t from, size_t len, unsigned char *buf) +{ + size_t i; + size_t len8; + size_t len4; + size_t from4; + size_t from_shift; + size_t len_s =3D len; + + idg_nvm_set_region_id(nvm, region); + + from4 =3D ALIGN_DOWN(from, sizeof(u32)); + from_shift =3D min(sizeof(u32) - ((size_t)from - from4), len); + + if (from - from4) { + u32 data =3D idg_nvm_read32(nvm, from4); + + if (idg_nvm_error(nvm)) + return -EIO; + memcpy(&buf[0], (u8 *)&data + (from - from4), from_shift); + len_s -=3D from_shift; + buf +=3D from_shift; + from +=3D from_shift; + } + + len8 =3D ALIGN_DOWN(len_s, sizeof(u64)); + for (i =3D 0; i < len8; i +=3D sizeof(u64)) { + u64 data =3D idg_nvm_read64(nvm, from + i); + + if (idg_nvm_error(nvm)) + return -EIO; + + memcpy(&buf[i], &data, sizeof(data)); + } + + len4 =3D len_s - len8; + if (len4 >=3D sizeof(u32)) { + u32 data =3D idg_nvm_read32(nvm, from + i); + + if (idg_nvm_error(nvm)) + return -EIO; + memcpy(&buf[i], &data, sizeof(data)); + i +=3D sizeof(u32); + len4 -=3D sizeof(u32); + } + + if (len4 > 0) { + u32 data =3D idg_nvm_read32(nvm, from + i); + + if (idg_nvm_error(nvm)) + return -EIO; + memcpy(&buf[i], &data, len4); + } + + return len; +} + +__maybe_unused +static ssize_t +idg_erase(struct intel_dg_nvm *nvm, u8 region, loff_t from, u64 len, u64 *= fail_addr) +{ + u64 i; + const u32 block =3D 0x10; + void __iomem *base =3D nvm->base; + + for (i =3D 0; i < len; i +=3D SZ_4K) { + iowrite32(from + i, base + NVM_ADDRESS_REG); + iowrite32(region << 24 | block, base + NVM_ERASE_REG); + /* Since the writes are via sguint + * we cannot do back to back erases. + */ + msleep(50); + } + return len; +} + static int intel_dg_nvm_init(struct intel_dg_nvm *nvm, struct device *devi= ce) { int ret; --=20 2.43.0