From nobody Sun Nov 24 04:49:27 2024 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71C872101A3 for ; Thu, 7 Nov 2024 13:25:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730985961; cv=none; b=rYAZnE0JC0GMlNgaQpS4USvwoR3tUEUlSGOIKP3J0jJl4xkxduLrLh7s9nEtO80EUoURT0poSmGDpnpqA8Od1uD13wVfmlyXiepj8+PhPifwqjLtZVGOVX0aXG+kHZ89YDBJVu0iolC5mCgiwg6do32AHECyXAyoKkc8+4ijp6c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730985961; c=relaxed/simple; bh=BjjCwUtzu9o5OMcrwqAlmYwWM9TqS3H85tJzsX9vwQQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=pj7FTkVmh+cBEzUK7mPYdjNpq6XdoiJXjPjyxewaSMI+Q8BF5hKRoJ4/PqjeG2WOpO5KXkCU7aylQGmTKCtwrikkcrYJkEohMrvWnP1rEs52BW9k/ze8zdlwDOaj+6R1Hn5QCT2X+Sy6Nms4Zkujal/W6anjHyVXvHf380TfH3M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=DbPzYNFi; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="DbPzYNFi" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730985959; x=1762521959; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BjjCwUtzu9o5OMcrwqAlmYwWM9TqS3H85tJzsX9vwQQ=; b=DbPzYNFiykQamSMHv0EOw7yjIb2jekEz8jTbN3aTvdtWVfsmyVE/LJ15 XlWsT2zx3a+OnL005CHb6YLIHkGqK/Vsf+mZ0nB0hZPnmi2qJHzbrjbPY ToO1Z/W51w7z9xpJFYsU3JgMwhqK9VCvGdnVob9aRH3kuoWAAjlfvUNwZ 5PS0dxQZEAf4fXPT3aRx3PcD/XFVG02yWQfiKbAjDDBe/zd1WypPK31sj 7AvhlfTxhdk1SCdc5CPQhXmbUodCne6mDEbd2HV55BhCLLmNCGXDrM4ru 7Umy1rhEH3xIFSfvWifPBCBdW07CdHNr+POmCKAaD/udD7WW0I/DeZsvw w==; X-CSE-ConnectionGUID: VYD8eOmUTYuCZvfhIhfh5g== X-CSE-MsgGUID: S9X5V5pgThqOLCi2+8ibbA== X-IronPort-AV: E=McAfee;i="6700,10204,11249"; a="34750701" X-IronPort-AV: E=Sophos;i="6.12,266,1728975600"; d="scan'208";a="34750701" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2024 05:25:59 -0800 X-CSE-ConnectionGUID: EeITkLMaTxWXIZ1T8AAARw== X-CSE-MsgGUID: 1NWBQH/hQQmvT2LQVh5HPg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,266,1728975600"; d="scan'208";a="89921639" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2024 05:25:55 -0800 From: Alexander Usyskin To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Rodrigo Vivi , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jani Nikula , Joonas Lahtinen , Tvrtko Ursulin Cc: Oren Weil , linux-mtd@lists.infradead.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Alexander Usyskin , Tomas Winkler Subject: [PATCH v2 01/10] mtd: add driver for intel graphics non-volatile memory device Date: Thu, 7 Nov 2024 15:13:47 +0200 Message-ID: <20241107131356.2796969-2-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241107131356.2796969-1-alexander.usyskin@intel.com> References: <20241107131356.2796969-1-alexander.usyskin@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add auxiliary driver for intel discrete graphics non-volatile memory device. CC: Lucas De Marchi Reviewed-by: Rodrigo Vivi Co-developed-by: Tomas Winkler Signed-off-by: Tomas Winkler Signed-off-by: Alexander Usyskin Acked-by: Miquel Raynal --- MAINTAINERS | 7 ++ drivers/mtd/devices/Kconfig | 11 +++ drivers/mtd/devices/Makefile | 1 + drivers/mtd/devices/mtd-intel-dg.c | 139 +++++++++++++++++++++++++++++ include/linux/intel_dg_nvm_aux.h | 27 ++++++ 5 files changed, 185 insertions(+) create mode 100644 drivers/mtd/devices/mtd-intel-dg.c create mode 100644 include/linux/intel_dg_nvm_aux.h diff --git a/MAINTAINERS b/MAINTAINERS index 3779b3cc138e..9cbab7e7a066 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11346,6 +11346,13 @@ L: linux-kernel@vger.kernel.org S: Supported F: arch/x86/include/asm/intel-family.h =20 +INTEL DISCRETE GRAPHIC NVM MTD DRIVER +M: Alexander Usyskin +L: linux-mtd@lists.infradead.org +S: Supported +F: drivers/mtd/devices/mtd-intel-dg.c +F: include/linux/intel_dg_nvm_aux.h + INTEL DRM DISPLAY FOR XE AND I915 DRIVERS M: Jani Nikula M: Rodrigo Vivi diff --git a/drivers/mtd/devices/Kconfig b/drivers/mtd/devices/Kconfig index ff2f9e55ef28..d93edf45c0bb 100644 --- a/drivers/mtd/devices/Kconfig +++ b/drivers/mtd/devices/Kconfig @@ -183,6 +183,17 @@ config MTD_POWERNV_FLASH platforms from Linux. This device abstracts away the firmware interface for flash access. =20 +config MTD_INTEL_DG + tristate "Intel Discrete Graphic non-volatile memory driver" + depends on AUXILIARY_BUS + depends on MTD + help + This provides MTD device to access Intel Discrete Graphic + non-volatile memory. + + To compile this driver as a module, choose M here: the module + will be called mtd-intel-dg. + comment "Disk-On-Chip Device Drivers" =20 config MTD_DOCG3 diff --git a/drivers/mtd/devices/Makefile b/drivers/mtd/devices/Makefile index d11eb2b8b6f8..77c05d269034 100644 --- a/drivers/mtd/devices/Makefile +++ b/drivers/mtd/devices/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_MTD_SST25L) +=3D sst25l.o obj-$(CONFIG_MTD_BCM47XXSFLASH) +=3D bcm47xxsflash.o obj-$(CONFIG_MTD_ST_SPI_FSM) +=3D st_spi_fsm.o obj-$(CONFIG_MTD_POWERNV_FLASH) +=3D powernv_flash.o +obj-$(CONFIG_MTD_INTEL_DG) +=3D mtd-intel-dg.o =20 =20 CFLAGS_docg3.o +=3D -I$(src) diff --git a/drivers/mtd/devices/mtd-intel-dg.c b/drivers/mtd/devices/mtd-i= ntel-dg.c new file mode 100644 index 000000000000..746c963ea540 --- /dev/null +++ b/drivers/mtd/devices/mtd-intel-dg.c @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright(c) 2019-2024, Intel Corporation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +struct intel_dg_nvm { + struct kref refcnt; + void __iomem *base; + size_t size; + unsigned int nregions; + struct { + const char *name; + u8 id; + u64 offset; + u64 size; + } regions[]; +}; + +static void intel_dg_nvm_release(struct kref *kref) +{ + struct intel_dg_nvm *nvm =3D container_of(kref, struct intel_dg_nvm, refc= nt); + int i; + + pr_debug("freeing intel_dg nvm\n"); + for (i =3D 0; i < nvm->nregions; i++) + kfree(nvm->regions[i].name); + kfree(nvm); +} + +static int intel_dg_mtd_probe(struct auxiliary_device *aux_dev, + const struct auxiliary_device_id *aux_dev_id) +{ + struct intel_dg_nvm_dev *invm =3D auxiliary_dev_to_intel_dg_nvm_dev(aux_d= ev); + struct device *device; + struct intel_dg_nvm *nvm; + unsigned int nregions; + unsigned int i, n; + size_t size; + char *name; + int ret; + + device =3D &aux_dev->dev; + + /* count available regions */ + for (nregions =3D 0, i =3D 0; i < INTEL_DG_NVM_REGIONS; i++) { + if (invm->regions[i].name) + nregions++; + } + + if (!nregions) { + dev_err(device, "no regions defined\n"); + return -ENODEV; + } + + size =3D sizeof(*nvm) + sizeof(nvm->regions[0]) * nregions; + nvm =3D kzalloc(size, GFP_KERNEL); + if (!nvm) + return -ENOMEM; + + kref_init(&nvm->refcnt); + + nvm->nregions =3D nregions; + for (n =3D 0, i =3D 0; i < INTEL_DG_NVM_REGIONS; i++) { + if (!invm->regions[i].name) + continue; + + name =3D kasprintf(GFP_KERNEL, "%s.%s", + dev_name(&aux_dev->dev), invm->regions[i].name); + if (!name) + continue; + nvm->regions[n].name =3D name; + nvm->regions[n].id =3D i; + n++; + } + + nvm->base =3D devm_ioremap_resource(device, &invm->bar); + if (IS_ERR(nvm->base)) { + dev_err(device, "mmio not mapped\n"); + ret =3D PTR_ERR(nvm->base); + goto err; + } + + dev_set_drvdata(&aux_dev->dev, nvm); + + return 0; + +err: + kref_put(&nvm->refcnt, intel_dg_nvm_release); + return ret; +} + +static void intel_dg_mtd_remove(struct auxiliary_device *aux_dev) +{ + struct intel_dg_nvm *nvm =3D dev_get_drvdata(&aux_dev->dev); + + if (!nvm) + return; + + dev_set_drvdata(&aux_dev->dev, NULL); + + kref_put(&nvm->refcnt, intel_dg_nvm_release); +} + +static const struct auxiliary_device_id intel_dg_mtd_id_table[] =3D { + { + .name =3D "i915.nvm", + }, + { + .name =3D "xe.nvm", + }, + { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(auxiliary, intel_dg_mtd_id_table); + +static struct auxiliary_driver intel_dg_mtd_driver =3D { + .probe =3D intel_dg_mtd_probe, + .remove =3D intel_dg_mtd_remove, + .driver =3D { + /* auxiliary_driver_register() sets .name to be the modname */ + }, + .id_table =3D intel_dg_mtd_id_table +}; + +module_auxiliary_driver(intel_dg_mtd_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Intel Corporation"); +MODULE_DESCRIPTION("Intel DGFX MTD driver"); diff --git a/include/linux/intel_dg_nvm_aux.h b/include/linux/intel_dg_nvm_= aux.h new file mode 100644 index 000000000000..2cc4179fbde2 --- /dev/null +++ b/include/linux/intel_dg_nvm_aux.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright(c) 2019-2024, Intel Corporation. All rights reserved. + */ + +#ifndef __INTEL_DG_NVM_AUX_H__ +#define __INTEL_DG_NVM_AUX_H__ + +#include + +#define INTEL_DG_NVM_REGIONS 13 + +struct intel_dg_nvm_region { + const char *name; +}; + +struct intel_dg_nvm_dev { + struct auxiliary_device aux_dev; + bool writeable_override; + struct resource bar; + const struct intel_dg_nvm_region *regions; +}; + +#define auxiliary_dev_to_intel_dg_nvm_dev(auxiliary_dev) \ + container_of(auxiliary_dev, struct intel_dg_nvm_dev, aux_dev) + +#endif /* __INTEL_DG_NVM_AUX_H__ */ --=20 2.43.0 From nobody Sun Nov 24 04:49:27 2024 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CCEB212177 for ; Thu, 7 Nov 2024 13:26:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730985966; cv=none; b=o9rtlhOCxsBw+HOLfd5o6AtMW3Aob8h2T6okCJGuKzvIV8dVZu4s8Ao7zVYrgJCjMc3trCr4ziVCFtNCBnyKU2BO/2rHeUWZ/ww1LEq0DWa02ljbfpMfB2Oqs3oPoW+i3kU2cTCP+Z5spjsCjcJnp4mCYNePAdTa3gY+SKj37YA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730985966; c=relaxed/simple; bh=kxRm/gIWV9t8+mhBKVrkdxXSfSLyFC00LqaghTUcp1k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JXliBWxiI4BSI5hR2DxteSnjCKsADVyajMC+w5uotS8xYEy42Vqx1UR8wLNRgkpPGsnNnFyMIKQI93HrwpkHhE1+F5o4tRiZsaYHY74YR5wTBeJa40KfFrXYi/f9RPWHEEyztv4ejMp/cFTM4g3KCbt0wNHI9CHTL9N5OTlcYgQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=XidEJxke; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="XidEJxke" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730985964; x=1762521964; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kxRm/gIWV9t8+mhBKVrkdxXSfSLyFC00LqaghTUcp1k=; b=XidEJxkeDzvWPUmWDedPYbOpNa99drF/ct+3VEiFvePhsJ4+YvYQK60e ylmS+KNHxZKBekYWnOlEiVPWsNamQkPP3pvfKHZZMLf21PgiXrc5UhLls aYUGpjHzf8SmHg2vnfc6+rI17YdJbJUqCH09PBpgz2Ucqpb3nYkm3GVQt MAzbCKscqKsRH+3pidOqert/iM3r1AJLvxwM+cU4g73TgmCAall3Ai+4q rgngnycvP1szX3ZrAYV4kkin6G6IYFbLzRieKGKrfsU4v3EOJTqTH64CU idCfZYBeWTL8hJrc6iAhE1NoCOe3+Zu3I5ltDNoGFNwzmjCggM9gS9Ew6 w==; X-CSE-ConnectionGUID: 3/UH1WtJTCy+F0kU/8hB7A== X-CSE-MsgGUID: 1pmy/K+oTdaefyR3pz5wuw== X-IronPort-AV: E=McAfee;i="6700,10204,11249"; a="34750716" X-IronPort-AV: E=Sophos;i="6.12,266,1728975600"; d="scan'208";a="34750716" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2024 05:26:04 -0800 X-CSE-ConnectionGUID: fWXMmSjlQpCIBkHUqna2eA== X-CSE-MsgGUID: Fl4C77hUQB6JpkSMUvE5jQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,266,1728975600"; d="scan'208";a="89921666" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2024 05:26:00 -0800 From: Alexander Usyskin To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Rodrigo Vivi , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jani Nikula , Joonas Lahtinen , Tvrtko Ursulin Cc: Oren Weil , linux-mtd@lists.infradead.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Alexander Usyskin , Tomas Winkler Subject: [PATCH v2 02/10] mtd: intel-dg: implement region enumeration Date: Thu, 7 Nov 2024 15:13:48 +0200 Message-ID: <20241107131356.2796969-3-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241107131356.2796969-1-alexander.usyskin@intel.com> References: <20241107131356.2796969-1-alexander.usyskin@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In intel-dg, there is no access to the spi controller, the information is extracted from the descriptor region. CC: Rodrigo Vivi CC: Lucas De Marchi Co-developed-by: Tomas Winkler Signed-off-by: Tomas Winkler Signed-off-by: Alexander Usyskin Acked-by: Miquel Raynal --- drivers/mtd/devices/mtd-intel-dg.c | 199 +++++++++++++++++++++++++++++ 1 file changed, 199 insertions(+) diff --git a/drivers/mtd/devices/mtd-intel-dg.c b/drivers/mtd/devices/mtd-i= ntel-dg.c index 746c963ea540..05e333771be0 100644 --- a/drivers/mtd/devices/mtd-intel-dg.c +++ b/drivers/mtd/devices/mtd-intel-dg.c @@ -3,6 +3,8 @@ * Copyright(c) 2019-2024, Intel Corporation. All rights reserved. */ =20 +#include +#include #include #include #include @@ -22,9 +24,199 @@ struct intel_dg_nvm { u8 id; u64 offset; u64 size; + unsigned int is_readable:1; + unsigned int is_writable:1; } regions[]; }; =20 +#define NVM_TRIGGER_REG 0x00000000 +#define NVM_VALSIG_REG 0x00000010 +#define NVM_ADDRESS_REG 0x00000040 +#define NVM_REGION_ID_REG 0x00000044 +/* + * [15:0]-Erase size =3D 0x0010 4K 0x0080 32K 0x0100 64K + * [23:16]-Reserved + * [31:24]-Erase MEM RegionID + */ +#define NVM_ERASE_REG 0x00000048 +#define NVM_ACCESS_ERROR_REG 0x00000070 +#define NVM_ADDRESS_ERROR_REG 0x00000074 + +/* Flash Valid Signature */ +#define NVM_FLVALSIG 0x0FF0A55A + +#define NVM_MAP_ADDR_MASK GENMASK(7, 0) +#define NVM_MAP_ADDR_SHIFT 0x00000004 + +#define NVM_REGION_ID_DESCRIPTOR 0 +/* Flash Region Base Address */ +#define NVM_FRBA 0x40 +/* Flash Region __n - Flash Descriptor Record */ +#define NVM_FLREG(__n) (NVM_FRBA + ((__n) * 4)) +/* Flash Map 1 Register */ +#define NVM_FLMAP1_REG 0x18 +#define NVM_FLMSTR4_OFFSET 0x00C + +#define NVM_ACCESS_ERROR_PCIE_MASK 0x7 + +#define NVM_FREG_BASE_MASK GENMASK(15, 0) +#define NVM_FREG_ADDR_MASK GENMASK(31, 16) +#define NVM_FREG_ADDR_SHIFT 12 +#define NVM_FREG_MIN_REGION_SIZE 0xFFF + +static inline void idg_nvm_set_region_id(struct intel_dg_nvm *nvm, u8 regi= on) +{ + iowrite32((u32)region, nvm->base + NVM_REGION_ID_REG); +} + +static inline u32 idg_nvm_error(struct intel_dg_nvm *nvm) +{ + void __iomem *base =3D nvm->base; + + u32 reg =3D ioread32(base + NVM_ACCESS_ERROR_REG) & NVM_ACCESS_ERROR_PCIE= _MASK; + + /* reset error bits */ + if (reg) + iowrite32(reg, base + NVM_ACCESS_ERROR_REG); + + return reg; +} + +static inline u32 idg_nvm_read32(struct intel_dg_nvm *nvm, u32 address) +{ + void __iomem *base =3D nvm->base; + + iowrite32(address, base + NVM_ADDRESS_REG); + + return ioread32(base + NVM_TRIGGER_REG); +} + +static int idg_nvm_get_access_map(struct intel_dg_nvm *nvm, u32 *access_ma= p) +{ + u32 flmap1; + u32 fmba; + u32 fmstr4; + u32 fmstr4_addr; + + idg_nvm_set_region_id(nvm, NVM_REGION_ID_DESCRIPTOR); + + flmap1 =3D idg_nvm_read32(nvm, NVM_FLMAP1_REG); + if (idg_nvm_error(nvm)) + return -EIO; + /* Get Flash Master Baser Address (FMBA) */ + fmba =3D (FIELD_GET(NVM_MAP_ADDR_MASK, flmap1) << NVM_MAP_ADDR_SHIFT); + fmstr4_addr =3D fmba + NVM_FLMSTR4_OFFSET; + + fmstr4 =3D idg_nvm_read32(nvm, fmstr4_addr); + if (idg_nvm_error(nvm)) + return -EIO; + + *access_map =3D fmstr4; + return 0; +} + +static bool idg_nvm_region_readable(u32 access_map, u8 region) +{ + if (region < 12) + return access_map & BIT(region + 8); /* [19:8] */ + else + return access_map & BIT(region - 12); /* [3:0] */ +} + +static bool idg_nvm_region_writeable(u32 access_map, u8 region) +{ + if (region < 12) + return access_map & BIT(region + 20); /* [31:20] */ + else + return access_map & BIT(region - 8); /* [7:4] */ +} + +static int idg_nvm_is_valid(struct intel_dg_nvm *nvm) +{ + u32 is_valid; + + idg_nvm_set_region_id(nvm, NVM_REGION_ID_DESCRIPTOR); + + is_valid =3D idg_nvm_read32(nvm, NVM_VALSIG_REG); + if (idg_nvm_error(nvm)) + return -EIO; + + if (is_valid !=3D NVM_FLVALSIG) + return -ENODEV; + + return 0; +} + +static int intel_dg_nvm_init(struct intel_dg_nvm *nvm, struct device *devi= ce) +{ + int ret; + unsigned int i, n; + u32 access_map =3D 0; + + /* clean error register, previous errors are ignored */ + idg_nvm_error(nvm); + + ret =3D idg_nvm_is_valid(nvm); + if (ret) { + dev_err(device, "The MEM is not valid %d\n", ret); + return ret; + } + + if (idg_nvm_get_access_map(nvm, &access_map)) + return -EIO; + + for (i =3D 0, n =3D 0; i < nvm->nregions; i++) { + u32 address, base, limit, region; + u8 id =3D nvm->regions[i].id; + + address =3D NVM_FLREG(id); + region =3D idg_nvm_read32(nvm, address); + + base =3D FIELD_GET(NVM_FREG_BASE_MASK, region) << NVM_FREG_ADDR_SHIFT; + limit =3D (FIELD_GET(NVM_FREG_ADDR_MASK, region) << NVM_FREG_ADDR_SHIFT)= | + NVM_FREG_MIN_REGION_SIZE; + + dev_dbg(device, "[%d] %s: region: 0x%08X base: 0x%08x limit: 0x%08x\n", + id, nvm->regions[i].name, region, base, limit); + + if (base >=3D limit || (i > 0 && limit =3D=3D 0)) { + dev_dbg(device, "[%d] %s: disabled\n", + id, nvm->regions[i].name); + nvm->regions[i].is_readable =3D 0; + continue; + } + + if (nvm->size < limit) + nvm->size =3D limit; + + nvm->regions[i].offset =3D base; + nvm->regions[i].size =3D limit - base + 1; + /* No write access to descriptor; mask it out*/ + nvm->regions[i].is_writable =3D idg_nvm_region_writeable(access_map, id); + + nvm->regions[i].is_readable =3D idg_nvm_region_readable(access_map, id); + dev_dbg(device, "Registered, %s id=3D%d offset=3D%lld size=3D%lld rd=3D%= d wr=3D%d\n", + nvm->regions[i].name, + nvm->regions[i].id, + nvm->regions[i].offset, + nvm->regions[i].size, + nvm->regions[i].is_readable, + nvm->regions[i].is_writable); + + if (nvm->regions[i].is_readable) + n++; + } + + dev_dbg(device, "Registered %d regions\n", n); + + /* Need to add 1 to the amount of memory + * so it is reported as an even block + */ + nvm->size +=3D 1; + + return n; +} + static void intel_dg_nvm_release(struct kref *kref) { struct intel_dg_nvm *nvm =3D container_of(kref, struct intel_dg_nvm, refc= nt); @@ -89,6 +281,13 @@ static int intel_dg_mtd_probe(struct auxiliary_device *= aux_dev, goto err; } =20 + ret =3D intel_dg_nvm_init(nvm, device); + if (ret < 0) { + dev_err(device, "cannot initialize nvm\n"); + ret =3D -ENODEV; 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charset="utf-8" Implement read(), erase() and write() functions. CC: Lucas De Marchi CC: Rodrigo Vivi Co-developed-by: Tomas Winkler Signed-off-by: Tomas Winkler Co-developed-by: Vitaly Lubart Signed-off-by: Vitaly Lubart Signed-off-by: Alexander Usyskin Acked-by: Miquel Raynal --- drivers/mtd/devices/mtd-intel-dg.c | 197 +++++++++++++++++++++++++++++ 1 file changed, 197 insertions(+) diff --git a/drivers/mtd/devices/mtd-intel-dg.c b/drivers/mtd/devices/mtd-i= ntel-dg.c index 05e333771be0..915b9750ca62 100644 --- a/drivers/mtd/devices/mtd-intel-dg.c +++ b/drivers/mtd/devices/mtd-intel-dg.c @@ -5,13 +5,16 @@ =20 #include #include +#include #include #include #include +#include #include #include #include #include +#include #include =20 struct intel_dg_nvm { @@ -91,6 +94,33 @@ static inline u32 idg_nvm_read32(struct intel_dg_nvm *nv= m, u32 address) return ioread32(base + NVM_TRIGGER_REG); } =20 +static inline u64 idg_nvm_read64(struct intel_dg_nvm *nvm, u32 address) +{ + void __iomem *base =3D nvm->base; + + iowrite32(address, base + NVM_ADDRESS_REG); + + return readq(base + NVM_TRIGGER_REG); +} + +static void idg_nvm_write32(struct intel_dg_nvm *nvm, u32 address, u32 dat= a) +{ + void __iomem *base =3D nvm->base; + + iowrite32(address, base + NVM_ADDRESS_REG); + + iowrite32(data, base + NVM_TRIGGER_REG); +} + +static void idg_nvm_write64(struct intel_dg_nvm *nvm, u32 address, u64 dat= a) +{ + void __iomem *base =3D nvm->base; + + iowrite32(address, base + NVM_ADDRESS_REG); + + writeq(data, base + NVM_TRIGGER_REG); +} + static int idg_nvm_get_access_map(struct intel_dg_nvm *nvm, u32 *access_ma= p) { u32 flmap1; @@ -147,6 +177,173 @@ static int idg_nvm_is_valid(struct intel_dg_nvm *nvm) return 0; } =20 +__maybe_unused +static unsigned int idg_nvm_get_region(const struct intel_dg_nvm *nvm, lof= f_t from) +{ + unsigned int i; + + for (i =3D 0; i < nvm->nregions; i++) { + if ((nvm->regions[i].offset + nvm->regions[i].size - 1) > from && + nvm->regions[i].offset <=3D from && + nvm->regions[i].size !=3D 0) + break; + } + + return i; +} + +static ssize_t idg_nvm_rewrite_partial(struct intel_dg_nvm *nvm, loff_t to, + loff_t offset, size_t len, const u32 *newdata) +{ + u32 data =3D idg_nvm_read32(nvm, to); + + if (idg_nvm_error(nvm)) + return -EIO; + + memcpy((u8 *)&data + offset, newdata, len); + + idg_nvm_write32(nvm, to, data); + if (idg_nvm_error(nvm)) + return -EIO; + + return len; +} + +__maybe_unused +static ssize_t idg_write(struct intel_dg_nvm *nvm, u8 region, + loff_t to, size_t len, const unsigned char *buf) +{ + size_t i; + size_t len8; + size_t len4; + size_t to4; + size_t to_shift; + size_t len_s =3D len; + ssize_t ret; + + idg_nvm_set_region_id(nvm, region); + + to4 =3D ALIGN_DOWN(to, sizeof(u32)); + to_shift =3D min(sizeof(u32) - ((size_t)to - to4), len); + if (to - to4) { + ret =3D idg_nvm_rewrite_partial(nvm, to4, to - to4, to_shift, (uint32_t = *)&buf[0]); + if (ret < 0) + return ret; + + buf +=3D to_shift; + to +=3D to_shift; + len_s -=3D to_shift; + } + + len8 =3D ALIGN_DOWN(len_s, sizeof(u64)); + for (i =3D 0; i < len8; i +=3D sizeof(u64)) { + u64 data; + + memcpy(&data, &buf[i], sizeof(u64)); + idg_nvm_write64(nvm, to + i, data); + if (idg_nvm_error(nvm)) + return -EIO; + } + + len4 =3D len_s - len8; + if (len4 >=3D sizeof(u32)) { + u32 data; + + memcpy(&data, &buf[i], sizeof(u32)); + idg_nvm_write32(nvm, to + i, data); + if (idg_nvm_error(nvm)) + return -EIO; + i +=3D sizeof(u32); + len4 -=3D sizeof(u32); + } + + if (len4 > 0) { + ret =3D idg_nvm_rewrite_partial(nvm, to + i, 0, len4, (uint32_t *)&buf[i= ]); + if (ret < 0) + return ret; + } + + return len; +} + +__maybe_unused +static ssize_t idg_read(struct intel_dg_nvm *nvm, u8 region, + loff_t from, size_t len, unsigned char *buf) +{ + size_t i; + size_t len8; + size_t len4; + size_t from4; + size_t from_shift; + size_t len_s =3D len; + + idg_nvm_set_region_id(nvm, region); + + from4 =3D ALIGN_DOWN(from, sizeof(u32)); + from_shift =3D min(sizeof(u32) - ((size_t)from - from4), len); + + if (from - from4) { + u32 data =3D idg_nvm_read32(nvm, from4); + + if (idg_nvm_error(nvm)) + return -EIO; + memcpy(&buf[0], (u8 *)&data + (from - from4), from_shift); + len_s -=3D from_shift; + buf +=3D from_shift; + from +=3D from_shift; + } + + len8 =3D ALIGN_DOWN(len_s, sizeof(u64)); + for (i =3D 0; i < len8; i +=3D sizeof(u64)) { + u64 data =3D idg_nvm_read64(nvm, from + i); + + if (idg_nvm_error(nvm)) + return -EIO; + + memcpy(&buf[i], &data, sizeof(data)); + } + + len4 =3D len_s - len8; + if (len4 >=3D sizeof(u32)) { + u32 data =3D idg_nvm_read32(nvm, from + i); + + if (idg_nvm_error(nvm)) + return -EIO; + memcpy(&buf[i], &data, sizeof(data)); + i +=3D sizeof(u32); + len4 -=3D sizeof(u32); + } + + if (len4 > 0) { + u32 data =3D idg_nvm_read32(nvm, from + i); + + if (idg_nvm_error(nvm)) + return -EIO; + memcpy(&buf[i], &data, len4); + } + + return len; +} + +__maybe_unused +static ssize_t +idg_erase(struct intel_dg_nvm *nvm, u8 region, loff_t from, u64 len, u64 *= fail_addr) +{ + u64 i; + const u32 block =3D 0x10; + void __iomem *base =3D nvm->base; + + for (i =3D 0; i < len; i +=3D SZ_4K) { + iowrite32(from + i, base + NVM_ADDRESS_REG); + iowrite32(region << 24 | block, base + NVM_ERASE_REG); + /* Since the writes are via sguint + * we cannot do back to back erases. + */ + msleep(50); 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07 Nov 2024 05:26:10 -0800 From: Alexander Usyskin To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Rodrigo Vivi , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jani Nikula , Joonas Lahtinen , Tvrtko Ursulin Cc: Oren Weil , linux-mtd@lists.infradead.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Alexander Usyskin , Tomas Winkler , Vitaly Lubart Subject: [PATCH v2 04/10] mtd: intel-dg: register with mtd Date: Thu, 7 Nov 2024 15:13:50 +0200 Message-ID: <20241107131356.2796969-5-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241107131356.2796969-1-alexander.usyskin@intel.com> References: <20241107131356.2796969-1-alexander.usyskin@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Register the on-die nvm device with the mtd subsystem. Refcount nvm object on _get and _put mtd callbacks. For erase operation address and size should be 4K aligned. For write operation address and size has to be 4bytes aligned. CC: Rodrigo Vivi CC: Lucas De Marchi Co-developed-by: Tomas Winkler Signed-off-by: Tomas Winkler Co-developed-by: Vitaly Lubart Signed-off-by: Vitaly Lubart Signed-off-by: Alexander Usyskin Acked-by: Miquel Raynal --- drivers/mtd/devices/mtd-intel-dg.c | 230 ++++++++++++++++++++++++++++- 1 file changed, 226 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/devices/mtd-intel-dg.c b/drivers/mtd/devices/mtd-i= ntel-dg.c index 915b9750ca62..76ef7198fff8 100644 --- a/drivers/mtd/devices/mtd-intel-dg.c +++ b/drivers/mtd/devices/mtd-intel-dg.c @@ -5,6 +5,7 @@ =20 #include #include +#include #include #include #include @@ -12,6 +13,8 @@ #include #include #include +#include +#include #include #include #include @@ -19,6 +22,8 @@ =20 struct intel_dg_nvm { struct kref refcnt; + struct mtd_info mtd; + struct mutex lock; /* region access lock */ void __iomem *base; size_t size; unsigned int nregions; @@ -177,7 +182,6 @@ static int idg_nvm_is_valid(struct intel_dg_nvm *nvm) return 0; } =20 -__maybe_unused static unsigned int idg_nvm_get_region(const struct intel_dg_nvm *nvm, lof= f_t from) { unsigned int i; @@ -209,7 +213,6 @@ static ssize_t idg_nvm_rewrite_partial(struct intel_dg_= nvm *nvm, loff_t to, return len; } =20 -__maybe_unused static ssize_t idg_write(struct intel_dg_nvm *nvm, u8 region, loff_t to, size_t len, const unsigned char *buf) { @@ -266,7 +269,6 @@ static ssize_t idg_write(struct intel_dg_nvm *nvm, u8 r= egion, return len; } =20 -__maybe_unused static ssize_t idg_read(struct intel_dg_nvm *nvm, u8 region, loff_t from, size_t len, unsigned char *buf) { @@ -325,7 +327,6 @@ static ssize_t idg_read(struct intel_dg_nvm *nvm, u8 re= gion, return len; } =20 -__maybe_unused static ssize_t idg_erase(struct intel_dg_nvm *nvm, u8 region, loff_t from, u64 len, u64 *= fail_addr) { @@ -414,6 +415,147 @@ static int intel_dg_nvm_init(struct intel_dg_nvm *nvm= , struct device *device) return n; } =20 +static int intel_dg_mtd_erase(struct mtd_info *mtd, struct erase_info *inf= o) +{ + struct intel_dg_nvm *nvm =3D mtd->priv; + unsigned int idx; + u8 region; + u64 addr; + ssize_t bytes; + loff_t from; + size_t len; + size_t total_len; + + if (WARN_ON(!nvm)) + return -EINVAL; + + if (!IS_ALIGNED(info->addr, SZ_4K) || !IS_ALIGNED(info->len, SZ_4K)) { + dev_err(&mtd->dev, "unaligned erase %llx %llx\n", + info->addr, info->len); + info->fail_addr =3D MTD_FAIL_ADDR_UNKNOWN; + return -EINVAL; + } + + total_len =3D info->len; + addr =3D info->addr; + + guard(mutex)(&nvm->lock); + + while (total_len > 0) { + if (!IS_ALIGNED(addr, SZ_4K) || !IS_ALIGNED(total_len, SZ_4K)) { + dev_err(&mtd->dev, "unaligned erase %llx %zx\n", addr, total_len); + info->fail_addr =3D addr; + return -ERANGE; + } + + idx =3D idg_nvm_get_region(nvm, addr); + if (idx >=3D nvm->nregions) { + dev_err(&mtd->dev, "out of range"); + info->fail_addr =3D MTD_FAIL_ADDR_UNKNOWN; + return -ERANGE; + } + + from =3D addr - nvm->regions[idx].offset; + region =3D nvm->regions[idx].id; + len =3D total_len; + if (len > nvm->regions[idx].size - from) + len =3D nvm->regions[idx].size - from; + + dev_dbg(&mtd->dev, "erasing region[%d] %s from %llx len %zx\n", + region, nvm->regions[idx].name, from, len); + + bytes =3D idg_erase(nvm, region, from, len, &info->fail_addr); + if (bytes < 0) { + dev_dbg(&mtd->dev, "erase failed with %zd\n", bytes); + info->fail_addr +=3D nvm->regions[idx].offset; + return bytes; + } + + addr +=3D len; + total_len -=3D len; + } + + return 0; +} + +static int intel_dg_mtd_read(struct mtd_info *mtd, loff_t from, size_t len, + size_t *retlen, u_char *buf) +{ + struct intel_dg_nvm *nvm =3D mtd->priv; + ssize_t ret; + unsigned int idx; + u8 region; + + if (WARN_ON(!nvm)) + return -EINVAL; + + idx =3D idg_nvm_get_region(nvm, from); + + dev_dbg(&mtd->dev, "reading region[%d] %s from %lld len %zd\n", + nvm->regions[idx].id, nvm->regions[idx].name, from, len); + + if (idx >=3D nvm->nregions) { + dev_err(&mtd->dev, "out of ragnge"); + return -ERANGE; + } + + from -=3D nvm->regions[idx].offset; + region =3D nvm->regions[idx].id; + if (len > nvm->regions[idx].size - from) + len =3D nvm->regions[idx].size - from; + + guard(mutex)(&nvm->lock); + + ret =3D idg_read(nvm, region, from, len, buf); + if (ret < 0) { + dev_dbg(&mtd->dev, "read failed with %zd\n", ret); + return ret; + } + + *retlen =3D ret; + + return 0; +} + +static int intel_dg_mtd_write(struct mtd_info *mtd, loff_t to, size_t len, + size_t *retlen, const u_char *buf) +{ + struct intel_dg_nvm *nvm =3D mtd->priv; + ssize_t ret; + unsigned int idx; + u8 region; + + if (WARN_ON(!nvm)) + return -EINVAL; + + idx =3D idg_nvm_get_region(nvm, to); + + dev_dbg(&mtd->dev, "writing region[%d] %s to %lld len %zd\n", + nvm->regions[idx].id, nvm->regions[idx].name, to, len); + + if (idx >=3D nvm->nregions) { + dev_err(&mtd->dev, "out of range"); + return -ERANGE; + } + + to -=3D nvm->regions[idx].offset; + region =3D nvm->regions[idx].id; + if (len > nvm->regions[idx].size - to) + len =3D nvm->regions[idx].size - to; + + guard(mutex)(&nvm->lock); + + ret =3D idg_write(nvm, region, to, len, buf); + if (ret < 0) { + dev_dbg(&mtd->dev, "write failed with %zd\n", ret); + return ret; + } + + *retlen =3D ret; + + return 0; +} + static void intel_dg_nvm_release(struct kref *kref) { struct intel_dg_nvm *nvm =3D container_of(kref, struct intel_dg_nvm, refc= nt); @@ -422,9 +564,80 @@ static void intel_dg_nvm_release(struct kref *kref) pr_debug("freeing intel_dg nvm\n"); for (i =3D 0; i < nvm->nregions; i++) kfree(nvm->regions[i].name); + mutex_destroy(&nvm->lock); kfree(nvm); } =20 +static int intel_dg_mtd_get_device(struct mtd_info *mtd) +{ + struct mtd_info *master =3D mtd_get_master(mtd); + struct intel_dg_nvm *nvm =3D master->priv; + + if (WARN_ON(!nvm)) + return -EINVAL; + pr_debug("get mtd %s %d\n", mtd->name, kref_read(&nvm->refcnt)); + kref_get(&nvm->refcnt); + + return 0; +} + +static void intel_dg_mtd_put_device(struct mtd_info *mtd) +{ + struct mtd_info *master =3D mtd_get_master(mtd); + struct intel_dg_nvm *nvm =3D master->priv; + + if (WARN_ON(!nvm)) + return; + pr_debug("put mtd %s %d\n", mtd->name, kref_read(&nvm->refcnt)); + kref_put(&nvm->refcnt, intel_dg_nvm_release); +} + +static int intel_dg_nvm_init_mtd(struct intel_dg_nvm *nvm, struct device *= device, + unsigned int nparts, bool writeable_override) +{ + unsigned int i; + unsigned int n; + struct mtd_partition *parts =3D NULL; + int ret; + + dev_dbg(device, "registering with mtd\n"); + + nvm->mtd.owner =3D THIS_MODULE; + nvm->mtd.dev.parent =3D device; + nvm->mtd.flags =3D MTD_CAP_NORFLASH | MTD_WRITEABLE; + nvm->mtd.type =3D MTD_DATAFLASH; + nvm->mtd.priv =3D nvm; + nvm->mtd._write =3D intel_dg_mtd_write; + nvm->mtd._read =3D intel_dg_mtd_read; + nvm->mtd._erase =3D intel_dg_mtd_erase; + nvm->mtd._get_device =3D intel_dg_mtd_get_device; + nvm->mtd._put_device =3D intel_dg_mtd_put_device; + nvm->mtd.writesize =3D SZ_1; /* 1 byte granularity */ + nvm->mtd.erasesize =3D SZ_4K; /* 4K bytes granularity */ + nvm->mtd.size =3D nvm->size; + + parts =3D kcalloc(nvm->nregions, sizeof(*parts), GFP_KERNEL); + if (!parts) + return -ENOMEM; + + for (i =3D 0, n =3D 0; i < nvm->nregions && n < nparts; i++) { + if (!nvm->regions[i].is_readable) + continue; + parts[n].name =3D nvm->regions[i].name; + parts[n].offset =3D nvm->regions[i].offset; + parts[n].size =3D nvm->regions[i].size; + if (!nvm->regions[i].is_writable && !writeable_override) + parts[n].mask_flags =3D MTD_WRITEABLE; + n++; + } + + ret =3D mtd_device_register(&nvm->mtd, parts, n); + + kfree(parts); + + return ret; +} + static int intel_dg_mtd_probe(struct auxiliary_device *aux_dev, const struct auxiliary_device_id *aux_dev_id) { @@ -456,6 +669,7 @@ static int intel_dg_mtd_probe(struct auxiliary_device *= aux_dev, return -ENOMEM; =20 kref_init(&nvm->refcnt); + mutex_init(&nvm->lock); =20 nvm->nregions =3D nregions; for (n =3D 0, i =3D 0; i < INTEL_DG_NVM_REGIONS; i++) { @@ -485,6 +699,12 @@ static int intel_dg_mtd_probe(struct auxiliary_device = *aux_dev, goto err; } =20 + ret =3D intel_dg_nvm_init_mtd(nvm, device, ret, invm->writeable_override); + if (ret) { + dev_err(device, "failed init mtd %d\n", ret); + goto err; + } + dev_set_drvdata(&aux_dev->dev, nvm); =20 return 0; @@ -501,6 +721,8 @@ static void intel_dg_mtd_remove(struct auxiliary_device= *aux_dev) if (!nvm) return; =20 + mtd_device_unregister(&nvm->mtd); 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07 Nov 2024 05:26:16 -0800 From: Alexander Usyskin To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Rodrigo Vivi , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jani Nikula , Joonas Lahtinen , Tvrtko Ursulin Cc: Oren Weil , linux-mtd@lists.infradead.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Alexander Usyskin Subject: [PATCH v2 05/10] mtd: intel-dg: align 64bit read and write Date: Thu, 7 Nov 2024 15:13:51 +0200 Message-ID: <20241107131356.2796969-6-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241107131356.2796969-1-alexander.usyskin@intel.com> References: <20241107131356.2796969-1-alexander.usyskin@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" GSC NVM controller HW errors on quad access overlapping 1K border. Align 64bit read and write to avoid readq/writeq over 1K border. Signed-off-by: Alexander Usyskin Acked-by: Miquel Raynal --- drivers/mtd/devices/mtd-intel-dg.c | 35 ++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/mtd/devices/mtd-intel-dg.c b/drivers/mtd/devices/mtd-i= ntel-dg.c index 76ef7198fff8..230bf444b7fe 100644 --- a/drivers/mtd/devices/mtd-intel-dg.c +++ b/drivers/mtd/devices/mtd-intel-dg.c @@ -238,6 +238,24 @@ static ssize_t idg_write(struct intel_dg_nvm *nvm, u8 = region, len_s -=3D to_shift; } =20 + if (!IS_ALIGNED(to, sizeof(u64)) && + ((to ^ (to + len_s)) & GENMASK(31, 10))) { + /* + * Workaround reads/writes across 1k-aligned addresses + * (start u32 before 1k, end u32 after) + * as this fails on hardware. + */ + u32 data; + + memcpy(&data, &buf[0], sizeof(u32)); + idg_nvm_write32(nvm, to, data); + if (idg_nvm_error(nvm)) + return -EIO; + buf +=3D sizeof(u32); + to +=3D sizeof(u32); + len_s -=3D sizeof(u32); + } + len8 =3D ALIGN_DOWN(len_s, sizeof(u64)); for (i =3D 0; i < len8; i +=3D sizeof(u64)) { u64 data; @@ -295,6 +313,23 @@ static ssize_t idg_read(struct intel_dg_nvm *nvm, u8 r= egion, from +=3D from_shift; } =20 + if (!IS_ALIGNED(from, sizeof(u64)) && + ((from ^ (from + len_s)) & GENMASK(31, 10))) { + /* + * Workaround reads/writes across 1k-aligned addresses + * (start u32 before 1k, end u32 after) + * as this fails on hardware. + */ + u32 data =3D idg_nvm_read32(nvm, from); + + if (idg_nvm_error(nvm)) + return -EIO; + memcpy(&buf[0], &data, sizeof(data)); + len_s -=3D sizeof(u32); + buf +=3D sizeof(u32); + from +=3D sizeof(u32); + } + len8 =3D ALIGN_DOWN(len_s, sizeof(u64)); for (i =3D 0; i < len8; i +=3D sizeof(u64)) { u64 data =3D idg_nvm_read64(nvm, from + i); --=20 2.43.0 From nobody Sun Nov 24 04:49:27 2024 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB3C2212179 for ; Thu, 7 Nov 2024 13:26:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a="34750777" X-IronPort-AV: E=Sophos;i="6.12,266,1728975600"; d="scan'208";a="34750777" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2024 05:26:24 -0800 X-CSE-ConnectionGUID: jpjw2bkBS4WMrzeLNJNyPQ== X-CSE-MsgGUID: SlhVDED6SAiEsi2QFi4Img== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,266,1728975600"; d="scan'208";a="89921734" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2024 05:26:21 -0800 From: Alexander Usyskin To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Rodrigo Vivi , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jani Nikula , Joonas Lahtinen , Tvrtko Ursulin Cc: Oren Weil , linux-mtd@lists.infradead.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Alexander Usyskin Subject: [PATCH v2 06/10] mtd: intel-dg: wake card on operations Date: Thu, 7 Nov 2024 15:13:52 +0200 Message-ID: <20241107131356.2796969-7-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241107131356.2796969-1-alexander.usyskin@intel.com> References: <20241107131356.2796969-1-alexander.usyskin@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable runtime PM in mtd driver to notify graphics driver that whole card should be kept awake while nvm operations are performed through this driver. CC: Lucas De Marchi Signed-off-by: Alexander Usyskin Acked-by: Miquel Raynal --- drivers/mtd/devices/mtd-intel-dg.c | 73 +++++++++++++++++++++++++----- 1 file changed, 61 insertions(+), 12 deletions(-) diff --git a/drivers/mtd/devices/mtd-intel-dg.c b/drivers/mtd/devices/mtd-i= ntel-dg.c index 230bf444b7fe..05a2f87b722a 100644 --- a/drivers/mtd/devices/mtd-intel-dg.c +++ b/drivers/mtd/devices/mtd-intel-dg.c @@ -15,11 +15,14 @@ #include #include #include +#include #include #include #include #include =20 +#define INTEL_DG_NVM_RPM_TIMEOUT 500 + struct intel_dg_nvm { struct kref refcnt; struct mtd_info mtd; @@ -460,6 +463,7 @@ static int intel_dg_mtd_erase(struct mtd_info *mtd, str= uct erase_info *info) loff_t from; size_t len; size_t total_len; + int ret =3D 0; =20 if (WARN_ON(!nvm)) return -EINVAL; @@ -474,20 +478,28 @@ static int intel_dg_mtd_erase(struct mtd_info *mtd, s= truct erase_info *info) total_len =3D info->len; addr =3D info->addr; =20 + ret =3D pm_runtime_resume_and_get(mtd->dev.parent); + if (ret < 0) { + dev_err(&mtd->dev, "rpm: get failed %d\n", ret); + return ret; + } + guard(mutex)(&nvm->lock); =20 while (total_len > 0) { if (!IS_ALIGNED(addr, SZ_4K) || !IS_ALIGNED(total_len, SZ_4K)) { dev_err(&mtd->dev, "unaligned erase %llx %zx\n", addr, total_len); info->fail_addr =3D addr; - return -ERANGE; + ret =3D -ERANGE; + goto out; } =20 idx =3D idg_nvm_get_region(nvm, addr); if (idx >=3D nvm->nregions) { dev_err(&mtd->dev, "out of range"); info->fail_addr =3D MTD_FAIL_ADDR_UNKNOWN; - return -ERANGE; + ret =3D -ERANGE; + goto out; } =20 from =3D addr - nvm->regions[idx].offset; @@ -503,14 +515,18 @@ static int intel_dg_mtd_erase(struct mtd_info *mtd, s= truct erase_info *info) if (bytes < 0) { dev_dbg(&mtd->dev, "erase failed with %zd\n", bytes); info->fail_addr +=3D nvm->regions[idx].offset; - return bytes; + ret =3D bytes; + goto out; } =20 addr +=3D len; total_len -=3D len; } =20 - return 0; +out: + pm_runtime_mark_last_busy(mtd->dev.parent); + pm_runtime_put_autosuspend(mtd->dev.parent); + return ret; } =20 static int intel_dg_mtd_read(struct mtd_info *mtd, loff_t from, size_t len, @@ -539,17 +555,25 @@ static int intel_dg_mtd_read(struct mtd_info *mtd, lo= ff_t from, size_t len, if (len > nvm->regions[idx].size - from) len =3D nvm->regions[idx].size - from; =20 + ret =3D pm_runtime_resume_and_get(mtd->dev.parent); + if (ret < 0) { + dev_err(&mtd->dev, "rpm: get failed %zd\n", ret); + return ret; + } + guard(mutex)(&nvm->lock); =20 ret =3D idg_read(nvm, region, from, len, buf); if (ret < 0) { dev_dbg(&mtd->dev, "read failed with %zd\n", ret); - return ret; + } else { + *retlen =3D ret; + ret =3D 0; } =20 - *retlen =3D ret; - - return 0; + pm_runtime_mark_last_busy(mtd->dev.parent); + pm_runtime_put_autosuspend(mtd->dev.parent); + return ret; } =20 static int intel_dg_mtd_write(struct mtd_info *mtd, loff_t to, size_t len, @@ -578,17 +602,25 @@ static int intel_dg_mtd_write(struct mtd_info *mtd, l= off_t to, size_t len, if (len > nvm->regions[idx].size - to) len =3D nvm->regions[idx].size - to; =20 + ret =3D pm_runtime_resume_and_get(mtd->dev.parent); + if (ret < 0) { + dev_err(&mtd->dev, "rpm: get failed %zd\n", ret); + return ret; + } + guard(mutex)(&nvm->lock); =20 ret =3D idg_write(nvm, region, to, len, buf); if (ret < 0) { dev_dbg(&mtd->dev, "write failed with %zd\n", ret); - return ret; + } else { + *retlen =3D ret; + ret =3D 0; } =20 - *retlen =3D ret; - - return 0; + pm_runtime_mark_last_busy(mtd->dev.parent); + pm_runtime_put_autosuspend(mtd->dev.parent); + return ret; } =20 static void intel_dg_nvm_release(struct kref *kref) @@ -720,6 +752,17 @@ static int intel_dg_mtd_probe(struct auxiliary_device = *aux_dev, n++; } =20 + pm_runtime_enable(device); + + pm_runtime_set_autosuspend_delay(device, INTEL_DG_NVM_RPM_TIMEOUT); + pm_runtime_use_autosuspend(device); + + ret =3D pm_runtime_resume_and_get(device); + if (ret < 0) { + dev_err(device, "rpm: get failed %d\n", ret); + goto err_norpm; + } + nvm->base =3D devm_ioremap_resource(device, &invm->bar); if (IS_ERR(nvm->base)) { dev_err(device, "mmio not mapped\n"); @@ -742,9 +785,13 @@ static int intel_dg_mtd_probe(struct auxiliary_device = *aux_dev, =20 dev_set_drvdata(&aux_dev->dev, nvm); =20 + pm_runtime_put(device); return 0; =20 err: + pm_runtime_put(device); +err_norpm: + pm_runtime_disable(device); kref_put(&nvm->refcnt, intel_dg_nvm_release); return ret; } @@ -756,6 +803,8 @@ static void intel_dg_mtd_remove(struct auxiliary_device= *aux_dev) if (!nvm) return; =20 + pm_runtime_disable(&aux_dev->dev); + mtd_device_unregister(&nvm->mtd); =20 dev_set_drvdata(&aux_dev->dev, NULL); --=20 2.43.0 From nobody Sun Nov 24 04:49:27 2024 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 89B22212D33 for ; Thu, 7 Nov 2024 13:26:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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07 Nov 2024 05:26:30 -0800 X-CSE-ConnectionGUID: OZ5bX8X7Q7+hBCppOkgDFQ== X-CSE-MsgGUID: i3CCZGuzTju2Khqjv0QZAw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,266,1728975600"; d="scan'208";a="89921748" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2024 05:26:26 -0800 From: Alexander Usyskin To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Rodrigo Vivi , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jani Nikula , Joonas Lahtinen , Tvrtko Ursulin Cc: Oren Weil , linux-mtd@lists.infradead.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Alexander Usyskin , Tomas Winkler Subject: [PATCH v2 07/10] drm/i915/nvm: add nvm device for discrete graphics Date: Thu, 7 Nov 2024 15:13:53 +0200 Message-ID: <20241107131356.2796969-8-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241107131356.2796969-1-alexander.usyskin@intel.com> References: <20241107131356.2796969-1-alexander.usyskin@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable access to internal non-volatile memory on DGFX devices via a child device. The nvm child device is exposed via auxiliary bus. CC: Rodrigo Vivi CC: Lucas De Marchi Co-developed-by: Tomas Winkler Signed-off-by: Tomas Winkler Signed-off-by: Alexander Usyskin Acked-by: Miquel Raynal Reviewed-by: Rodrigo Vivi --- drivers/gpu/drm/i915/Makefile | 4 ++ drivers/gpu/drm/i915/i915_driver.c | 6 ++ drivers/gpu/drm/i915/i915_drv.h | 3 + drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_nvm.c | 94 ++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_nvm.h | 15 +++++ 6 files changed, 123 insertions(+) create mode 100644 drivers/gpu/drm/i915/intel_nvm.c create mode 100644 drivers/gpu/drm/i915/intel_nvm.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index e033bcaef4f3..09f509843b4e 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -212,6 +212,10 @@ i915-y +=3D \ i915-y +=3D \ gt/intel_gsc.o =20 +# graphics nvm device (DGFX) support +i915-y +=3D \ + intel_nvm.o + # graphics hardware monitoring (HWMON) support i915-$(CONFIG_HWMON) +=3D \ i915_hwmon.o diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915= _driver.c index 365329ff8a07..7f7dffdc8852 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -80,6 +80,8 @@ #include "soc/intel_dram.h" #include "soc/intel_gmch.h" =20 +#include "intel_nvm.h" + #include "i915_debugfs.h" #include "i915_driver.h" #include "i915_drm_client.h" @@ -620,6 +622,8 @@ static void i915_driver_register(struct drm_i915_privat= e *dev_priv) /* Depends on sysfs having been initialized */ i915_perf_register(dev_priv); =20 + intel_nvm_init(dev_priv); + for_each_gt(gt, dev_priv, i) intel_gt_driver_register(gt); =20 @@ -663,6 +667,8 @@ static void i915_driver_unregister(struct drm_i915_priv= ate *dev_priv) =20 i915_hwmon_unregister(dev_priv); =20 + intel_nvm_fini(dev_priv); + i915_perf_unregister(dev_priv); i915_pmu_unregister(dev_priv); =20 diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_dr= v.h index a66e5bb078cf..faaad8b16ab9 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -67,6 +67,7 @@ struct drm_i915_clock_gating_funcs; struct vlv_s0ix_state; struct intel_pxp; +struct intel_dg_nvm_dev; =20 #define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0) =20 @@ -316,6 +317,8 @@ struct drm_i915_private { =20 struct i915_perf perf; =20 + struct intel_dg_nvm_dev *nvm; + struct i915_hwmon *hwmon; =20 struct intel_gt *gt[I915_MAX_GT]; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_re= g.h index 818142f5a10c..eddafd5d7628 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -323,6 +323,7 @@ #define DG2_GSC_HECI2_BASE 0x00374000 #define MTL_GSC_HECI1_BASE 0x00116000 #define MTL_GSC_HECI2_BASE 0x00117000 +#define GEN12_GUNIT_NVM_BASE 0x00102040 =20 #define HECI_H_CSR(base) _MMIO((base) + 0x4) #define HECI_H_CSR_IE REG_BIT(0) diff --git a/drivers/gpu/drm/i915/intel_nvm.c b/drivers/gpu/drm/i915/intel_= nvm.c new file mode 100644 index 000000000000..214c4d47a9cd --- /dev/null +++ b/drivers/gpu/drm/i915/intel_nvm.c @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright(c) 2019-2024, Intel Corporation. All rights reserved. + */ + +#include +#include +#include "i915_reg.h" +#include "i915_drv.h" +#include "intel_nvm.h" + +#define GEN12_GUNIT_NVM_SIZE 0x80 + +static const struct intel_dg_nvm_region regions[INTEL_DG_NVM_REGIONS] =3D { + [0] =3D { .name =3D "DESCRIPTOR", }, + [2] =3D { .name =3D "GSC", }, + [11] =3D { .name =3D "OptionROM", }, + [12] =3D { .name =3D "DAM", }, +}; + +static void i915_nvm_release_dev(struct device *dev) +{ +} + +void intel_nvm_init(struct drm_i915_private *i915) +{ + struct pci_dev *pdev =3D to_pci_dev(i915->drm.dev); + struct intel_dg_nvm_dev *nvm; + struct auxiliary_device *aux_dev; + int ret; + + /* Only the DGFX devices have internal NVM */ + if (!IS_DGFX(i915)) + return; + + /* Nvm pointer should be NULL here */ + if (WARN_ON(i915->nvm)) + return; + + i915->nvm =3D kzalloc(sizeof(*nvm), GFP_KERNEL); + if (!i915->nvm) + return; + + nvm =3D i915->nvm; + + nvm->writeable_override =3D true; + nvm->bar.parent =3D &pdev->resource[0]; + nvm->bar.start =3D GEN12_GUNIT_NVM_BASE + pdev->resource[0].start; + nvm->bar.end =3D nvm->bar.start + GEN12_GUNIT_NVM_SIZE - 1; + nvm->bar.flags =3D IORESOURCE_MEM; + nvm->bar.desc =3D IORES_DESC_NONE; + nvm->regions =3D regions; + + aux_dev =3D &nvm->aux_dev; + + aux_dev->name =3D "nvm"; + aux_dev->id =3D (pci_domain_nr(pdev->bus) << 16) | + PCI_DEVID(pdev->bus->number, pdev->devfn); + aux_dev->dev.parent =3D &pdev->dev; + aux_dev->dev.release =3D i915_nvm_release_dev; + + ret =3D auxiliary_device_init(aux_dev); + if (ret) { + drm_err(&i915->drm, "i915-nvm aux init failed %d\n", ret); + return; + } + + ret =3D auxiliary_device_add(aux_dev); + if (ret) { + drm_err(&i915->drm, "i915-nvm aux add failed %d\n", ret); + auxiliary_device_uninit(aux_dev); + return; + } +} + +void intel_nvm_fini(struct drm_i915_private *i915) +{ + struct intel_dg_nvm_dev *nvm =3D i915->nvm; + + /* Only the DGFX devices have internal NVM */ + if (!IS_DGFX(i915)) + return; + + /* Nvm pointer should not be NULL here */ + if (WARN_ON(!nvm)) + return; + + drm_err(&i915->drm, "removing i915-nvm cell\n"); + + auxiliary_device_delete(&nvm->aux_dev); + auxiliary_device_uninit(&nvm->aux_dev); + kfree(nvm); + i915->nvm =3D NULL; +} diff --git a/drivers/gpu/drm/i915/intel_nvm.h b/drivers/gpu/drm/i915/intel_= nvm.h new file mode 100644 index 000000000000..7bc3d1114a3f --- /dev/null +++ b/drivers/gpu/drm/i915/intel_nvm.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright(c) 2019-2024 Intel Corporation. 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Signed-off-by: Alexander Usyskin Acked-by: Miquel Raynal Reviewed-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_nvm.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_nvm.c b/drivers/gpu/drm/i915/intel_= nvm.c index 214c4d47a9cd..cbd776e667ad 100644 --- a/drivers/gpu/drm/i915/intel_nvm.c +++ b/drivers/gpu/drm/i915/intel_nvm.c @@ -10,6 +10,7 @@ #include "intel_nvm.h" =20 #define GEN12_GUNIT_NVM_SIZE 0x80 +#define HECI_FW_STATUS_2_NVM_ACCESS_MODE BIT(3) =20 static const struct intel_dg_nvm_region regions[INTEL_DG_NVM_REGIONS] =3D { [0] =3D { .name =3D "DESCRIPTOR", }, @@ -22,6 +23,28 @@ static void i915_nvm_release_dev(struct device *dev) { } =20 +static bool i915_nvm_writeable_override(struct drm_i915_private *i915) +{ + resource_size_t base; + bool writeable_override; + + if (IS_DG1(i915)) { + base =3D DG1_GSC_HECI2_BASE; + } else if (IS_DG2(i915)) { + base =3D DG2_GSC_HECI2_BASE; + } else { + drm_err(&i915->drm, "Unknown platform\n"); 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a="34750814" X-IronPort-AV: E=Sophos;i="6.12,266,1728975600"; d="scan'208";a="34750814" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2024 05:26:40 -0800 X-CSE-ConnectionGUID: TNO//S2cRIq6pDtOiuITNQ== X-CSE-MsgGUID: moCsFgZUTCScknzuz2A2Zw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,266,1728975600"; d="scan'208";a="89921784" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2024 05:26:36 -0800 From: Alexander Usyskin To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Rodrigo Vivi , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jani Nikula , Joonas Lahtinen , Tvrtko Ursulin Cc: Oren Weil , linux-mtd@lists.infradead.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Alexander Usyskin Subject: [PATCH v2 09/10] drm/xe/nvm: add on-die non-volatile memory device Date: Thu, 7 Nov 2024 15:13:55 +0200 Message-ID: <20241107131356.2796969-10-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241107131356.2796969-1-alexander.usyskin@intel.com> References: <20241107131356.2796969-1-alexander.usyskin@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable access to internal non-volatile memory on DGFX with GSC/CSC devices via a child device. The nvm child device is exposed via auxiliary bus. Reviewed-by: Rodrigo Vivi Signed-off-by: Alexander Usyskin Acked-by: Miquel Raynal --- drivers/gpu/drm/xe/Makefile | 1 + drivers/gpu/drm/xe/xe_device.c | 3 + drivers/gpu/drm/xe/xe_device_types.h | 8 +++ drivers/gpu/drm/xe/xe_nvm.c | 100 +++++++++++++++++++++++++++ drivers/gpu/drm/xe/xe_nvm.h | 15 ++++ drivers/gpu/drm/xe/xe_pci.c | 6 ++ 6 files changed, 133 insertions(+) create mode 100644 drivers/gpu/drm/xe/xe_nvm.c create mode 100644 drivers/gpu/drm/xe/xe_nvm.h diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index da80c29aa363..35b191170105 100644 --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@ -94,6 +94,7 @@ xe-y +=3D xe_bb.o \ xe_ring_ops.o \ xe_sa.o \ xe_sched_job.o \ + xe_nvm.o \ xe_step.o \ xe_sync.o \ xe_tile.o \ diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c index 0e2dd691bdae..cd6946c3aa71 100644 --- a/drivers/gpu/drm/xe/xe_device.c +++ b/drivers/gpu/drm/xe/xe_device.c @@ -49,6 +49,7 @@ #include "xe_pcode.h" #include "xe_pm.h" #include "xe_query.h" +#include "xe_nvm.h" #include "xe_sriov.h" #include "xe_tile.h" #include "xe_ttm_stolen_mgr.h" @@ -734,6 +735,7 @@ int xe_device_probe(struct xe_device *xe) goto err_fini_gt; } =20 + xe_nvm_init(xe); xe_heci_gsc_init(xe); =20 err =3D xe_oa_init(xe); @@ -802,6 +804,7 @@ void xe_device_remove(struct xe_device *xe) xe_oa_fini(xe); =20 xe_heci_gsc_fini(xe); + xe_nvm_fini(xe); =20 for_each_gt(gt, xe, id) xe_gt_remove(gt); diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_d= evice_types.h index b9ea455d6f59..d840339d8209 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -35,6 +35,8 @@ struct xe_ggtt; struct xe_pat_ops; =20 +struct intel_dg_nvm_dev; + #define XE_BO_INVALID_OFFSET LONG_MAX =20 #define GRAPHICS_VER(xe) ((xe)->info.graphics_verx100 / 100) @@ -44,6 +46,7 @@ struct xe_pat_ops; #define IS_DGFX(xe) ((xe)->info.is_dgfx) #define HAS_HECI_GSCFI(xe) ((xe)->info.has_heci_gscfi) #define HAS_HECI_CSCFI(xe) ((xe)->info.has_heci_cscfi) +#define HAS_GSC_NVM(xe) ((xe)->info.has_gsc_nvm) =20 #define XE_VRAM_FLAGS_NEED64K BIT(0) =20 @@ -331,6 +334,8 @@ struct xe_device { u8 has_heci_gscfi:1; /** @info.has_heci_cscfi: device has heci cscfi */ u8 has_heci_cscfi:1; + /** @info.has_gsc_nvm: device has gsc non-volatile memory */ + u8 has_gsc_nvm:1; /** @info.skip_guc_pc: Skip GuC based PM feature init */ u8 skip_guc_pc:1; /** @info.has_atomic_enable_pte_bit: Device has atomic enable PTE bit */ @@ -493,6 +498,9 @@ struct xe_device { /** @heci_gsc: graphics security controller */ struct xe_heci_gsc heci_gsc; =20 + /** @nvm: discrete graphics non-volatile memory */ + struct intel_dg_nvm_dev *nvm; + /** @oa: oa observation subsystem */ struct xe_oa oa; =20 diff --git a/drivers/gpu/drm/xe/xe_nvm.c b/drivers/gpu/drm/xe/xe_nvm.c new file mode 100644 index 000000000000..787272761e42 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_nvm.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright(c) 2019-2024, Intel Corporation. All rights reserved. + */ + +#include +#include +#include "xe_device_types.h" +#include "xe_nvm.h" +#include "xe_sriov.h" + +#define GEN12_GUNIT_NVM_BASE 0x00102040 +#define GEN12_GUNIT_NVM_SIZE 0x80 +#define HECI_FW_STATUS_2_NVM_ACCESS_MODE BIT(3) + +static const struct intel_dg_nvm_region regions[INTEL_DG_NVM_REGIONS] =3D { + [0] =3D { .name =3D "DESCRIPTOR", }, + [2] =3D { .name =3D "GSC", }, + [11] =3D { .name =3D "OptionROM", }, + [12] =3D { .name =3D "DAM", }, +}; + +static void xe_nvm_release_dev(struct device *dev) +{ +} + +void xe_nvm_init(struct xe_device *xe) +{ + struct pci_dev *pdev =3D to_pci_dev(xe->drm.dev); + struct intel_dg_nvm_dev *nvm; + struct auxiliary_device *aux_dev; + int ret; + + if (!HAS_GSC_NVM(xe)) + return; + + /* No access to internal NVM from VFs */ + if (IS_SRIOV_VF(xe)) + return; + + /* Nvm pointer should be NULL here */ + if (WARN_ON(xe->nvm)) + return; + + xe->nvm =3D kzalloc(sizeof(*nvm), GFP_KERNEL); + if (!xe->nvm) + return; + + nvm =3D xe->nvm; + + nvm->writeable_override =3D false; + nvm->bar.parent =3D &pdev->resource[0]; + nvm->bar.start =3D GEN12_GUNIT_NVM_BASE + pdev->resource[0].start; + nvm->bar.end =3D nvm->bar.start + GEN12_GUNIT_NVM_SIZE - 1; + nvm->bar.flags =3D IORESOURCE_MEM; + nvm->bar.desc =3D IORES_DESC_NONE; + nvm->regions =3D regions; + + aux_dev =3D &nvm->aux_dev; + + aux_dev->name =3D "nvm"; + aux_dev->id =3D (pci_domain_nr(pdev->bus) << 16) | + PCI_DEVID(pdev->bus->number, pdev->devfn); + aux_dev->dev.parent =3D &pdev->dev; + aux_dev->dev.release =3D xe_nvm_release_dev; + + ret =3D auxiliary_device_init(aux_dev); + if (ret) { + drm_err(&xe->drm, "xe-nvm aux init failed %d\n", ret); + return; + } + + ret =3D auxiliary_device_add(aux_dev); + if (ret) { + drm_err(&xe->drm, "xe-nvm aux add failed %d\n", ret); + auxiliary_device_uninit(aux_dev); + return; + } +} + +void xe_nvm_fini(struct xe_device *xe) +{ + struct intel_dg_nvm_dev *nvm =3D xe->nvm; + + if (!HAS_GSC_NVM(xe)) + return; + + /* No access to internal NVM from VFs */ + if (IS_SRIOV_VF(xe)) + return; + + /* Nvm pointer should not be NULL here */ + if (WARN_ON(!nvm)) + return; + + auxiliary_device_delete(&nvm->aux_dev); + auxiliary_device_uninit(&nvm->aux_dev); + kfree(nvm); + xe->nvm =3D NULL; +} diff --git a/drivers/gpu/drm/xe/xe_nvm.h b/drivers/gpu/drm/xe/xe_nvm.h new file mode 100644 index 000000000000..068695447913 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_nvm.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright(c) 2019-2024 Intel Corporation. All rights reserved. + */ + +#ifndef __XE_NVM_H__ +#define __XE_NVM_H__ + +struct xe_device; + +void xe_nvm_init(struct xe_device *xe); + +void xe_nvm_fini(struct xe_device *xe); + +#endif /* __XE_NVM_H__ */ diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index 64a8336ca437..dad9f10cf05b 100644 --- a/drivers/gpu/drm/xe/xe_pci.c +++ b/drivers/gpu/drm/xe/xe_pci.c @@ -60,6 +60,7 @@ struct xe_device_desc { u8 has_display:1; u8 has_heci_gscfi:1; u8 has_heci_cscfi:1; + u8 has_gsc_nvm:1; u8 has_llc:1; u8 has_mmio_ext:1; u8 has_sriov:1; @@ -282,6 +283,7 @@ static const struct xe_device_desc dg1_desc =3D { PLATFORM(DG1), .has_display =3D true, .has_heci_gscfi =3D 1, + .has_gsc_nvm =3D 1, .require_force_probe =3D true, }; =20 @@ -293,6 +295,7 @@ static const u16 dg2_g12_ids[] =3D { XE_DG2_G12_IDS(NOP= ), 0 }; DGFX_FEATURES, \ PLATFORM(DG2), \ .has_heci_gscfi =3D 1, \ + .has_gsc_nvm =3D 1, \ .subplatforms =3D (const struct xe_subplatform_desc[]) { \ { XE_SUBPLATFORM_DG2_G10, "G10", dg2_g10_ids }, \ { XE_SUBPLATFORM_DG2_G11, "G11", dg2_g11_ids }, \ @@ -324,6 +327,7 @@ static const __maybe_unused struct xe_device_desc pvc_d= esc =3D { PLATFORM(PVC), .has_display =3D false, .has_heci_gscfi =3D 1, + .has_gsc_nvm =3D 1, .require_force_probe =3D true, }; =20 @@ -344,6 +348,7 @@ static const struct xe_device_desc bmg_desc =3D { PLATFORM(BATTLEMAGE), .has_display =3D true, .has_heci_cscfi =3D 1, + .has_gsc_nvm =3D 1, }; =20 static const struct xe_device_desc ptl_desc =3D { @@ -623,6 +628,7 @@ static int xe_info_init_early(struct xe_device *xe, xe->info.is_dgfx =3D desc->is_dgfx; xe->info.has_heci_gscfi =3D desc->has_heci_gscfi; xe->info.has_heci_cscfi =3D desc->has_heci_cscfi; + xe->info.has_gsc_nvm =3D desc->has_gsc_nvm; xe->info.has_llc =3D desc->has_llc; xe->info.has_mmio_ext =3D desc->has_mmio_ext; xe->info.has_sriov =3D desc->has_sriov; --=20 2.43.0 From nobody Sun Nov 24 04:49:27 2024 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 19618212F0E for ; Thu, 7 Nov 2024 13:26:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; 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spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Tnpduwm1" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730986005; x=1762522005; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=E233I3I6GcoFzPCbkV4ez7ihHSVbpBY2WBZMmgRDhzE=; b=Tnpduwm1m+WHRv/sBT4H28/UwS7fyNNspxx/tI/nSuIGG/mefZxPDoNf EewYmnY39H0Yx6AAKyvotZt93wFub84rrqPSr88kLVR9heJyMZJE66t6N lD5Vb8LUQsGPwkpkG0yYc0FjIG8JMCdLRtXDju3Wnh93SBZSbTpXl7Xft ax35X7fS4+jwDKN+ZmIP7utu4s6wMU9s4U+A4eYtPmVm2J8wFxbqqunTN ofzFZFp4t9ciV7gkOKleZPxlf9w6Lm13uWF89uc1+jXD0A0ITGwYcIy0z 0K8JW2aynjZEAozckuTXwoid9jLSPnEMqljKfKfygPr5V+JtqdSN8hIBe Q==; X-CSE-ConnectionGUID: dKV2wlyjRPKz+xxY7CNhDg== X-CSE-MsgGUID: NPJ3CTo5T2+O0FjWsz+QJw== X-IronPort-AV: E=McAfee;i="6700,10204,11249"; a="34750828" X-IronPort-AV: E=Sophos;i="6.12,266,1728975600"; d="scan'208";a="34750828" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2024 05:26:44 -0800 X-CSE-ConnectionGUID: 2HZJLObbTpywNq8tLRvuWg== X-CSE-MsgGUID: sN2rS/S+TbiOxKdGuSPL1w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,266,1728975600"; d="scan'208";a="89921814" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2024 05:26:41 -0800 From: Alexander Usyskin To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Rodrigo Vivi , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jani Nikula , Joonas Lahtinen , Tvrtko Ursulin Cc: Oren Weil , linux-mtd@lists.infradead.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Alexander Usyskin Subject: [PATCH v2 10/10] drm/xe/nvm: add support for access mode Date: Thu, 7 Nov 2024 15:13:56 +0200 Message-ID: <20241107131356.2796969-11-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241107131356.2796969-1-alexander.usyskin@intel.com> References: <20241107131356.2796969-1-alexander.usyskin@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Check NVM access mode from GSC FW status registers and overwrite access status read from SPI descriptor, if needed. Signed-off-by: Alexander Usyskin Acked-by: Miquel Raynal --- drivers/gpu/drm/xe/regs/xe_gsc_regs.h | 4 ++++ drivers/gpu/drm/xe/xe_heci_gsc.c | 5 +---- drivers/gpu/drm/xe/xe_nvm.c | 32 ++++++++++++++++++++++++++- 3 files changed, 36 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/xe/regs/xe_gsc_regs.h b/drivers/gpu/drm/xe/reg= s/xe_gsc_regs.h index 7702364b65f1..9b66cc972a63 100644 --- a/drivers/gpu/drm/xe/regs/xe_gsc_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gsc_regs.h @@ -16,6 +16,10 @@ #define MTL_GSC_HECI1_BASE 0x00116000 #define MTL_GSC_HECI2_BASE 0x00117000 =20 +#define DG1_GSC_HECI2_BASE 0x00259000 +#define PVC_GSC_HECI2_BASE 0x00285000 +#define DG2_GSC_HECI2_BASE 0x00374000 + #define HECI_H_CSR(base) XE_REG((base) + 0x4) #define HECI_H_CSR_IE REG_BIT(0) #define HECI_H_CSR_IS REG_BIT(1) diff --git a/drivers/gpu/drm/xe/xe_heci_gsc.c b/drivers/gpu/drm/xe/xe_heci_= gsc.c index 65b2e147c4b9..27734085164e 100644 --- a/drivers/gpu/drm/xe/xe_heci_gsc.c +++ b/drivers/gpu/drm/xe/xe_heci_gsc.c @@ -11,14 +11,11 @@ #include "xe_device_types.h" #include "xe_drv.h" #include "xe_heci_gsc.h" +#include "regs/xe_gsc_regs.h" #include "xe_platform_types.h" =20 #define GSC_BAR_LENGTH 0x00000FFC =20 -#define DG1_GSC_HECI2_BASE 0x259000 -#define PVC_GSC_HECI2_BASE 0x285000 -#define DG2_GSC_HECI2_BASE 0x374000 - static void heci_gsc_irq_mask(struct irq_data *d) { /* generic irq handling */ diff --git a/drivers/gpu/drm/xe/xe_nvm.c b/drivers/gpu/drm/xe/xe_nvm.c index 787272761e42..3396bec29c97 100644 --- a/drivers/gpu/drm/xe/xe_nvm.c +++ b/drivers/gpu/drm/xe/xe_nvm.c @@ -5,8 +5,11 @@ =20 #include #include +#include "xe_device.h" #include "xe_device_types.h" +#include "xe_mmio.h" #include "xe_nvm.h" +#include "regs/xe_gsc_regs.h" #include "xe_sriov.h" =20 #define GEN12_GUNIT_NVM_BASE 0x00102040 @@ -24,6 +27,33 @@ static void xe_nvm_release_dev(struct device *dev) { } =20 +static bool xe_nvm_writeable_override(struct xe_device *xe) +{ + struct xe_gt *gt =3D xe_root_mmio_gt(xe); + resource_size_t base; + bool writeable_override; + + if (xe->info.platform =3D=3D XE_BATTLEMAGE) { + base =3D DG2_GSC_HECI2_BASE; + } else if (xe->info.platform =3D=3D XE_PVC) { + base =3D PVC_GSC_HECI2_BASE; + } else if (xe->info.platform =3D=3D XE_DG2) { + base =3D DG2_GSC_HECI2_BASE; + } else if (xe->info.platform =3D=3D XE_DG1) { + base =3D DG1_GSC_HECI2_BASE; + } else { + drm_err(&xe->drm, "Unknown platform\n"); + return true; + } + + writeable_override =3D + !(xe_mmio_read32(>->mmio, HECI_FWSTS2(base)) & + HECI_FW_STATUS_2_NVM_ACCESS_MODE); + if (writeable_override) + drm_info(&xe->drm, "NVM access overridden by jumper\n"); + return writeable_override; +} + void xe_nvm_init(struct xe_device *xe) { struct pci_dev *pdev =3D to_pci_dev(xe->drm.dev); @@ -48,7 +78,7 @@ void xe_nvm_init(struct xe_device *xe) =20 nvm =3D xe->nvm; =20 - nvm->writeable_override =3D false; + nvm->writeable_override =3D xe_nvm_writeable_override(xe); nvm->bar.parent =3D &pdev->resource[0]; nvm->bar.start =3D GEN12_GUNIT_NVM_BASE + pdev->resource[0].start; nvm->bar.end =3D nvm->bar.start + GEN12_GUNIT_NVM_SIZE - 1; --=20 2.43.0