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charset="utf-8" Add SPDIF IPG clk. The SPDIF IPG clock and root clock share same clock gate. Signed-off-by: Shengjiu Wang Reviewed-by: Frank Li --- include/dt-bindings/clock/imx93-clock.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/imx93-clock.h b/include/dt-bindings/= clock/imx93-clock.h index 6c685067288b..c393fad3a346 100644 --- a/include/dt-bindings/clock/imx93-clock.h +++ b/include/dt-bindings/clock/imx93-clock.h @@ -209,5 +209,6 @@ #define IMX91_CLK_ENET2_REGULAR 204 #define IMX91_CLK_ENET2_REGULAR_GATE 205 #define IMX91_CLK_ENET1_QOS_TSN_GATE 206 +#define IMX93_CLK_SPDIF_IPG 207 =20 #endif --=20 2.34.1 From nobody Sun Nov 24 03:28:02 2024 Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2046.outbound.protection.outlook.com [40.107.20.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BADFE1EC01E; Thu, 7 Nov 2024 10:11:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.20.46 ARC-Seal: i=2; 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charset="utf-8" The IMX93_CLK_SPDIF_GATE also controls the gate of IPG clock and root clock, need to define them separately. Otherwise driver disable IMX93_CLK_SPDIF_GATE will cause IPG clock is also disabled, then register accessing fail. Signed-off-by: Shengjiu Wang Reviewed-by: Frank Li --- drivers/clk/imx/clk-imx93.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c index 58a516dd385b..eb818db008fb 100644 --- a/drivers/clk/imx/clk-imx93.c +++ b/drivers/clk/imx/clk-imx93.c @@ -15,7 +15,7 @@ =20 #include "clk.h" =20 -#define IMX93_CLK_END 207 +#define IMX93_CLK_END 208 =20 #define PLAT_IMX93 BIT(0) #define PLAT_IMX91 BIT(1) @@ -38,6 +38,7 @@ static u32 share_count_sai2; static u32 share_count_sai3; static u32 share_count_mub; static u32 share_count_pdm; +static u32 share_count_spdif; =20 static const char * const a55_core_sels[] =3D {"a55_alt", "arm_pll"}; static const char *parent_names[MAX_SEL][4] =3D { @@ -252,7 +253,8 @@ static const struct imx93_clk_ccgr { { IMX93_CLK_MQS1_GATE, "mqs1", "sai1_root", 0x9b00, }, { IMX93_CLK_MQS2_GATE, "mqs2", "sai3_root", 0x9b40, }, { IMX93_CLK_AUD_XCVR_GATE, "aud_xcvr", "audio_xcvr_root", 0x9b80, }, - { IMX93_CLK_SPDIF_GATE, "spdif", "spdif_root", 0x9c00, }, + { IMX93_CLK_SPDIF_IPG, "spdif_ipg_clk", "bus_wakeup_root", 0x9c00, 0, &s= hare_count_spdif}, + { IMX93_CLK_SPDIF_GATE, "spdif", "spdif_root", 0x9c00, 0, &share_count_= spdif}, { IMX93_CLK_HSIO_32K_GATE, "hsio_32k", "osc_32k", 0x9dc0, }, { IMX93_CLK_ENET1_GATE, "enet1", "wakeup_axi_root", 0x9e00, 0, NULL, PLA= T_IMX93, }, { IMX93_CLK_ENET_QOS_GATE, "enet_qos", "wakeup_axi_root", 0x9e40, 0, NULL= , PLAT_IMX93, }, --=20 2.34.1 From nobody Sun Nov 24 03:28:02 2024 Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2046.outbound.protection.outlook.com [40.107.20.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D17491EABB4; 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charset="utf-8" IMX93_CLK_BUS_WAKEUP is not accurate IPG clock, which missed the clock gate. IMX93_CLK_SPDIF_IPG is the correct clock. Signed-off-by: Shengjiu Wang Reviewed-by: Frank Li --- arch/arm64/boot/dts/freescale/imx93.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts= /freescale/imx93.dtsi index 688488de8cd2..56766fdb0b1e 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -925,7 +925,7 @@ xcvr: xcvr@42680000 { reg-names =3D "ram", "regs", "rxfifo", "txfifo"; interrupts =3D , ; - clocks =3D <&clk IMX93_CLK_BUS_WAKEUP>, + clocks =3D <&clk IMX93_CLK_SPDIF_IPG>, <&clk IMX93_CLK_SPDIF_GATE>, <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_AUD_XCVR_GATE>; --=20 2.34.1