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Thu, 07 Nov 2024 08:05:20 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 4A785G1d004533; Thu, 7 Nov 2024 08:05:16 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 42nd5mu5nw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Thu, 07 Nov 2024 08:05:16 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 4A785DfI004498; Thu, 7 Nov 2024 08:05:15 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-sartgarg-hyd.qualcomm.com [10.213.105.147]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 4A785FUa004527; Thu, 07 Nov 2024 08:05:15 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2339771) id E2F105013D2; Thu, 7 Nov 2024 13:35:14 +0530 (+0530) From: Sarthak Garg To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Adrian Hunter , Bhupesh Sharma Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, quic_cang@quicinc.com, quic_nguyenb@quicinc.com, quic_rampraka@quicinc.com, quic_pragalla@quicinc.com, quic_sayalil@quicinc.com, quic_nitirawa@quicinc.com, quic_sachgupt@quicinc.com, quic_bhaskarv@quicinc.com, quic_narepall@quicinc.com, kernel@quicinc.com, Sarthak Garg Subject: [PATCH V1 3/3] mmc: sdhci-msm: Limit HS mode frequency to 37.5MHz Date: Thu, 7 Nov 2024 13:35:05 +0530 Message-Id: <20241107080505.29244-4-quic_sartgarg@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241107080505.29244-1-quic_sartgarg@quicinc.com> References: <20241107080505.29244-1-quic_sartgarg@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: LkANyD9lYgCDZA9MYRePx1y3Fhq-FenZ X-Proofpoint-GUID: LkANyD9lYgCDZA9MYRePx1y3Fhq-FenZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 lowpriorityscore=0 priorityscore=1501 clxscore=1015 mlxscore=0 spamscore=0 suspectscore=0 bulkscore=0 phishscore=0 adultscore=0 impostorscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411070060 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For Qualcomm SoCs with level shifter delays are seen on receivers data path due to latency added by level shifter. To bring these delays in normal range and avoid CMD CRC errors reduce frequency for HS mode SD cards to 37.5MHz for targets which has level shifter. Signed-off-by: Sarthak Garg --- drivers/mmc/host/sdhci-msm.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 16325c21de52..5e1dc06c4707 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -138,6 +138,8 @@ /* Max load for eMMC Vdd-io supply */ #define MMC_VQMMC_MAX_LOAD_UA 325000 =20 +#define LEVEL_SHIFTER_HIGH_SPEED_FREQ 37500000 + #define msm_host_readl(msm_host, host, offset) \ msm_host->var_ops->msm_readl_relaxed(host, offset) =20 @@ -287,6 +289,7 @@ struct sdhci_msm_host { bool use_cdr; u32 transfer_mode; bool updated_ddr_cfg; + bool uses_level_shifter; bool uses_tassadar_dll; u32 dll_config; u32 ddr_config; @@ -366,6 +369,11 @@ static void msm_set_clock_rate_for_bus_mode(struct sdh= ci_host *host, =20 mult =3D msm_get_clock_mult_for_bus_mode(host); desired_rate =3D clock * mult; + + if (curr_ios.timing =3D=3D MMC_TIMING_SD_HS && desired_rate =3D=3D 500000= 00 + && msm_host->uses_level_shifter) + desired_rate =3D LEVEL_SHIFTER_HIGH_SPEED_FREQ; + rc =3D dev_pm_opp_set_rate(mmc_dev(host->mmc), desired_rate); if (rc) { pr_err("%s: Failed to set clock at rate %u at timing %d\n", @@ -2372,6 +2380,8 @@ static inline void sdhci_msm_get_of_property(struct p= latform_device *pdev, =20 of_property_read_u32(node, "qcom,dll-config", &msm_host->dll_config); =20 + msm_host->uses_level_shifter =3D of_property_read_bool(node, "qcom,use-le= vel-shifter"); + if (of_device_is_compatible(node, "qcom,msm8916-sdhci")) host->quirks2 |=3D SDHCI_QUIRK2_BROKEN_64_BIT_DMA; } --=20 2.17.1