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Thu, 07 Nov 2024 08:05:17 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 4A785EUl004504; Thu, 7 Nov 2024 08:05:14 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 42nd5mu5nn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Thu, 07 Nov 2024 08:05:14 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 4A785DfG004498; Thu, 7 Nov 2024 08:05:13 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-sartgarg-hyd.qualcomm.com [10.213.105.147]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 4A785DBW004497; Thu, 07 Nov 2024 08:05:13 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2339771) id EB08C5013D2; Thu, 7 Nov 2024 13:35:12 +0530 (+0530) From: Sarthak Garg To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Adrian Hunter , Bhupesh Sharma Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, quic_cang@quicinc.com, quic_nguyenb@quicinc.com, quic_rampraka@quicinc.com, quic_pragalla@quicinc.com, quic_sayalil@quicinc.com, quic_nitirawa@quicinc.com, quic_sachgupt@quicinc.com, quic_bhaskarv@quicinc.com, quic_narepall@quicinc.com, kernel@quicinc.com, Sarthak Garg Subject: [PATCH V1 2/3] mmc: sdhci-msm: Enable tuning for SDR50 mode for SD card Date: Thu, 7 Nov 2024 13:35:04 +0530 Message-Id: <20241107080505.29244-3-quic_sartgarg@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241107080505.29244-1-quic_sartgarg@quicinc.com> References: <20241107080505.29244-1-quic_sartgarg@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: GPwoXT1SiJF8lCQw0ks1YqylnfKqbKtY X-Proofpoint-GUID: GPwoXT1SiJF8lCQw0ks1YqylnfKqbKtY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxlogscore=999 suspectscore=0 spamscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 mlxscore=0 adultscore=0 priorityscore=1501 bulkscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411070060 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For Qualcomm SoCs which needs level shifter for SD card, extra delay is seen on receiver data path. To compensate this delay enable tuning for SDR50 mode for targets which has level shifter. Signed-off-by: Sarthak Garg --- drivers/mmc/host/sdhci-msm.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index e00208535bd1..16325c21de52 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -81,6 +81,7 @@ #define CORE_IO_PAD_PWR_SWITCH_EN BIT(15) #define CORE_IO_PAD_PWR_SWITCH BIT(16) #define CORE_HC_SELECT_IN_EN BIT(18) +#define CORE_HC_SELECT_IN_SDR50 (4 << 19) #define CORE_HC_SELECT_IN_HS400 (6 << 19) #define CORE_HC_SELECT_IN_MASK (7 << 19) =20 @@ -1124,6 +1125,10 @@ static bool sdhci_msm_is_tuning_needed(struct sdhci_= host *host) { struct mmc_ios *ios =3D &host->mmc->ios; =20 + if (ios->timing =3D=3D MMC_TIMING_UHS_SDR50 && + host->flags & SDHCI_SDR50_NEEDS_TUNING) + return true; + /* * Tuning is required for SDR104, HS200 and HS400 cards and * if clock frequency is greater than 100MHz in these modes. @@ -1192,6 +1197,8 @@ static int sdhci_msm_execute_tuning(struct mmc_host *= mmc, u32 opcode) struct mmc_ios ios =3D host->mmc->ios; struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); struct sdhci_msm_host *msm_host =3D sdhci_pltfm_priv(pltfm_host); + const struct sdhci_msm_offset *msm_offset =3D msm_host->offset; + u32 config; =20 if (!sdhci_msm_is_tuning_needed(host)) { msm_host->use_cdr =3D false; @@ -1208,6 +1215,15 @@ static int sdhci_msm_execute_tuning(struct mmc_host = *mmc, u32 opcode) */ msm_host->tuning_done =3D 0; =20 + if (ios.timing =3D=3D MMC_TIMING_UHS_SDR50 && + host->flags & SDHCI_SDR50_NEEDS_TUNING) { + config =3D readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); + config |=3D CORE_HC_SELECT_IN_EN; + config &=3D ~CORE_HC_SELECT_IN_MASK; + config |=3D CORE_HC_SELECT_IN_SDR50; + writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); + } + /* * For HS400 tuning in HS200 timing requires: * - select MCLK/2 in VENDOR_SPEC --=20 2.17.1