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[83.233.6.197]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2ff179d80f5sm2276591fa.105.2024.11.07.05.47.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Nov 2024 05:47:33 -0800 (PST) From: Marcus Folkesson Date: Thu, 07 Nov 2024 14:47:07 +0100 Subject: [PATCH v7 1/2] mtd: nand: davinci: add support for on-die ECC engine type Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241107-ondie-v7-1-98829fc8a958@gmail.com> References: <20241107-ondie-v7-0-98829fc8a958@gmail.com> In-Reply-To: <20241107-ondie-v7-0-98829fc8a958@gmail.com> To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Marcus Folkesson X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1761; i=marcus.folkesson@gmail.com; h=from:subject:message-id; bh=aEezSAYRZux5sp8R/V/BZi69L/f49HVcP44j8wR1Vf8=; b=owEBbQKS/ZANAwAIAYiATm9ZXVIyAcsmYgBnLMTomdUX6qyJCp5iC5mJbbMGc/zZt+dO48AXd cJzzvAvBlOJAjMEAAEIAB0WIQQFUaLotmy1TWTBLGWIgE5vWV1SMgUCZyzE6AAKCRCIgE5vWV1S MrR3D/sFuhOd8C3qeA1eeAPtI5jyaqZ501Z7Jvnijo/eKG2sexB2doGkM5mDbHfmanCYTEaX6R6 OfVO03LCSAqElMilqYG8q0o8hfo2Ad/dmDg58tjrKCAqaEsiElMjdr5FpI7Q782s3XnbZ8vq5Ih 6SlzQwyMLQxeJMVlaIUVYnm6gh5X4y37NHABs7Kr+IpbpppUdcHjyxc6gUOZQFopGA65uQIaDZy X4gc0yO8d+qxyRTpnZkNcZoLz3TyyakL3ikVLYXkxjryeLYF9p7bO95vXytU4Zi1SLNyyJ6hCdW KV1rItkX1Id4+3HyqWrEii90BIw/CzoVoCOUSMHxSc//BKihZgFznpbLuJXHCWh/afTzBvMuH6B Z8zp+knjRwbcfgU5vpkiDSvMTLrM1xKL2wvmwcy2P+mJiAYDYo8VMJBUOPV8eHAmMQwM9KBXhge NhhyD5hRC8Nlq03Kju7D+IMnB+M3P+9I3CNrh5BxS0W5pkaMyIiJDcZ5mbfTEGa+D1RtHq+X8xe dLHMUdHHBpe2F/fZ7jMJ1/PW5iuq1xyqyb5yGHDfcLVTBycTD9UEojc5drZlHyyz50YMs9Ueoe5 W+FW0e5ZT7WXTNHG5u5TP6RZHRkpsdfAzg/6OHTridZcPbUi5i6hkUE8mID/0j2Y9UGbVQI/u8+ 7qd1Wm3wWJnLchQ== X-Developer-Key: i=marcus.folkesson@gmail.com; a=openpgp; fpr=AB91D46C7E0F6E6FB2AB640EC0FE25D598F6C127 Some chips, e.g. Micron MT29F1G08ABBFAH4, has a mandatory on-die ECC. Add "on-die" as ECC engine type in order to be compatible with those. Signed-off-by: Marcus Folkesson --- drivers/mtd/nand/raw/davinci_nand.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/dav= inci_nand.c index 392678143a36b20b42c1827eee8203dc2e41889a..79e768d337ae12f6e8d7f21f1ac= d4e259f4f3020 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -66,6 +66,7 @@ struct davinci_nand_pdata { =20 /* none =3D=3D NAND_ECC_ENGINE_TYPE_NONE (strongly *not* advised!!) * soft =3D=3D NAND_ECC_ENGINE_TYPE_SOFT + * on-die =3D=3D NAND_ECC_ENGINE_TYPE_ON_DIE * else =3D=3D NAND_ECC_ENGINE_TYPE_ON_HOST, according to ecc_bits * * All DaVinci-family chips support 1-bit hardware ECC. @@ -524,6 +525,8 @@ static struct davinci_nand_pdata pdata->engine_type =3D NAND_ECC_ENGINE_TYPE_SOFT; if (!strncmp("hw", mode, 2)) pdata->engine_type =3D NAND_ECC_ENGINE_TYPE_ON_HOST; + if (!strncmp("on-die", mode, 6)) + pdata->engine_type =3D NAND_ECC_ENGINE_TYPE_ON_DIE; } if (!of_property_read_u32(pdev->dev.of_node, "ti,davinci-ecc-bits", &prop)) @@ -580,6 +583,7 @@ static int davinci_nand_attach_chip(struct nand_chip *c= hip) =20 switch (chip->ecc.engine_type) { case NAND_ECC_ENGINE_TYPE_NONE: + case NAND_ECC_ENGINE_TYPE_ON_DIE: pdata->ecc_bits =3D 0; break; case NAND_ECC_ENGINE_TYPE_SOFT: @@ -914,4 +918,3 @@ module_platform_driver(nand_davinci_driver); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Texas Instruments"); MODULE_DESCRIPTION("Davinci NAND flash driver"); - --=20 2.47.0