From nobody Sun Nov 24 04:41:05 2024 Received: from mail-lf1-f54.google.com (mail-lf1-f54.google.com [209.85.167.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D9571DFDB4; Thu, 7 Nov 2024 09:20:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730971221; cv=none; b=Vn/s71shh+u+KtB16EOiddR5C+MB60K4YfoKijz5yI2NKx+++27KAugqXveSlqQbN2m9575yO+AUp4woF8AT0P4KDVdRI0sbgfIw+PsZKksIcOUWZfBZQgL5cZC4zfgxHYCSA+SVlTwqEk9/R3Jr+e/tipBf6j41uetBnXLJRpI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730971221; c=relaxed/simple; bh=aEezSAYRZux5sp8R/V/BZi69L/f49HVcP44j8wR1Vf8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hR5tBraaJqEUX1TkBMo8R+oawiFCLjFW7ANgMdx9Hpu4+4VoML2fp5zY+RXjl62nKPsoyvk+f9JmPzxQAPDUPI0ai4wRVuD6Q79AqAjaBxbXKJL3jJisgaNCqSJ7+eqUCfytE8lmtxKuHvscyP0Dfp19FttbNpcrCL7lIaY0M4E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=YWxzNMz8; arc=none smtp.client-ip=209.85.167.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="YWxzNMz8" Received: by mail-lf1-f54.google.com with SMTP id 2adb3069b0e04-539f8490856so739076e87.2; Thu, 07 Nov 2024 01:20:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730971218; x=1731576018; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=smTKmYgVjf2tZh/nJwAXDtC0KskLoU7un/mwCANgBrg=; b=YWxzNMz8H62YNemL0RdK3y7YaSjT/mnUSxhLoy0Qdpvmp30gM6/JMJsTk9+7f9gegl 4y6wksgMyfV2VgBHR3oRe+LLRfHyFNyHX9Y7Q1EWbQg59SBCaXoMSXJ3EtOyr4sOXPLK gpTp7ZClUHwvmQaiLE5bh+O5+4G7TjZwBlrt6m2uTBn+Hri/ULD3MsJvOZBS53wMJnRP zDW7egZv7KOlW+8NwmdTggSdSjCeHs3niBv1teDBDZopXH2aoP+4Uvt2pvI0436c+zjT bkX/SdAJ/I4PdGNvgjhCIgkgtLSWWhrPiTn4KDWbDiXqHKG4LGVRizjQ3qYpOVEVfNHb cB5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730971218; x=1731576018; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=smTKmYgVjf2tZh/nJwAXDtC0KskLoU7un/mwCANgBrg=; b=Ar/WoQi75R8XdacXchEOFV+P4eiZgNrDqNo+rMZzVthgbYrmCbZBeo4YLfJ6AvtCkC /MpUWh+ACZ74hbTWC3TPMpH4QdQQI/rHLgBCrfZq4XlOgqsvXVOp5+S0DS2rr/WHiQZz pVMaPOvrXVYIY3pX/WxzblPzZ9a6xsArLaQjLFnPdlddqk/m9GQY0vLbCtDSaL1+n/Bh nspd7i62+GfxC5te2ZhDpzopP7UlIDSHC7qymzyd6LErRGlaTAlwGWdtlQtXnZqJFp2e PzRswcwKunuBhJlJTXWYJ1hQJz79L7IJ2Vhe9xzRZljkRc1AZJDCUHai8Y3+pNXCYUyi nomQ== X-Forwarded-Encrypted: i=1; AJvYcCUt4SG3vd17Ayoh81x2uXON4veCZ5WGDb/BZgdP0eP7s2Pocp2yjAPSiDQBk7mlAiWPHrsWC08wB3JVx1Le@vger.kernel.org, AJvYcCX2/AS4q1jabrVzRe5ipuBww0w6eUvnPbw0LrbNZPdsnRrJkrb5Y3ezbMeyztO9FPLkUMDBSFPsLuLm@vger.kernel.org X-Gm-Message-State: AOJu0YyB9X1XdV7zbQahh7WsQBQVS0R5DfGH+sL4tvM2SqK+1HIRYJmb bOgqK6UlblTZy14COPlrNhOX60qPwduju0EiCM8cKoBKYQqOTE7Gq1D8H89O X-Google-Smtp-Source: AGHT+IFuIiLW2mk1ed3zYO/2ZhWW3/RTdXo26ke6p/NuYlsoFxOGKyvFrI12iIQ0sjMuQZgqnxIZdw== X-Received: by 2002:a05:6512:2248:b0:53a:aea:a9e1 with SMTP id 2adb3069b0e04-53d840a6931mr152942e87.54.1730971218007; Thu, 07 Nov 2024 01:20:18 -0800 (PST) Received: from [192.168.1.11] (83-233-6-197.cust.bredband2.com. [83.233.6.197]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53d826a9b50sm139509e87.182.2024.11.07.01.20.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Nov 2024 01:20:16 -0800 (PST) From: Marcus Folkesson Date: Thu, 07 Nov 2024 10:19:53 +0100 Subject: [PATCH v6 1/2] mtd: nand: davinci: add support for on-die ECC engine type Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241107-ondie-v6-1-f70905dc12bf@gmail.com> References: <20241107-ondie-v6-0-f70905dc12bf@gmail.com> In-Reply-To: <20241107-ondie-v6-0-f70905dc12bf@gmail.com> To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Marcus Folkesson X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1761; i=marcus.folkesson@gmail.com; h=from:subject:message-id; bh=aEezSAYRZux5sp8R/V/BZi69L/f49HVcP44j8wR1Vf8=; b=owEBbQKS/ZANAwAIAYiATm9ZXVIyAcsmYgBnLIZAFjNw3EK+EcvSnpI7MpKvyuxjbmeYprbII Nj8FMoFDj+JAjMEAAEIAB0WIQQFUaLotmy1TWTBLGWIgE5vWV1SMgUCZyyGQAAKCRCIgE5vWV1S MnnwEACCRn+mYJTDuG0gkPH7hwwi6zmKOcnUZD3SCKVhRNOrsVTg2PZ5Umq1fzK5h+5bE+NtpcQ qifVLbFXsZRTdioh6g39Jrv/tjnmFxqWU5GaHoGpkwIBtZL3D/m/UOX+DCLhZa2X68lJs5gQBpH Uh2uh2WJfKh+sPeZm1si8XFbdEH/n5c3HbALGsIcGTZ2pSMHdZmqVAkqiuc4+FPAgNZ2rhbzC+2 t8/LcKGCCgEpx1K6r5U66qaDxJQBXOZGcpAw3PgV61L4PaWoD+IbQgLTK8U3vqOiTWuaYHBckWy 6JKidxhiuQ4LhL2L9FQ8zLyx+Q7SQ0b1qk6Vg7+heGCBXaHs+M39oaT9TFAH/b+ErC04W47hTWD 3r2txc0uFt4I37L+njC8FvlU+coNkddbXzPF2anYdroxAlZ58TGuNB//yORCtwfKBAcrbUSnO4g avgNppx7IgggmDscuFhSF1SUqJA+yLbypacQjgfUagaA3WXO3+GvYMQFi8RDY0bXMs9hJt/XF46 u8RWKZlYJS0nfN+hVEDVBS/zgcml85faQbFY7Ed1tx8L0VAREB/7vN0C+oG0+BNO/DjuDHydtH1 KCExe1TrVkK+xPR2gl4noWDoRbLHMj+tHZ2VnXCZAVk9glf/sj+YDMfNe08bY+UjwF+8BIkKqwV d+uOlwpVh3WdK/g== X-Developer-Key: i=marcus.folkesson@gmail.com; a=openpgp; fpr=AB91D46C7E0F6E6FB2AB640EC0FE25D598F6C127 Some chips, e.g. Micron MT29F1G08ABBFAH4, has a mandatory on-die ECC. Add "on-die" as ECC engine type in order to be compatible with those. Signed-off-by: Marcus Folkesson --- drivers/mtd/nand/raw/davinci_nand.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/dav= inci_nand.c index 392678143a36b20b42c1827eee8203dc2e41889a..79e768d337ae12f6e8d7f21f1ac= d4e259f4f3020 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -66,6 +66,7 @@ struct davinci_nand_pdata { =20 /* none =3D=3D NAND_ECC_ENGINE_TYPE_NONE (strongly *not* advised!!) * soft =3D=3D NAND_ECC_ENGINE_TYPE_SOFT + * on-die =3D=3D NAND_ECC_ENGINE_TYPE_ON_DIE * else =3D=3D NAND_ECC_ENGINE_TYPE_ON_HOST, according to ecc_bits * * All DaVinci-family chips support 1-bit hardware ECC. @@ -524,6 +525,8 @@ static struct davinci_nand_pdata pdata->engine_type =3D NAND_ECC_ENGINE_TYPE_SOFT; if (!strncmp("hw", mode, 2)) pdata->engine_type =3D NAND_ECC_ENGINE_TYPE_ON_HOST; + if (!strncmp("on-die", mode, 6)) + pdata->engine_type =3D NAND_ECC_ENGINE_TYPE_ON_DIE; } if (!of_property_read_u32(pdev->dev.of_node, "ti,davinci-ecc-bits", &prop)) @@ -580,6 +583,7 @@ static int davinci_nand_attach_chip(struct nand_chip *c= hip) =20 switch (chip->ecc.engine_type) { case NAND_ECC_ENGINE_TYPE_NONE: + case NAND_ECC_ENGINE_TYPE_ON_DIE: pdata->ecc_bits =3D 0; break; case NAND_ECC_ENGINE_TYPE_SOFT: @@ -914,4 +918,3 @@ module_platform_driver(nand_davinci_driver); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Texas Instruments"); MODULE_DESCRIPTION("Davinci NAND flash driver"); - --=20 2.47.0 From nobody Sun Nov 24 04:41:05 2024 Received: from mail-lf1-f47.google.com (mail-lf1-f47.google.com [209.85.167.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D86011E261C; Thu, 7 Nov 2024 09:20:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730971225; cv=none; b=JmSPPPd+0Vyl/++OKW5MuLs+G9pMq1NLAUnvslg1YbW2w+1nKRyUZ64gDniDKAQ2P3fYsRD4d4+Kgk04adQIQSmnVgPdqluiE0R1QDGFuRGOPAVfd8TDrkbFmkDB54dhURWsfrcVVAXBzlHw/mH4c5BiyWZiUK2FHSwL8tSNJAo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730971225; c=relaxed/simple; bh=qcVQKBxN0F6baKWfAFHd5n9gYoMcBRYNhU4G/s72Xrs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WFLWj6cSS3QyO89VCzmdChx1Oly3/6kMA6hn52utvKJZbABUJ2f5uqi48rhfsbkn8q3gTDoCHPRZbCRmSGBJWpphAzC5jcnHvSNz2UUj1ZepX92Z9EETiLA3x55iD9j/wPnm+/pAOYgPeYQKpspR7asjmDAqArWCNf7LRzGGaO4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=k6/3aCrL; arc=none smtp.client-ip=209.85.167.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="k6/3aCrL" Received: by mail-lf1-f47.google.com with SMTP id 2adb3069b0e04-539ee1acb86so708681e87.0; Thu, 07 Nov 2024 01:20:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730971222; x=1731576022; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=QK1XdOVmAUkQ2fTe+YuCgvHp77+BHuIFQXUOx8rf0ug=; b=k6/3aCrLJ+HuQLPAzsEfR0aNGKnT1WJxHYTupShUaZyTRcP6HVBhbPf/A68OLXw6cF QxlmLSdM5bVFC45J9VEWSAmY0j2SaEMilKl4TKQhzNBLKeHYp1jEBTh5jeH6Xf6mtPxN V8AtMFlpcfDW15A5MI+xxqm60VAw9LNrvF+VO2nNoVC0B3RAfHiN9jls4E92+3rRGUFD 4Ii4lnaYF0VSHReKsvkrQDnHKWSmbHl9cpXb2f4yPMOy+fdY682rIUTWIFMkDxWIjgw9 5kjswWZhgWr1x8peBIthjG/IzcySxLVsBGLDuHWeUYtIYTgjllN45LO1vdJhAtBsPyvf dlmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730971222; x=1731576022; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QK1XdOVmAUkQ2fTe+YuCgvHp77+BHuIFQXUOx8rf0ug=; b=jELwNx3ZjtSwHUU7LMBvEwPlalpct9qgXoA7pbyvkdY+1zisBC8OL2aNMd0pCKQ1NX JjghbXwGvFQaUxvs6gfH/+GSfuOogrPZnSMyAtHgT5+6daB1XUW6kx7jpt16y3AyyX00 wx8pHUyYO/ypNmtcjwMValrx7D9qXBmyg9U5DlBNYt+5/tulIMvPX0tj83gDnP8xF/fX fLB/fiUMovC4wzZcprw51GhLGI0e6xVjYTOxoXj2mFWWLK0MxiJvLAkF+Qnh+bVvqG7f 6hPlSMhH1o/ts6ChnLcdbwKOdUcY0Fn5SU+L2Bpyxe8oX+frMuD3AZF4+mXOePiSzKYX ArRg== X-Forwarded-Encrypted: i=1; AJvYcCUFKElHX2cC+y9zr/jMpUJi4qq7fGsfGlF3xcVVF0iSgoLw6omx57esexAMTRZEwyCrA7pNJ6uM26qc@vger.kernel.org, AJvYcCVFGeqGM7MkLbLSCwhKFeVQsnEcFJgjQXTQN0j5wK+AynrbDG0PiQQIHwoWPnIQ99lN5FH50OhrwQkD02P6@vger.kernel.org X-Gm-Message-State: AOJu0YwOs9IQc0FCKlX+h2B1lKCxLCUhJFzRUywYieEQW4Nb5AUUqOgA U9NxRC+0Vul8lXTpXLDL4ZfRunYxSUc3JLq+12PPC7hF51+Se0HoxfZajyrd X-Google-Smtp-Source: AGHT+IEEQWtPYTw/UAfp3xustQoSg0MSdAth22EFd3NaHj0cAEhDqoMH8t3n/7QUg9JZseSLN9VyCA== X-Received: by 2002:a05:6512:3caa:b0:539:f827:2fbc with SMTP id 2adb3069b0e04-53d65df7c5cmr11667995e87.26.1730971221265; Thu, 07 Nov 2024 01:20:21 -0800 (PST) Received: from [192.168.1.11] (83-233-6-197.cust.bredband2.com. [83.233.6.197]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53d826a9b50sm139509e87.182.2024.11.07.01.20.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Nov 2024 01:20:19 -0800 (PST) From: Marcus Folkesson Date: Thu, 07 Nov 2024 10:19:54 +0100 Subject: [PATCH v6 2/2] dt-bindings: mtd: davinci: convert to yaml Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241107-ondie-v6-2-f70905dc12bf@gmail.com> References: <20241107-ondie-v6-0-f70905dc12bf@gmail.com> In-Reply-To: <20241107-ondie-v6-0-f70905dc12bf@gmail.com> To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Marcus Folkesson X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7516; i=marcus.folkesson@gmail.com; h=from:subject:message-id; bh=qcVQKBxN0F6baKWfAFHd5n9gYoMcBRYNhU4G/s72Xrs=; b=owEBbQKS/ZANAwAIAYiATm9ZXVIyAcsmYgBnLIZG1343w/337NBzc1ONG4UdeNT8FL9DnYAzN CjKDumVhAGJAjMEAAEIAB0WIQQFUaLotmy1TWTBLGWIgE5vWV1SMgUCZyyGRgAKCRCIgE5vWV1S MgqDD/wIYhvhmKLHzq4wjW0lIg4Dgrg/017ks9Vj+CkmlPtLeN4QNsQPGrJ1K1MlAQG22+MfUIA dC8iC+khIWro6pEJBKvPi8TBQviJKYHft2cGqQJ+e2k+I4InhQ4lnPtxzu1WV+9cYTXSulTBFZW StwzddKVQT8JeBN+Vv9IEIruj1jMzVSV2DSsshQLdE3KhWCxJo43urvBLhSKv2vSqz7TjRXu9Wx yvpw4FSTsQCEB/D2KPTUIkLenPoYv2LerenZkpDQ8N6SMgs46K0AjdMSglmYX6MlQ6c4e1P/mC5 MoDzIO87sW+bNHEaT8uFb7pc/z/5Sah7bjbryiLZ01LFuIvBHaiYmLpJ6OSRxHmLO9h7+OGpNLg 5ievr0gOpdaEoZz7teL3ig/730QUPr8IEgb7ZVCBQ7JxTHB3MkDlItPg0vln2wUWqvlWkaY6UTu eJ4MN9OC5Blna3of1UZ0FYl0gHmRKMA9KwPbvE+KL8tb3X1lQxyme3DJ1hcsQVm9/BmAi2RGAu7 2Q/EV+KUVxY+o485DhPNPyvBQ6ydB7cChgYPOozsUTiSTuOiwRoK2u49Exq1mQEZwBhoWLB0tzr dE32FX15AkThDpDdihFn+xzvsvnkvTmjzsMe5zQE71HK7FZyDGRaiGE7ExjNq/+G0YvfyC/OrF0 1/ZdcGLXku550vA== X-Developer-Key: i=marcus.folkesson@gmail.com; a=openpgp; fpr=AB91D46C7E0F6E6FB2AB640EC0FE25D598F6C127 Convert the bindings to yaml format. Signed-off-by: Marcus Folkesson --- .../devicetree/bindings/mtd/davinci-nand.txt | 94 --------------- .../devicetree/bindings/mtd/ti,davinci-nand.yaml | 134 +++++++++++++++++= ++++ 2 files changed, 134 insertions(+), 94 deletions(-) diff --git a/Documentation/devicetree/bindings/mtd/davinci-nand.txt b/Docum= entation/devicetree/bindings/mtd/davinci-nand.txt deleted file mode 100644 index eb8e2ff4dbd2901b3c396f2e66c1f590a32dcf67..000000000000000000000000000= 0000000000000 --- a/Documentation/devicetree/bindings/mtd/davinci-nand.txt +++ /dev/null @@ -1,94 +0,0 @@ -Device tree bindings for Texas instruments Davinci/Keystone NAND controller - -This file provides information, what the device node for the davinci/keyst= one -NAND interface contains. - -Documentation: -Davinci DM646x - https://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf -Kestone - https://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf - -Required properties: - -- compatible: "ti,davinci-nand" - "ti,keystone-nand" - -- reg: Contains 2 offset/length values: - - offset and length for the access window. - - offset and length for accessing the AEMIF - control registers. - -- ti,davinci-chipselect: number of chipselect. Indicates on the - davinci_nand driver which chipselect is used - for accessing the nand. - Can be in the range [0-3]. - -Recommended properties : - -- ti,davinci-mask-ale: mask for ALE. Needed for executing address - phase. These offset will be added to the base - address for the chip select space the NAND Flash - device is connected to. - If not set equal to 0x08. - -- ti,davinci-mask-cle: mask for CLE. Needed for executing command - phase. These offset will be added to the base - address for the chip select space the NAND Flash - device is connected to. - If not set equal to 0x10. - -- ti,davinci-mask-chipsel: mask for chipselect address. Needed to mask - addresses for given chipselect. - -- nand-ecc-mode: operation mode of the NAND ecc mode. ECC mode - valid values for davinci driver: - - "none" - - "soft" - - "hw" - -- ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4. - -- nand-bus-width: buswidth 8 or 16. If not present 8. - -- nand-on-flash-bbt: use flash based bad block table support. OOB - identifier is saved in OOB area. If not present - false. - -Deprecated properties: - -- ti,davinci-ecc-mode: operation mode of the NAND ecc mode. ECC mode - valid values for davinci driver: - - "none" - - "soft" - - "hw" - -- ti,davinci-nand-buswidth: buswidth 8 or 16. If not present 8. - -- ti,davinci-nand-use-bbt: use flash based bad block table support. OOB - identifier is saved in OOB area. If not present - false. - -Nand device bindings may contain additional sub-nodes describing partition= s of -the address space. See mtd.yaml for more detail. The NAND Flash timing -values must be programmed in the chip select=E2=80=99s node of AEMIF -memory-controller (see Documentation/devicetree/bindings/memory-controller= s/ -davinci-aemif.txt). - -Example(da850 EVM ): - -nand_cs3@62000000 { - compatible =3D "ti,davinci-nand"; - reg =3D <0x62000000 0x807ff - 0x68000000 0x8000>; - ti,davinci-chipselect =3D <1>; - ti,davinci-mask-ale =3D <0>; - ti,davinci-mask-cle =3D <0>; - ti,davinci-mask-chipsel =3D <0>; - nand-ecc-mode =3D "hw"; - ti,davinci-ecc-bits =3D <4>; - nand-on-flash-bbt; - - partition@180000 { - label =3D "ubifs"; - reg =3D <0x180000 0x7e80000>; - }; -}; diff --git a/Documentation/devicetree/bindings/mtd/ti,davinci-nand.yaml b/D= ocumentation/devicetree/bindings/mtd/ti,davinci-nand.yaml new file mode 100644 index 0000000000000000000000000000000000000000..fffdaa9bf85ac2ffb1b177bdc69= 3c995d2a8ea20 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/ti,davinci-nand.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/ti,davinci-nand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI DaVinci NAND controller + +maintainers: + - Marcus Folkesson + +allOf: + - $ref: nand-controller.yaml + +properties: + compatible: + enum: + - ti,davinci-nand + - ti,keystone-nand + + reg: + items: + - description: + Access window. + - description: + AEMIF control registers + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + partitions: + $ref: /schemas/mtd/partitions/partitions.yaml + + ti,davinci-chipselect: + description: + Number of chipselect. Indicate on the davinci_nand driver which + chipselect is used for accessing the nand. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + ti,davinci-mask-ale: + description: + Mask for ALE. Needed for executing address phase. These offset will = be + added to the base address for the chip select space the NAND Flash + device is connected to. + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0x08 + + ti,davinci-mask-cle: + description: + Mask for CLE. Needed for executing command phase. These offset will = be + added to the base address for the chip select space the NAND Flash d= evice + is connected to. + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0x10 + + ti,davinci-mask-chipsel: + description: + Mask for chipselect address. Needed to mask addresses for given + chipselect. + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + + ti,davinci-ecc-bits: + description: Used ECC bits. + enum: [1, 4] + + ti,davinci-ecc-mode: + description: Operation mode of the NAND ECC mode. + $ref: /schemas/types.yaml#/definitions/string + enum: [none, soft, hw, on-die] + deprecated: true + + ti,davinci-nand-buswidth: + description: Bus width to the NAND chip + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [8, 16] + default: 8 + deprecated: true + + ti,davinci-nand-use-bbt: + type: boolean + description: + Use flash based bad block table support. OOB identifier is saved in = OOB + area. + deprecated: true + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ti,davinci-chipselect + +unevaluatedProperties: false + +examples: + - | + bus { + #address-cells =3D <2>; + #size-cells =3D <1>; + + nand-controller@2000000,0 { + compatible =3D "ti,davinci-nand"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0 0x02000000 0x02000000 + 1 0x00000000 0x00008000>; + + ti,davinci-chipselect =3D <1>; + ti,davinci-mask-ale =3D <0>; + ti,davinci-mask-cle =3D <0>; + ti,davinci-mask-chipsel =3D <0>; + + ti,davinci-nand-buswidth =3D <16>; + ti,davinci-ecc-mode =3D "hw"; + ti,davinci-ecc-bits =3D <4>; + ti,davinci-nand-use-bbt; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "u-boot env"; + reg =3D <0 0x020000>; + }; + }; + }; + }; --=20 2.47.0