From nobody Sun Nov 24 01:31:42 2024 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 30610212F0E; Thu, 7 Nov 2024 17:03:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730998983; cv=none; b=P8XwAK9iiKf8L6gJpWor4Y3s5Ib2Pp1wwZmgj6R5OYlGvF9Q0qd4WnxeZXnhP6/C2Bpwf126zOwdzIxPlFyIT3X4ogWqinhXu54MRN8JaZUAwdRRGzW9ESxCQoRuh0iskqJSliO5DpCztNG8JtDdk4sfsFPt6JuTQqQ+WLHoUvI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730998983; c=relaxed/simple; bh=LkaCWW3zjWDLBVsp88RQzozjsFyLCaGPD6+VtFvGVDI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SsfJG0J7woHy7/bcXQ1L2vrG5c4YDvCSSjGNANv8pO/ZX1TL0LF/i9/GhPAyKNxP43Q8nAYocEXlo23WBe16BiH0kk8u3BAlj4ja19is5nEm4mme5S37w0RBOmSL+KfmZk6bGWxZAKYzKIbzZNpLejCyfQzYUklChjJMrUHBhoY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org; spf=pass smtp.mailfrom=mainlining.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=vQLC87CU; arc=none smtp.client-ip=5.75.144.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="vQLC87CU" Received: from [192.168.118.162] (254C2715.nat.pool.telekom.hu [37.76.39.21]) by mail.mainlining.org (Postfix) with ESMTPSA id 3B27EE45C4; Thu, 7 Nov 2024 17:02:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mainlining.org; s=psm; t=1730998973; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Ekjj10oUzQBlH9L8yVZcgYXaoycw+VSDrJGKyzti4PA=; b=vQLC87CU6N5c7bhxWXElqejUGzteRP/76CMzXnY8IRUF6lbVD6+p363GTxzKGCnnkDFfQ7 qcd25bsIvn8+0wz6MQ2v2wiRP1AmCyjGyvn5dseM9TyOr/Y6D0BgSq+46HRZ6JYF9t0IpU 9RsKre49xV4qU2mtgyOlAGPxpkYvt5YFe78oL+hfeu4MN1hQLDVlj9NfgBq+JUiabbKMXf t0r+w7kt+zQ5vmprD5bZ5u0beourNi/FAjjuPPBJZ6z1J4gZhEiqqi6lcxA51XAg7oTjir /TjY0FXG2em4lS4sS8JLrmyh1VXtBt+u73+YYTqiTja7i/BvHcFPOggkseHiUQ== From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Thu, 07 Nov 2024 18:02:42 +0100 Subject: [PATCH v3 01/14] dt-bindings: pinctrl: qcom,pmic-gpio: Add PM8937 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241107-msm8917-v3-1-6ddc5acd978b@mainlining.org> References: <20241107-msm8917-v3-0-6ddc5acd978b@mainlining.org> In-Reply-To: <20241107-msm8917-v3-0-6ddc5acd978b@mainlining.org> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Lee Jones , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Joerg Roedel , Will Deacon , Robin Murphy , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, iommu@lists.linux.dev, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1730998970; l=1652; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=LkaCWW3zjWDLBVsp88RQzozjsFyLCaGPD6+VtFvGVDI=; b=IfpEWFE5Bv23ghs5uEmHFKDTzOV98RKqVrRW9GAj+hGddknVQoW7SpsBR3S0gRJ9t4ZiW792h R5TVIzSlFjCDyqHHAw+eeUqBto+iw8yJXvrMrrhvcRVfGNRCI01DoSW X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= Document the 8 GPIOs found on PM8937. It has holes on 3,4 and 6 pins. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml = b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml index c1b799167d81b0b4e1edff6a6fce557fa88fd1ea..055cea5452eb62ab6e251a3a919= 3d1e5da293ccb 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml @@ -48,6 +48,7 @@ properties: - qcom,pm8916-gpio - qcom,pm8917-gpio - qcom,pm8921-gpio + - qcom,pm8937-gpio - qcom,pm8941-gpio - qcom,pm8950-gpio - qcom,pm8953-gpio @@ -184,6 +185,7 @@ allOf: - qcom,pm8226-gpio - qcom,pm8350b-gpio - qcom,pm8550ve-gpio + - qcom,pm8937-gpio - qcom,pm8950-gpio - qcom,pm8953-gpio - qcom,pmi632-gpio @@ -468,6 +470,7 @@ $defs: - gpio1-gpio6 for pm8550vs - gpio1-gpio38 for pm8917 - gpio1-gpio44 for pm8921 + - gpio1-gpio8 for pm8937 (hole on gpio3, gpio4 and gpio6) - gpio1-gpio36 for pm8941 - gpio1-gpio8 for pm8950 (hole on gpio3) - gpio1-gpio8 for pm8953 (hole on gpio3 and gpio6) --=20 2.47.0 From nobody Sun Nov 24 01:31:42 2024 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5DD12170BD; Thu, 7 Nov 2024 17:03:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730998984; cv=none; b=o7sdWdBlwaCLiJ0O71kcQ8DjbXXX7vuslUtu2MQy/COtgc9eh2KW5NPyWP7QipHZ/uI1ZfZBjKC+QmrXbjpuCGM/qtEOXBHsSnjhFUlWpbqgWNF0elW08t0YkYOLZMm0QW8ZB+GzX7g7I1KdXrP/QqstISR9GqmtGFO9o/3d5+Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730998984; c=relaxed/simple; bh=4/3yIerMwWJrV0PgQtDH3R5bMiqTFPqF4LbIqu7XNtA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qTMCgln4Ldd/IOAamYQhVtzbzKS3G6wccnZ4geENmXKhg+At4VisRSs51kEMajFevy4RKoaLR0MepfkZVf83C6mtNmUh/YDOi+za0FK4qjIf8EM2r+IbEuJOmj/5EV9v+wkwBghfz3e8JZqxEYcAJGzaoaa+QIz9IEzygF2JMZY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org; spf=pass smtp.mailfrom=mainlining.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=b9HYVxWD; arc=none smtp.client-ip=5.75.144.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="b9HYVxWD" Received: from [192.168.118.162] (254C2715.nat.pool.telekom.hu [37.76.39.21]) by mail.mainlining.org (Postfix) with ESMTPSA id A0E35E45C5; Thu, 7 Nov 2024 17:02:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mainlining.org; s=psm; t=1730998974; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1cSXtHNT4k7URrcC7KCf7aIwX75O9SVcuiydlyG6cN4=; b=b9HYVxWDznwYuZi4XF9UWzgo7T2G7AbHKxNGyzA9bg4KCuEnHKCOS7uU2NZHyAkNJpI7K9 pIOnXoN9usroW0HzYRkB1gQocw2qm/lg8FZ/CBRvn0OMbPvvVU0qJMmjx1MWJmUefANMFd H5Lnt6mY5neGaFD4YoV7OB8RBhHxivLJaz27fW2p+YFQUIUPwGxR5pxgnhGP4b7gYDh8JI Z9NhkQHjFvW0jxkztOwvGEUg3YNOEIVv8Fdc0D77YDk73wobzyg/cbX3TIcAZsFDOxVkd6 EB4K1h7e1ekgygN/D02H66UjG6LNB8XecVyKaeeokqqCX7Gc4RAsPWJMP+/cog== From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Thu, 07 Nov 2024 18:02:43 +0100 Subject: [PATCH v3 02/14] pinctrl: qcom-pmic-gpio: Add support for PM8937 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241107-msm8917-v3-2-6ddc5acd978b@mainlining.org> References: <20241107-msm8917-v3-0-6ddc5acd978b@mainlining.org> In-Reply-To: <20241107-msm8917-v3-0-6ddc5acd978b@mainlining.org> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Lee Jones , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Joerg Roedel , Will Deacon , Robin Murphy , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, iommu@lists.linux.dev, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1730998970; l=1136; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=4/3yIerMwWJrV0PgQtDH3R5bMiqTFPqF4LbIqu7XNtA=; b=hYAUT/svKEE3ITQ9nUpOqCrhVmG7XwioFmlK4nUk5gjlSWoqKelQEC7PpLxYRnfYMmlu6g2Gn rIR00t+BMMeAKVNlEvTNII2x6kXLd/izhXFVriudpGrFhaqXX1xGY/B X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= PM8937 has 8 GPIO-s with holes on GPIO3, GPIO4 and GPIO6. Reviewed-by: Dmitry Baryshkov Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qco= m/pinctrl-spmi-gpio.c index d42c812a89a848b2f64c84da1546f48e9e899d4d..a8a154a2ac94e3fc94d2da17108= 67a6f0a7ae11e 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -1226,6 +1226,8 @@ static const struct of_device_id pmic_gpio_of_match[]= =3D { { .compatible =3D "qcom,pm8550ve-gpio", .data =3D (void *) 8 }, { .compatible =3D "qcom,pm8550vs-gpio", .data =3D (void *) 6 }, { .compatible =3D "qcom,pm8916-gpio", .data =3D (void *) 4 }, + /* pm8937 has 8 GPIOs with holes on 3, 4 and 6 */ + { .compatible =3D "qcom,pm8937-gpio", .data =3D (void *) 8 }, { .compatible =3D "qcom,pm8941-gpio", .data =3D (void *) 36 }, /* pm8950 has 8 GPIOs with holes on 3 */ { .compatible =3D "qcom,pm8950-gpio", .data =3D (void *) 8 }, --=20 2.47.0 From nobody Sun Nov 24 01:31:42 2024 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29936217329; Thu, 7 Nov 2024 17:03:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730998985; cv=none; b=VPADbFJLND/7Oiij6mSI++PqGrFQWjbUhvlOJYkLqekw5joHe64rWUG/2n5x3iX0qX4Kn7P1/SiQJYq2ZEtUwkuC/pPxxIg9STAk4R4M8liQN0Hr5NvvO4ABi3vdrCXoXV0xizhh3StuObrlPBFdbKMwxquT0uW8AZc5i1TUfy8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730998985; c=relaxed/simple; bh=A0fmQDK8m7oxJnEMI+GXPI0MVrZif3Z38lQBRjITpDA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WfyC+geR28BCYxfDQcx3MTAmPrZVz5QayagSrFPRNUbYgBexqzHWQQq24wS73Q7U1Zjb/85LXO51SUeGw0b3VM970yQlsspojRf9DY2UDbBSgTJiyH86Kp+OkedbqdVd5Jc9PlEYg1Bu7L4wFbVww9YbsGRBqd/sOvAoi7dc3sU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org; spf=pass smtp.mailfrom=mainlining.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=fr4rBFPJ; arc=none smtp.client-ip=5.75.144.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="fr4rBFPJ" Received: from [192.168.118.162] (254C2715.nat.pool.telekom.hu [37.76.39.21]) by mail.mainlining.org (Postfix) with ESMTPSA id 5A980E45C6; Thu, 7 Nov 2024 17:02:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mainlining.org; s=psm; t=1730998976; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Ze6/FwJGlwoZIH5QX0UZSFz6K9jP+T7IzTY3dKemhXQ=; b=fr4rBFPJyaJ39C6eKeHzqJYWQZcg1QcvIwIIJ+xPoRLXwsPk4wqbq6uYBZnadM50yyzvSA PebDREFNaKPp/T7Fw0aQBqJin30nnE2lwcNF58eA4ICXk0/Vsp95cNolPRPTTveLO3foZm oKgprRA1xqjhQ8amfrXZkEc7L7r8jYM8oMC0e1NRGIPVC/s8GiJzIYiTohpH0473pF0SYm 6m8mn7P20jD4nny4dnjcPK9spuU6X0ZGfMx9ufht/i3v07F1VjSbYMZibg1mEhrmBkEjBG dz3XFVoIsdKwcqY9lyJ9EzrGh4RnbHJdzIH/uwTtzuaCbUEcdKqv2s3ibjn9Xg== From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Thu, 07 Nov 2024 18:02:44 +0100 Subject: [PATCH v3 03/14] dt-bindings: pinctrl: qcom,pmic-mpp: Add PM8937 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241107-msm8917-v3-3-6ddc5acd978b@mainlining.org> References: <20241107-msm8917-v3-0-6ddc5acd978b@mainlining.org> In-Reply-To: <20241107-msm8917-v3-0-6ddc5acd978b@mainlining.org> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Lee Jones , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Joerg Roedel , Will Deacon , Robin Murphy , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, iommu@lists.linux.dev, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1730998970; l=1273; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=A0fmQDK8m7oxJnEMI+GXPI0MVrZif3Z38lQBRjITpDA=; b=hhnjY8odk06rK1S61Z5megT38z31/ktCL9JcthBjdVSCIwiwWoJN6K/+R59Z5o8wOslRgsYp6 se+VChFqUY2AOV4i+2DeRZrIqjV3o85b0lr7jln2J63M5LLJxAHATNz X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= Document the Device Tree binding for PM8937 MPPs. Acked-by: Krzysztof Kozlowski Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml b= /Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml index 43146709e2044d9dead08a6786b98672ef766629..9364ae05f3e68f3a2f4dd78ba3c= 0f94b3ccc3c51 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml @@ -22,6 +22,7 @@ properties: - qcom,pm8226-mpp - qcom,pm8841-mpp - qcom,pm8916-mpp + - qcom,pm8937-mpp - qcom,pm8941-mpp - qcom,pm8950-mpp - qcom,pmi8950-mpp @@ -92,6 +93,7 @@ $defs: this subnode. Valid pins are - mpp1-mpp4 for pm8841 - mpp1-mpp4 for pm8916 + - mpp1-mpp4 for pm8937 - mpp1-mpp8 for pm8941 - mpp1-mpp4 for pm8950 - mpp1-mpp4 for pmi8950 --=20 2.47.0 From nobody Sun Nov 24 01:31:42 2024 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4247321315B; Thu, 7 Nov 2024 17:03:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730998981; cv=none; b=MPy9HeVkgSefNB8TfFUFvgglslzgZS5/dEo/bb28Yvo/mlJ0u1lDqGJNbUWHVvI0yuDWxltyNFXi4BfO/CmBIF6Ui7Pp9NR7X1s9LTsBJ4IPaDdk6BlL2mrzvlDcUFh/NN0nfpHsZwJVMhJppXkwkdSZKVHn2V2K/61PM1nFooc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730998981; c=relaxed/simple; bh=ZUgeto9/E87fDiZJrXBC+X56+By41ZSfPN7XvT0Ux6Y=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RN8oyfZ7h8Z5EG7wURW9qHq7KQwUoGflnydl1V5ZhtAnfLlAdnqhTqnVESGI2JHrkMq9b936ndjW5blaO9UDpCRNYxvjpPHxM6e0/+/jB0QzI7ZmXM2lcu3KFu5mTRr8zjEpDvzZRSY1fEB/feg7oxoUV94A3byP+1VDiES4Tfw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org; spf=pass smtp.mailfrom=mainlining.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=VD0iOsfC; arc=none smtp.client-ip=5.75.144.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="VD0iOsfC" Received: from [192.168.118.162] (254C2715.nat.pool.telekom.hu [37.76.39.21]) by mail.mainlining.org (Postfix) with ESMTPSA id DBFEEE45C7; Thu, 7 Nov 2024 17:02:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mainlining.org; s=psm; t=1730998977; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=UZFwbFxl+fO/yfXuNk3d5tUxPWCdUEMpagrp1Rl+Vgc=; b=VD0iOsfCy8Wuc3BP5weRCHJFY6ApGhkVDRfufi0V/mSPibkk//2bpdg/nz9Isxuew4uMvs Dhw6aLuACFw8WjeRThxVcCWjpk+43CgNbQ3ri4A7W2m+AkGKlpsVJMuNpf2EWa3NaMUaWh 7U9byhps8r/uP1NLk+LA2Qkp35FxVMi08rHmUkDdeLWiPik+CQP4yc5Uzu1LgvmqKHKAzh lQLA6iJsVTFjg/Y4YF9qlatE5qw5CsQMEUWakjYm4kLSCk5WS9+eUSusVb/jw5HBGcWB7a ZLogLf+8lJn6JbMFXNsZ+szXIZzPpbJJTl84S1u6JPihvam7w2q7WvDaa0HL1g== From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Thu, 07 Nov 2024 18:02:45 +0100 Subject: [PATCH v3 04/14] pinctrl: qcom: spmi-mpp: Add PM8937 compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241107-msm8917-v3-4-6ddc5acd978b@mainlining.org> References: <20241107-msm8917-v3-0-6ddc5acd978b@mainlining.org> In-Reply-To: <20241107-msm8917-v3-0-6ddc5acd978b@mainlining.org> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Lee Jones , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Joerg Roedel , Will Deacon , Robin Murphy , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, iommu@lists.linux.dev, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1730998970; l=1084; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=ZUgeto9/E87fDiZJrXBC+X56+By41ZSfPN7XvT0Ux6Y=; b=2VfRXLWfHUaF4RbGeGO0kiQ1+sIuXxrW8PbGA4tatq9Kkngy+a4GSFT+Yl0BB40+DEIczuT+y Hb7k0AKJ2JeCnmlYeXOKE6ZlXphGQ5PeNPdnPINkPSZ2XnfOdvyOf7X X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= The PM8937 provides 4 MPPs. Add a compatible to support them. Reviewed-by: Dmitry Baryshkov Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- drivers/pinctrl/qcom/pinctrl-spmi-mpp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom= /pinctrl-spmi-mpp.c index b5b3ac82f030b55f9e199bb4265c770cfde4a81a..84de584cf7ebbd35dd3e7aa89d4= b971645b02f82 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c @@ -983,6 +983,7 @@ static const struct of_device_id pmic_mpp_of_match[] = =3D { { .compatible =3D "qcom,pm8226-mpp", .data =3D (void *) 8 }, { .compatible =3D "qcom,pm8841-mpp", .data =3D (void *) 4 }, { .compatible =3D "qcom,pm8916-mpp", .data =3D (void *) 4 }, + { .compatible =3D "qcom,pm8937-mpp", .data =3D (void *) 4 }, { .compatible =3D "qcom,pm8941-mpp", .data =3D (void *) 8 }, { .compatible =3D "qcom,pm8950-mpp", .data =3D (void *) 4 }, { .compatible =3D "qcom,pmi8950-mpp", .data =3D (void *) 4 }, --=20 2.47.0 From nobody Sun Nov 24 01:31:42 2024 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CEA5217317; Thu, 7 Nov 2024 17:03:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730998985; cv=none; b=leiV5fquwz6gCpf+rhN9Qq0KcOl6Ex55hnVqpy4ZDycn0TDMKyQxSH6GXzw+Dn4DzrujmYwTvdyddOs5ViG5bGArKxiTg085trfJYNKHtHzWv4bPLax/B516MJMX83xTttaLrlIXg4iCxAEWDqvjSC88rSzbcnCZQnR94yiQonw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730998985; c=relaxed/simple; bh=UjL9JXQQ119tJGWqiITE11zteO0vgLUycgawyHA9VGo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NXb7atjs6rqw+VI5GT3QHzV19OQEQOkRzvUtQk6YGSANoFP00ysk53GbLA5HIUnHhsgw0PvOU7GAD9Y9KxTlOoayIwc8hyuDjWgQ0zFtITZS+jGVNbsHKx2ZqG3QEFo5C8DQKuyvUVrInCVt3kapbh9+gkOYkX2CTeUCpT8/VVc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org; spf=pass smtp.mailfrom=mainlining.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=vVo8kVu8; arc=none smtp.client-ip=5.75.144.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="vVo8kVu8" Received: from [192.168.118.162] (254C2715.nat.pool.telekom.hu [37.76.39.21]) by mail.mainlining.org (Postfix) with ESMTPSA id B7813E45C8; Thu, 7 Nov 2024 17:02:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mainlining.org; s=psm; t=1730998979; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=4O09ZiSIv+mEo/bJ7pidfgYhpVOBMlebhOJxZ0ds7BQ=; b=vVo8kVu8MUZBVuAsghwWSbG+POUNFwXrxb7Zp2LLO7u1yhGupwmtlaDrBhB30XAahVWAQc ZqDagTM5w+Ph+HdWBp0c4MCZPmXwg3J5PO0NlmN7WZp2/88apLxcLy5Cj9lQOwSK64F71o v4YQBDsnfBNvbARgOCMBd4DYAxxigm0o5Jz4Ker1X4dUCZKMoz8ktePMDE97jITNaWA7CR dOhLUQSlsWSwYYdBx7zisa1CSfV55wCYjDQq5r9k6nuf0Y3r7Mdf5eK2195agRijxPwwZF sRB32mizgzfSf0Jie03wDu+dl9/j+AX5snPosFLXlXVRJwlROEsVRkSLJkqsOQ== From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Thu, 07 Nov 2024 18:02:46 +0100 Subject: [PATCH v3 05/14] arm64: dts: qcom: Add PM8937 PMIC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241107-msm8917-v3-5-6ddc5acd978b@mainlining.org> References: <20241107-msm8917-v3-0-6ddc5acd978b@mainlining.org> In-Reply-To: <20241107-msm8917-v3-0-6ddc5acd978b@mainlining.org> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Lee Jones , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Joerg Roedel , Will Deacon , Robin Murphy , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, iommu@lists.linux.dev, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= , Dang Huynh , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1730998970; l=4120; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=7USdc5qvUHeHbgBI+sq8tO9MUWKj31JWpFnlIkEMcdA=; b=GxMY+P8CVQD5vKlozCHv4FlWLeIesY5dIyLl4+jFzk4ZvaxQLOwgY4/ToIgeWTUCxPV0OdYSe JoO4XoTW88eApAYENBZQ0ajNqn0igVjDBL+8P0RuGCN8WY+rCXTHjJ/ X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= From: Dang Huynh The PM8937 features integrated peripherals like ADC, GPIO controller, MPPs, PON keys and others. Add the device tree so that any boards with this PMIC can use it. Reviewed-by: Dmitry Baryshkov Signed-off-by: Dang Huynh Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- arch/arm64/boot/dts/qcom/pm8937.dtsi | 152 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 152 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8937.dtsi b/arch/arm64/boot/dts/qco= m/pm8937.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..38421e89e556eaaf318118175e8= e2036029311a9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8937.dtsi @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Dang Huynh + */ + +#include +#include +#include +#include +#include + +/ { + thermal-zones { + pm8937-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&pm8937_temp>; + + trips { + trip0 { + temperature =3D <105000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "hot"; + }; + + trip2 { + temperature =3D <145000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + }; +}; + +&spmi_bus { + pmic@0 { + compatible =3D "qcom,pm8937", "qcom,spmi-pmic"; + reg =3D <0x0 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pon@800 { + compatible =3D "qcom,pm8916-pon"; + reg =3D <0x800>; + mode-bootloader =3D <0x2>; + mode-recovery =3D <0x1>; + + pm8937_pwrkey: pwrkey { + compatible =3D "qcom,pm8941-pwrkey"; + interrupts =3D <0 0x8 0 IRQ_TYPE_EDGE_BOTH>; + debounce =3D <15625>; + bias-pull-up; + linux,code =3D ; + }; + + pm8937_resin: resin { + compatible =3D "qcom,pm8941-resin"; + interrupts =3D <0 0x8 1 IRQ_TYPE_EDGE_BOTH>; + debounce =3D <15625>; + bias-pull-up; + status =3D "disabled"; + }; + }; + + pm8937_gpios: gpio@c000 { + compatible =3D "qcom,pm8937-gpio", "qcom,spmi-gpio"; + reg =3D <0xc000>; + gpio-controller; + gpio-ranges =3D <&pm8937_gpios 0 0 8>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + pm8937_mpps: mpps@a000 { + compatible =3D "qcom,pm8937-mpp", "qcom,spmi-mpp"; + reg =3D <0xa000>; + gpio-controller; + gpio-ranges =3D <&pm8937_mpps 0 0 4>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + pm8937_temp: temp-alarm@2400 { + compatible =3D "qcom,spmi-temp-alarm"; + reg =3D <0x2400>; + interrupts =3D <0 0x24 0 IRQ_TYPE_EDGE_RISING>; + io-channels =3D <&pm8937_vadc VADC_DIE_TEMP>; + io-channel-names =3D "thermal"; + #thermal-sensor-cells =3D <0>; + }; + + pm8937_vadc: adc@3100 { + compatible =3D "qcom,spmi-vadc"; + reg =3D <0x3100>; + interrupts =3D <0 0x31 0 IRQ_TYPE_EDGE_RISING>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #io-channel-cells =3D <1>; + + channel@8 { + reg =3D ; + }; + + channel@9 { + reg =3D ; + }; + + channel@a { + reg =3D ; + }; + + channel@c { + reg =3D ; + }; + + channel@e { + reg =3D ; + }; + + channel@f { + reg =3D ; + }; + }; + + rtc@6000 { + compatible =3D "qcom,pm8941-rtc"; + reg =3D <0x6000>, <0x6100>; + reg-names =3D "rtc", "alarm"; + interrupts =3D <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; + }; + }; + + pmic@1 { + compatible =3D "qcom,pm8937", "qcom,spmi-pmic"; + reg =3D <0x1 SPMI_USID>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pm8937_spmi_regulators: regulators { + compatible =3D "qcom,pm8937-regulators"; + }; + }; +}; --=20 2.47.0 From nobody Sun Nov 24 01:31:42 2024 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59A0921730C; Thu, 7 Nov 2024 17:03:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730998985; cv=none; b=AewMwhctwWTk0sJuFTltbHpn3tL/0sOpFX/Eui94BiZ+/ikPU1lcjhtS8U+jRVeSV0zQGEw8wqUGuEa3JfXKorCZST1ppQyAKbu7GSWT/5eAxkEcFU9kZ+HoK1B6Xch/JEqB65s0vZlaM37lxotgdTK9z/mHfu4uweD+Gens+Kg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Thu, 7 Nov 2024 17:03:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mainlining.org; s=psm; t=1730998981; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=KRS7V3ZOvu7gFf33oE9QkvuDo5RSW5nvjApdzZbQQmc=; b=nhg9o851vlBFSki/d+uLkFtAkduGKmJgu2TaJ03qE9kXLlSlbnifNEtjs3vhGyPrfed/qX GVstyVszC5YA38au25ZWvPJi3WBe/2wE93//p9NIp9yXFueWwOZiLMxQUl/MKMFVjzglSS 0FAPtvWMBUVL9Wru9M9E3Rrehc6ZNsNRkKBvcuQLBxsSJuqQISbJSBN4zDln7DbfNY506K 6T61Roicox7AzC0GFnahKMwgWMYy535MKr+LeceY/gFD4do6Xq4YA75pJqwwFmML0+KLo0 q+0zCJCKOFTA0QKYvrVOln8t1punt1cQ61D4nSGDnE5iQ+nGFYqka+e9FL2aQA== From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Thu, 07 Nov 2024 18:02:47 +0100 Subject: [PATCH v3 06/14] dt-bindings: pinctrl: qcom: Add MSM8917 pinctrl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241107-msm8917-v3-6-6ddc5acd978b@mainlining.org> References: <20241107-msm8917-v3-0-6ddc5acd978b@mainlining.org> In-Reply-To: <20241107-msm8917-v3-0-6ddc5acd978b@mainlining.org> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Lee Jones , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Joerg Roedel , Will Deacon , Robin Murphy , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, iommu@lists.linux.dev, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1730998970; l=6583; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=JHx/mJNY/VmzW58rPorCah4CdAs5u7Kb/7+X5nbaHLI=; b=2fP0JVam1p3fctuLzyEqJRJsZfpfyn23m9Kc/XnDS5z+sepPjga5hTETEd3XW9xa1prBPW4uM xjNmOYcGIOMCcrWOPMmMqXOfvqOqvqKtme3cLPFGUfMBwGtChAmtLTP X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= Add device tree bindings documentation for Qualcomm MSM8917 pinctrl driver. Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- .../bindings/pinctrl/qcom,msm8917-pinctrl.yaml | 160 +++++++++++++++++= ++++ 1 file changed, 160 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8917-pinctrl= .yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8917-pinctrl.yaml new file mode 100644 index 0000000000000000000000000000000000000000..48bfb1fda4938d5a0fb33335695= db0fd56152c42 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8917-pinctrl.yaml @@ -0,0 +1,160 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,msm8917-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8917 TLMM pin controller + +maintainers: + - Barnabas Czeman + +description: + Top Level Mode Multiplexer pin controller in Qualcomm MSM8917 SoC. + +properties: + compatible: + const: qcom,msm8917-pinctrl + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 66 + + gpio-line-names: + maxItems: 134 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-msm8917-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-msm8917-tlmm-state" + additionalProperties: false + +$defs: + qcom-msm8917-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configura= tion. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-3])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk, + sdc2_cmd, sdc2_data, qdsd_clk, qdsd_cmd, qdsd_data0, + qdsd_data1, qdsd_data2, qdsd_data3 ] + minItems: 1 + maxItems: 16 + + function: + description: + Specify the alternative function to be configured for the specif= ied + pins. + + enum: [ accel_int, adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1, + atest_char, atest_char0, atest_char1, atest_char2, + atest_char3, atest_combodac_to_gpio_native, + atest_gpsadc_dtest0_native, atest_gpsadc_dtest1_native, + atest_tsens, atest_wlan0, atest_wlan1, audio_ref, + audio_reset, bimc_dte0, bimc_dte1, blsp6_spi, blsp8_spi, + blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5, + blsp_i2c6, blsp_i2c7, blsp_i2c8, blsp_spi1, blsp_spi2, + blsp_spi3, blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, + blsp_spi8, blsp_uart1, blsp_uart2, blsp_uart3, blsp_uart4, + blsp_uart5, blsp_uart6, blsp_uart7, blsp_uart8, cam0_ldo, + cam1_rst, cam1_standby, cam2_rst, cam2_standby, cam_mclk, + cci_async, cci_i2c, cci_timer0, cci_timer1, cdc_pdm0, + codec_int1, codec_int2, codec_mad, coex_uart, cri_trng, + cri_trng0, cri_trng1, dbg_out, dmic0_clk, dmic0_data, + ebi_cdc, ebi_ch0, ext_lpass, forced_usb, fp_gpio, fp_int, + gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b, + gcc_gp3_clk_a, gcc_gp3_clk_b, gcc_plltest, gcc_tlmm, gpio, + gsm0_tx, key_focus, key_snapshot, key_volp, ldo_en, + ldo_update, lpass_slimbus, lpass_slimbus0, lpass_slimbus1, + m_voc, mag_int, mdp_vsync, mipi_dsi0, modem_tsync, nav_pps, + nav_pps_in_a, nav_pps_in_b, nav_tsync, nfc_pwr, ov_ldo, + pa_indicator, pbs0, pbs1, pbs2, pri_mi2s, pri_mi2s_mclk_a, + pri_mi2s_mclk_b, pri_mi2s_ws, prng_rosc, + pwr_crypto_enabled_a, pwr_crypto_enabled_b, + pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_= a, + pwr_nav_enabled_b, qdss_cti_trig_in_a0, qdss_cti_trig_in_a= 1, + qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, + qdss_cti_trig_out_a0, qdss_cti_trig_out_a1, + qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_= a, + qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, + qdss_tracedata_a, qdss_tracedata_b, sd_write, sdcard_det, + sec_mi2s, sec_mi2s_mclk_a, sec_mi2s_mclk_b, sensor_rst, + smb_int, ssbi_wtr1, ts_resout, ts_sample, uim1_clk, + uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data, + uim2_present, uim2_reset, uim_batt, us_emitter, us_euro, + wcss_bt, wcss_fm, wcss_wlan, wcss_wlan0, wcss_wlan1, + wcss_wlan2, webcam_rst, webcam_standby, wsa_io, wsa_irq ] + + required: + - pins + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + tlmm: pinctrl@1000000 { + compatible =3D "qcom,msm8917-pinctrl"; + reg =3D <0x01000000 0x300000>; + interrupts =3D ; + gpio-controller; + gpio-ranges =3D <&tlmm 0 0 134>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + + blsp1-uart2-sleep-state { + pins =3D "gpio4", "gpio5"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-pull-down; + }; + + spi1-default-state { + spi-pins { + pins =3D "gpio0", "gpio1", "gpio3"; + function =3D "blsp_spi1"; + + drive-strength =3D <12>; + bias-disable; + }; + + cs-pins { + pins =3D "gpio2"; + function =3D "gpio"; + + drive-strength =3D <16>; + bias-disable; + output-high; + }; + }; + }; --=20 2.47.0 From nobody Sun Nov 24 01:31:42 2024 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00D8B217479; Thu, 7 Nov 2024 17:03:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; 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dmarc=pass (p=quarantine dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="kS+QYrWt" Received: from [192.168.118.162] (254C2715.nat.pool.telekom.hu [37.76.39.21]) by mail.mainlining.org (Postfix) with ESMTPSA id B7B03E45CA; Thu, 7 Nov 2024 17:03:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mainlining.org; s=psm; t=1730998983; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=oDcbaoWz517RRg3ignuV+h44n0wFAaok3EFDJHyMCgU=; b=kS+QYrWtyBYW2sETvNAB4Tmve0rrYL2uNHGaCFXeFtlIzFsZ6K2YKel8pxFyPR8ARUU6kv pl/4t+Ur/YqD2i6+VbA9ywUdBPIgxLvaxiwilZ2mHovNL/8/7hWegi9bP49L3fSP8ZfwKz aTbxWI6qU0jV4Kyryy3kzki4ctfXVFh/OGWF8FccnFzN5leoBnAFs5SvaqQjE5cpmYc6jX 7wGyo3P3MvwI8eIuYg+31N8xa8rtWJZax8+sqHX/Vsw4m+emAQW/fg7FvOCME97Q8FqYyb PY4hMI2dwIWL2wgPbxEgCVO5ZRsP2rFmf6DRoZhvUctPzXEHEOv80FDy2z/fHw== From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Thu, 07 Nov 2024 18:02:48 +0100 Subject: [PATCH v3 07/14] pinctrl: qcom: Add MSM8917 tlmm pinctrl driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241107-msm8917-v3-7-6ddc5acd978b@mainlining.org> References: <20241107-msm8917-v3-0-6ddc5acd978b@mainlining.org> In-Reply-To: <20241107-msm8917-v3-0-6ddc5acd978b@mainlining.org> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Lee Jones , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Joerg Roedel , Will Deacon , Robin Murphy , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, iommu@lists.linux.dev, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= , =?utf-8?q?Otto_Pfl=C3=BCger?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1730998970; l=48796; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=QB/X1ZrZZstCG89/cEkMFMQB6ybA9cbguO8Wf/rn6B0=; b=IgIlcQdf2cfC9qmzpzlxS4lrKtVVBOVlPZ1XX2VGI3/6mJlmDM+ePVeAozB1yH1ck4u4mzNPm WHXupdxJuBbAIj6Idj6iZVitQbl930/cGnCSNXJHpmuJUyklHgBCNpV X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= From: Otto Pfl=C3=BCger It is based on MSM8916 driver with the pinctrl definitions from Qualcomm's downstream MSM8917 driver. Signed-off-by: Otto Pfl=C3=BCger Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n Reviewed-by: Dmitry Baryshkov --- drivers/pinctrl/qcom/Kconfig.msm | 6 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-msm8917.c | 1620 ++++++++++++++++++++++++++++= ++++ 3 files changed, 1627 insertions(+) diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfi= g.msm index 38d44052d3c91c1718c8745a306bbc0d24d9f91f..d01f47f45423cce0a50e4a2b890= d6576a72af0bf 100644 --- a/drivers/pinctrl/qcom/Kconfig.msm +++ b/drivers/pinctrl/qcom/Kconfig.msm @@ -137,6 +137,12 @@ config PINCTRL_MSM8916 This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found on the Qualcomm 8916 platform. =20 +config PINCTRL_MSM8917 + tristate "Qualcomm 8917 pin controller driver" + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found on the Qualcomm MSM8917 platform. + config PINCTRL_MSM8953 tristate "Qualcomm 8953 pin controller driver" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 51bf41c343803e47aca7953664b0ef109fbdac67..1bab0551c998e174f63b22468cc= 98ee0e3ddf9e8 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_MSM8960) +=3D pinctrl-msm8960.o obj-$(CONFIG_PINCTRL_MSM8X74) +=3D pinctrl-msm8x74.o obj-$(CONFIG_PINCTRL_MSM8909) +=3D pinctrl-msm8909.o obj-$(CONFIG_PINCTRL_MSM8916) +=3D pinctrl-msm8916.o +obj-$(CONFIG_PINCTRL_MSM8917) +=3D pinctrl-msm8917.o obj-$(CONFIG_PINCTRL_MSM8953) +=3D pinctrl-msm8953.o obj-$(CONFIG_PINCTRL_MSM8976) +=3D pinctrl-msm8976.o obj-$(CONFIG_PINCTRL_MSM8994) +=3D pinctrl-msm8994.o diff --git a/drivers/pinctrl/qcom/pinctrl-msm8917.c b/drivers/pinctrl/qcom/= pinctrl-msm8917.c new file mode 100644 index 0000000000000000000000000000000000000000..cff137bb3b23fbbe2b2630a7cbb= f9f46e39981e7 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-msm8917.c @@ -0,0 +1,1620 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include + +#include "pinctrl-msm.h" + +static const struct pinctrl_pin_desc msm8917_pins[] =3D { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "SDC1_CLK"), + PINCTRL_PIN(135, "SDC1_CMD"), + PINCTRL_PIN(136, "SDC1_DATA"), + PINCTRL_PIN(137, "SDC1_RCLK"), + PINCTRL_PIN(138, "SDC2_CLK"), + PINCTRL_PIN(139, "SDC2_CMD"), + PINCTRL_PIN(140, "SDC2_DATA"), + PINCTRL_PIN(141, "QDSD_CLK"), + PINCTRL_PIN(142, "QDSD_CMD"), + PINCTRL_PIN(143, "QDSD_DATA0"), + PINCTRL_PIN(144, "QDSD_DATA1"), + PINCTRL_PIN(145, "QDSD_DATA2"), + PINCTRL_PIN(146, "QDSD_DATA3"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] =3D { pin } + +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); + +static const unsigned int sdc1_clk_pins[] =3D { 134 }; +static const unsigned int sdc1_cmd_pins[] =3D { 135 }; +static const unsigned int sdc1_data_pins[] =3D { 136 }; +static const unsigned int sdc1_rclk_pins[] =3D { 137 }; +static const unsigned int sdc2_clk_pins[] =3D { 138 }; +static const unsigned int sdc2_cmd_pins[] =3D { 139 }; +static const unsigned int sdc2_data_pins[] =3D { 140 }; +static const unsigned int qdsd_clk_pins[] =3D { 141 }; +static const unsigned int qdsd_cmd_pins[] =3D { 142 }; +static const unsigned int qdsd_data0_pins[] =3D { 143 }; +static const unsigned int qdsd_data1_pins[] =3D { 144 }; +static const unsigned int qdsd_data2_pins[] =3D { 145 }; +static const unsigned int qdsd_data3_pins[] =3D { 146 }; + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .grp =3D PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs =3D (int[]){ \ + msm_mux_gpio, \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs =3D 10, \ + .ctl_reg =3D 0x1000 * id, \ + .io_reg =3D 0x4 + 0x1000 * id, \ + .intr_cfg_reg =3D 0x8 + 0x1000 * id, \ + .intr_status_reg =3D 0xc + 0x1000 * id, \ + .intr_target_reg =3D 0x8 + 0x1000 * id, \ + .mux_bit =3D 2, \ + .pull_bit =3D 0, \ + .drv_bit =3D 6, \ + .oe_bit =3D 9, \ + .in_bit =3D 0, \ + .out_bit =3D 1, \ + .intr_enable_bit =3D 0, \ + .intr_status_bit =3D 0, \ + .intr_target_bit =3D 5, \ + .intr_target_kpss_val =3D 4, \ + .intr_raw_status_bit =3D 4, \ + .intr_polarity_bit =3D 1, \ + .intr_detection_bit =3D 2, \ + .intr_detection_width =3D 2, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp =3D PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg =3D ctl, \ + .io_reg =3D 0, \ + .intr_cfg_reg =3D 0, \ + .intr_status_reg =3D 0, \ + .intr_target_reg =3D 0, \ + .mux_bit =3D -1, \ + .pull_bit =3D pull, \ + .drv_bit =3D drv, \ + .oe_bit =3D -1, \ + .in_bit =3D -1, \ + .out_bit =3D -1, \ + .intr_enable_bit =3D -1, \ + .intr_status_bit =3D -1, \ + .intr_target_bit =3D -1, \ + .intr_target_kpss_val =3D -1, \ + .intr_raw_status_bit =3D -1, \ + .intr_polarity_bit =3D -1, \ + .intr_detection_bit =3D -1, \ + .intr_detection_width =3D -1, \ + } + +enum msm8917_functions { + msm_mux_accel_int, + msm_mux_adsp_ext, + msm_mux_alsp_int, + msm_mux_atest_bbrx0, + msm_mux_atest_bbrx1, + msm_mux_atest_char, + msm_mux_atest_char0, + msm_mux_atest_char1, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_atest_combodac_to_gpio_native, + msm_mux_atest_gpsadc_dtest0_native, + msm_mux_atest_gpsadc_dtest1_native, + msm_mux_atest_tsens, + msm_mux_atest_wlan0, + msm_mux_atest_wlan1, + msm_mux_audio_ref, + msm_mux_audio_reset, + msm_mux_bimc_dte0, + msm_mux_bimc_dte1, + msm_mux_blsp6_spi, + msm_mux_blsp8_spi, + msm_mux_blsp_i2c1, + msm_mux_blsp_i2c2, + msm_mux_blsp_i2c3, + msm_mux_blsp_i2c4, + msm_mux_blsp_i2c5, + msm_mux_blsp_i2c6, + msm_mux_blsp_i2c7, + msm_mux_blsp_i2c8, + msm_mux_blsp_spi1, + msm_mux_blsp_spi2, + msm_mux_blsp_spi3, + msm_mux_blsp_spi4, + msm_mux_blsp_spi5, + msm_mux_blsp_spi6, + msm_mux_blsp_spi7, + msm_mux_blsp_spi8, + msm_mux_blsp_uart1, + msm_mux_blsp_uart2, + msm_mux_blsp_uart3, + msm_mux_blsp_uart4, + msm_mux_blsp_uart5, + msm_mux_blsp_uart6, + msm_mux_blsp_uart7, + msm_mux_blsp_uart8, + msm_mux_cam0_ldo, + msm_mux_cam1_rst, + msm_mux_cam1_standby, + msm_mux_cam2_rst, + msm_mux_cam2_standby, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cdc_pdm0, + msm_mux_codec_int1, + msm_mux_codec_int2, + msm_mux_codec_mad, + msm_mux_coex_uart, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dbg_out, + msm_mux_dmic0_clk, + msm_mux_dmic0_data, + msm_mux_ebi_cdc, + msm_mux_ebi_ch0, + msm_mux_ext_lpass, + msm_mux_forced_usb, + msm_mux_fp_gpio, + msm_mux_fp_int, + msm_mux_gcc_gp1_clk_a, + msm_mux_gcc_gp1_clk_b, + msm_mux_gcc_gp2_clk_a, + msm_mux_gcc_gp2_clk_b, + msm_mux_gcc_gp3_clk_a, + msm_mux_gcc_gp3_clk_b, + msm_mux_gcc_plltest, + msm_mux_gcc_tlmm, + msm_mux_gpio, + msm_mux_gsm0_tx, + msm_mux_key_focus, + msm_mux_key_snapshot, + msm_mux_key_volp, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_lpass_slimbus, + msm_mux_lpass_slimbus0, + msm_mux_lpass_slimbus1, + msm_mux_m_voc, + msm_mux_mag_int, + msm_mux_mdp_vsync, + msm_mux_mipi_dsi0, + msm_mux_modem_tsync, + msm_mux_nav_pps, + msm_mux_nav_pps_in_a, + msm_mux_nav_pps_in_b, + msm_mux_nav_tsync, + msm_mux_nfc_pwr, + msm_mux_ov_ldo, + msm_mux_pa_indicator, + msm_mux_pbs0, + msm_mux_pbs1, + msm_mux_pbs2, + msm_mux_pri_mi2s, + msm_mux_pri_mi2s_mclk_a, + msm_mux_pri_mi2s_mclk_b, + msm_mux_pri_mi2s_ws, + msm_mux_prng_rosc, + msm_mux_pwr_crypto_enabled_a, + msm_mux_pwr_crypto_enabled_b, + msm_mux_pwr_modem_enabled_a, + msm_mux_pwr_modem_enabled_b, + msm_mux_pwr_nav_enabled_a, + msm_mux_pwr_nav_enabled_b, + msm_mux_qdss_cti_trig_in_a0, + msm_mux_qdss_cti_trig_in_a1, + msm_mux_qdss_cti_trig_in_b0, + msm_mux_qdss_cti_trig_in_b1, + msm_mux_qdss_cti_trig_out_a0, + msm_mux_qdss_cti_trig_out_a1, + msm_mux_qdss_cti_trig_out_b0, + msm_mux_qdss_cti_trig_out_b1, + msm_mux_qdss_traceclk_a, + msm_mux_qdss_traceclk_b, + msm_mux_qdss_tracectl_a, + msm_mux_qdss_tracectl_b, + msm_mux_qdss_tracedata_a, + msm_mux_qdss_tracedata_b, + msm_mux_sd_write, + msm_mux_sdcard_det, + msm_mux_sec_mi2s, + msm_mux_sec_mi2s_mclk_a, + msm_mux_sec_mi2s_mclk_b, + msm_mux_sensor_rst, + msm_mux_smb_int, + msm_mux_ssbi_wtr1, + msm_mux_ts_resout, + msm_mux_ts_sample, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_uim2_clk, + msm_mux_uim2_data, + msm_mux_uim2_present, + msm_mux_uim2_reset, + msm_mux_uim_batt, + msm_mux_us_emitter, + msm_mux_us_euro, + msm_mux_wcss_bt, + msm_mux_wcss_fm, + msm_mux_wcss_wlan, + msm_mux_wcss_wlan0, + msm_mux_wcss_wlan1, + msm_mux_wcss_wlan2, + msm_mux_webcam_rst, + msm_mux_webcam_standby, + msm_mux_wsa_io, + msm_mux_wsa_irq, + msm_mux__, +}; + +static const char * const qdss_tracedata_b_groups[] =3D { + "gpio0", "gpio1", "gpio6", "gpio7", "gpio12", "gpio13", "gpio23", + "gpio42", "gpio43", "gpio44", "gpio47", "gpio66", "gpio86", "gpio87", + "gpio88", "gpio92", +}; + +static const char * const blsp_uart1_groups[] =3D { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char * const gpio_groups[] =3D { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", +}; + +static const char * const blsp_spi1_groups[] =3D { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char * const adsp_ext_groups[] =3D { + "gpio1", +}; + +static const char * const blsp_i2c1_groups[] =3D { + "gpio2", "gpio3", +}; + +static const char * const prng_rosc_groups[] =3D { + "gpio2", +}; + +static const char * const qdss_cti_trig_out_b0_groups[] =3D { + "gpio2", +}; + +static const char * const blsp_spi2_groups[] =3D { + "gpio4", "gpio5", "gpio6", "gpio7", +}; + +static const char * const blsp_uart2_groups[] =3D { + "gpio4", "gpio5", "gpio6", "gpio7", +}; + +static const char * const blsp_uart3_groups[] =3D { + "gpio8", "gpio9", "gpio10", "gpio11", +}; + +static const char * const pbs0_groups[] =3D { + "gpio8", +}; + +static const char * const pbs1_groups[] =3D { + "gpio9", +}; + +static const char * const pwr_modem_enabled_b_groups[] =3D { + "gpio9", +}; + +static const char * const blsp_i2c3_groups[] =3D { + "gpio10", "gpio11", +}; + +static const char * const gcc_gp2_clk_b_groups[] =3D { + "gpio10", +}; + +static const char * const ldo_update_groups[] =3D { + "gpio4", +}; + +static const char * const atest_combodac_to_gpio_native_groups[] =3D { + "gpio4", "gpio12", "gpio13", "gpio20", "gpio21", "gpio28", "gpio29", + "gpio30", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", + "gpio45", "gpio46", "gpio47", "gpio48", "gpio67", "gpio115", +}; + +static const char * const ldo_en_groups[] =3D { + "gpio5", +}; + +static const char * const blsp_i2c2_groups[] =3D { + "gpio6", "gpio7", +}; + +static const char * const gcc_gp1_clk_b_groups[] =3D { + "gpio6", +}; + +static const char * const pbs2_groups[] =3D { + "gpio7", +}; + +static const char * const atest_gpsadc_dtest0_native_groups[] =3D { + "gpio7", +}; + +static const char * const blsp_spi3_groups[] =3D { + "gpio8", "gpio9", "gpio10", "gpio11", +}; + +static const char * const gcc_gp3_clk_b_groups[] =3D { + "gpio11", +}; + +static const char * const blsp_spi4_groups[] =3D { + "gpio12", "gpio13", "gpio14", "gpio15", +}; + +static const char * const blsp_uart4_groups[] =3D { + "gpio12", "gpio13", "gpio14", "gpio15", +}; + +static const char * const sec_mi2s_groups[] =3D { + "gpio12", "gpio13", "gpio94", "gpio95", +}; + +static const char * const pwr_nav_enabled_b_groups[] =3D { + "gpio12", +}; + +static const char * const codec_mad_groups[] =3D { + "gpio13", +}; + +static const char * const pwr_crypto_enabled_b_groups[] =3D { + "gpio13", +}; + +static const char * const blsp_i2c4_groups[] =3D { + "gpio14", "gpio15", +}; + +static const char * const blsp_spi5_groups[] =3D { + "gpio16", "gpio17", "gpio18", "gpio19", +}; + +static const char * const blsp_uart5_groups[] =3D { + "gpio16", "gpio17", "gpio18", "gpio19", +}; + +static const char * const qdss_traceclk_a_groups[] =3D { + "gpio16", +}; + +static const char * const atest_bbrx1_groups[] =3D { + "gpio16", +}; + +static const char * const m_voc_groups[] =3D { + "gpio17", "gpio21", +}; + +static const char * const qdss_cti_trig_in_a0_groups[] =3D { + "gpio17", +}; + +static const char * const qdss_cti_trig_in_b0_groups[] =3D { + "gpio21", +}; + +static const char * const blsp_i2c6_groups[] =3D { + "gpio22", "gpio23", +}; + +static const char * const qdss_traceclk_b_groups[] =3D { + "gpio22", +}; + +static const char * const atest_wlan0_groups[] =3D { + "gpio22", +}; + +static const char * const atest_bbrx0_groups[] =3D { + "gpio17", +}; + +static const char * const blsp_i2c5_groups[] =3D { + "gpio18", "gpio19", +}; + +static const char * const qdss_tracectl_a_groups[] =3D { + "gpio18", +}; + +static const char * const atest_gpsadc_dtest1_native_groups[] =3D { + "gpio18", +}; + +static const char * const qdss_tracedata_a_groups[] =3D { + "gpio19", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", + "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", "gpio38", "gpio39", + "gpio40", "gpio50", +}; + +static const char * const blsp_spi6_groups[] =3D { + "gpio20", "gpio21", "gpio22", "gpio23", +}; + +static const char * const blsp_uart6_groups[] =3D { + "gpio20", "gpio21", "gpio22", "gpio23", +}; + +static const char * const qdss_tracectl_b_groups[] =3D { + "gpio20", +}; + +static const char * const atest_wlan1_groups[] =3D { + "gpio23", +}; + +static const char * const mdp_vsync_groups[] =3D { + "gpio24", "gpio25", +}; + +static const char * const pri_mi2s_mclk_a_groups[] =3D { + "gpio25", +}; + +static const char * const sec_mi2s_mclk_a_groups[] =3D { + "gpio25", +}; + +static const char * const cam_mclk_groups[] =3D { + "gpio26", "gpio27", "gpio28", +}; + +static const char * const cci_i2c_groups[] =3D { + "gpio29", "gpio30", "gpio31", "gpio32", +}; + +static const char * const pwr_modem_enabled_a_groups[] =3D { + "gpio29", +}; + +static const char * const cci_timer0_groups[] =3D { + "gpio33", +}; + +static const char * const cci_timer1_groups[] =3D { + "gpio34", +}; + +static const char * const cam1_standby_groups[] =3D { + "gpio35", +}; + +static const char * const pwr_nav_enabled_a_groups[] =3D { + "gpio35", +}; + +static const char * const cam1_rst_groups[] =3D { + "gpio36", +}; + +static const char * const pwr_crypto_enabled_a_groups[] =3D { + "gpio36", +}; + +static const char * const forced_usb_groups[] =3D { + "gpio37", +}; + +static const char * const qdss_cti_trig_out_b1_groups[] =3D { + "gpio37", +}; + +static const char * const cam2_rst_groups[] =3D { + "gpio38", +}; + +static const char * const webcam_standby_groups[] =3D { + "gpio39", +}; + +static const char * const cci_async_groups[] =3D { + "gpio39", +}; + +static const char * const webcam_rst_groups[] =3D { + "gpio40", +}; + +static const char * const ov_ldo_groups[] =3D { + "gpio41", +}; + +static const char * const sd_write_groups[] =3D { + "gpio41", +}; + +static const char * const accel_int_groups[] =3D { + "gpio42", +}; + +static const char * const gcc_gp1_clk_a_groups[] =3D { + "gpio42", +}; + +static const char * const alsp_int_groups[] =3D { + "gpio43", +}; + +static const char * const gcc_gp2_clk_a_groups[] =3D { + "gpio43", +}; + +static const char * const mag_int_groups[] =3D { + "gpio44", +}; + +static const char * const gcc_gp3_clk_a_groups[] =3D { + "gpio44", +}; + +static const char * const blsp6_spi_groups[] =3D { + "gpio47", +}; + +static const char * const fp_int_groups[] =3D { + "gpio48", +}; + +static const char * const qdss_cti_trig_in_b1_groups[] =3D { + "gpio48", +}; + +static const char * const uim_batt_groups[] =3D { + "gpio49", +}; + +static const char * const cam2_standby_groups[] =3D { + "gpio50", +}; + +static const char * const uim1_data_groups[] =3D { + "gpio51", +}; + +static const char * const uim1_clk_groups[] =3D { + "gpio52", +}; + +static const char * const uim1_reset_groups[] =3D { + "gpio53", +}; + +static const char * const uim1_present_groups[] =3D { + "gpio54", +}; + +static const char * const uim2_data_groups[] =3D { + "gpio55", +}; + +static const char * const uim2_clk_groups[] =3D { + "gpio56", +}; + +static const char * const uim2_reset_groups[] =3D { + "gpio57", +}; + +static const char * const uim2_present_groups[] =3D { + "gpio58", +}; + +static const char * const sensor_rst_groups[] =3D { + "gpio59", +}; + +static const char * const mipi_dsi0_groups[] =3D { + "gpio60", +}; + +static const char * const smb_int_groups[] =3D { + "gpio61", +}; + +static const char * const cam0_ldo_groups[] =3D { + "gpio62", +}; + +static const char * const us_euro_groups[] =3D { + "gpio63", +}; + +static const char * const atest_char3_groups[] =3D { + "gpio63", +}; + +static const char * const dbg_out_groups[] =3D { + "gpio63", +}; + +static const char * const bimc_dte0_groups[] =3D { + "gpio63", "gpio65", +}; + +static const char * const ts_resout_groups[] =3D { + "gpio64", +}; + +static const char * const ts_sample_groups[] =3D { + "gpio65", +}; + +static const char * const sec_mi2s_mclk_b_groups[] =3D { + "gpio66", +}; + +static const char * const pri_mi2s_groups[] =3D { + "gpio66", "gpio85", "gpio86", "gpio88", "gpio94", "gpio95", +}; + +static const char * const sdcard_det_groups[] =3D { + "gpio67", +}; + +static const char * const atest_char1_groups[] =3D { + "gpio67", +}; + +static const char * const ebi_cdc_groups[] =3D { + "gpio67", "gpio69", "gpio118", "gpio119", "gpio120", "gpio123", +}; + +static const char * const audio_reset_groups[] =3D { + "gpio68", +}; + +static const char * const atest_char0_groups[] =3D { + "gpio68", +}; + +static const char * const audio_ref_groups[] =3D { + "gpio69", +}; + +static const char * const cdc_pdm0_groups[] =3D { + "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", +}; + +static const char * const pri_mi2s_mclk_b_groups[] =3D { + "gpio69", +}; + +static const char * const lpass_slimbus_groups[] =3D { + "gpio70", +}; + +static const char * const lpass_slimbus0_groups[] =3D { + "gpio71", +}; + +static const char * const lpass_slimbus1_groups[] =3D { + "gpio72", +}; + +static const char * const codec_int1_groups[] =3D { + "gpio73", +}; + +static const char * const codec_int2_groups[] =3D { + "gpio74", +}; + +static const char * const wcss_bt_groups[] =3D { + "gpio75", "gpio83", "gpio84", +}; + +static const char * const atest_char2_groups[] =3D { + "gpio75", +}; + +static const char * const ebi_ch0_groups[] =3D { + "gpio75", +}; + +static const char * const wcss_wlan2_groups[] =3D { + "gpio76", +}; + +static const char * const wcss_wlan1_groups[] =3D { + "gpio77", +}; + +static const char * const wcss_wlan0_groups[] =3D { + "gpio78", +}; + +static const char * const wcss_wlan_groups[] =3D { + "gpio79", "gpio80", +}; + +static const char * const wcss_fm_groups[] =3D { + "gpio81", "gpio82", +}; + +static const char * const ext_lpass_groups[] =3D { + "gpio81", +}; + +static const char * const cri_trng_groups[] =3D { + "gpio82", +}; + +static const char * const cri_trng1_groups[] =3D { + "gpio83", +}; + +static const char * const cri_trng0_groups[] =3D { + "gpio84", +}; + +static const char * const blsp_spi7_groups[] =3D { + "gpio85", "gpio86", "gpio87", "gpio88", +}; + +static const char * const blsp_uart7_groups[] =3D { + "gpio85", "gpio86", "gpio87", "gpio88", +}; + +static const char * const pri_mi2s_ws_groups[] =3D { + "gpio87", +}; + +static const char * const blsp_i2c7_groups[] =3D { + "gpio87", "gpio88", +}; + +static const char * const gcc_tlmm_groups[] =3D { + "gpio87", +}; + +static const char * const dmic0_clk_groups[] =3D { + "gpio89", +}; + +static const char * const dmic0_data_groups[] =3D { + "gpio90", +}; + +static const char * const key_volp_groups[] =3D { + "gpio91", +}; + +static const char * const qdss_cti_trig_in_a1_groups[] =3D { + "gpio91", +}; + +static const char * const us_emitter_groups[] =3D { + "gpio92", +}; + +static const char * const wsa_irq_groups[] =3D { + "gpio93", +}; + +static const char * const wsa_io_groups[] =3D { + "gpio94", "gpio95", +}; + +static const char * const blsp_spi8_groups[] =3D { + "gpio96", "gpio97", "gpio98", "gpio99", +}; + +static const char * const blsp_uart8_groups[] =3D { + "gpio96", "gpio97", "gpio98", "gpio99", +}; + +static const char * const blsp_i2c8_groups[] =3D { + "gpio98", "gpio99", +}; + +static const char * const gcc_plltest_groups[] =3D { + "gpio98", "gpio99", +}; + +static const char * const nav_pps_in_a_groups[] =3D { + "gpio115", +}; + +static const char * const pa_indicator_groups[] =3D { + "gpio116", +}; + +static const char * const modem_tsync_groups[] =3D { + "gpio117", +}; + +static const char * const nav_tsync_groups[] =3D { + "gpio117", +}; + +static const char * const nav_pps_in_b_groups[] =3D { + "gpio117", +}; + +static const char * const nav_pps_groups[] =3D { + "gpio117", +}; + +static const char * const gsm0_tx_groups[] =3D { + "gpio119", +}; + +static const char * const atest_char_groups[] =3D { + "gpio120", +}; + +static const char * const atest_tsens_groups[] =3D { + "gpio120", +}; + +static const char * const bimc_dte1_groups[] =3D { + "gpio121", "gpio122", +}; + +static const char * const ssbi_wtr1_groups[] =3D { + "gpio122", "gpio123", +}; + +static const char * const fp_gpio_groups[] =3D { + "gpio124", +}; + +static const char * const coex_uart_groups[] =3D { + "gpio124", "gpio127", +}; + +static const char * const key_snapshot_groups[] =3D { + "gpio127", +}; + +static const char * const key_focus_groups[] =3D { + "gpio128", +}; + +static const char * const nfc_pwr_groups[] =3D { + "gpio129", +}; + +static const char * const blsp8_spi_groups[] =3D { + "gpio130", +}; + +static const char * const qdss_cti_trig_out_a0_groups[] =3D { + "gpio132", +}; + +static const char * const qdss_cti_trig_out_a1_groups[] =3D { + "gpio133", +}; + +static const struct pinfunction msm8917_functions[] =3D { + MSM_PIN_FUNCTION(accel_int), + MSM_PIN_FUNCTION(adsp_ext), + MSM_PIN_FUNCTION(alsp_int), + MSM_PIN_FUNCTION(atest_bbrx0), + MSM_PIN_FUNCTION(atest_bbrx1), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_char0), + MSM_PIN_FUNCTION(atest_char1), + MSM_PIN_FUNCTION(atest_char2), + MSM_PIN_FUNCTION(atest_char3), + MSM_PIN_FUNCTION(atest_combodac_to_gpio_native), + MSM_PIN_FUNCTION(atest_gpsadc_dtest0_native), + MSM_PIN_FUNCTION(atest_gpsadc_dtest1_native), + MSM_PIN_FUNCTION(atest_tsens), + MSM_PIN_FUNCTION(atest_wlan0), + MSM_PIN_FUNCTION(atest_wlan1), + MSM_PIN_FUNCTION(audio_ref), + MSM_PIN_FUNCTION(audio_reset), + MSM_PIN_FUNCTION(bimc_dte0), + MSM_PIN_FUNCTION(bimc_dte1), + MSM_PIN_FUNCTION(blsp6_spi), + MSM_PIN_FUNCTION(blsp8_spi), + MSM_PIN_FUNCTION(blsp_i2c1), + MSM_PIN_FUNCTION(blsp_i2c2), + MSM_PIN_FUNCTION(blsp_i2c3), + MSM_PIN_FUNCTION(blsp_i2c4), + MSM_PIN_FUNCTION(blsp_i2c5), + MSM_PIN_FUNCTION(blsp_i2c6), + MSM_PIN_FUNCTION(blsp_i2c7), + MSM_PIN_FUNCTION(blsp_i2c8), + MSM_PIN_FUNCTION(blsp_spi1), + MSM_PIN_FUNCTION(blsp_spi2), + MSM_PIN_FUNCTION(blsp_spi3), + MSM_PIN_FUNCTION(blsp_spi4), + MSM_PIN_FUNCTION(blsp_spi5), + MSM_PIN_FUNCTION(blsp_spi6), + MSM_PIN_FUNCTION(blsp_spi7), + MSM_PIN_FUNCTION(blsp_spi8), + MSM_PIN_FUNCTION(blsp_uart1), + MSM_PIN_FUNCTION(blsp_uart2), + MSM_PIN_FUNCTION(blsp_uart3), + MSM_PIN_FUNCTION(blsp_uart4), + MSM_PIN_FUNCTION(blsp_uart5), + MSM_PIN_FUNCTION(blsp_uart6), + MSM_PIN_FUNCTION(blsp_uart7), + MSM_PIN_FUNCTION(blsp_uart8), + MSM_PIN_FUNCTION(cam0_ldo), + MSM_PIN_FUNCTION(cam1_rst), + MSM_PIN_FUNCTION(cam1_standby), + MSM_PIN_FUNCTION(cam2_rst), + MSM_PIN_FUNCTION(cam2_standby), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async), + MSM_PIN_FUNCTION(cci_i2c), + MSM_PIN_FUNCTION(cci_timer0), + MSM_PIN_FUNCTION(cci_timer1), + MSM_PIN_FUNCTION(cdc_pdm0), + MSM_PIN_FUNCTION(codec_int1), + MSM_PIN_FUNCTION(codec_int2), + MSM_PIN_FUNCTION(codec_mad), + MSM_PIN_FUNCTION(coex_uart), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(cri_trng0), + MSM_PIN_FUNCTION(cri_trng1), + MSM_PIN_FUNCTION(dbg_out), + MSM_PIN_FUNCTION(dmic0_clk), + MSM_PIN_FUNCTION(dmic0_data), + MSM_PIN_FUNCTION(ebi_cdc), + MSM_PIN_FUNCTION(ebi_ch0), + MSM_PIN_FUNCTION(ext_lpass), + MSM_PIN_FUNCTION(forced_usb), + MSM_PIN_FUNCTION(fp_gpio), + MSM_PIN_FUNCTION(fp_int), + MSM_PIN_FUNCTION(gcc_gp1_clk_a), + MSM_PIN_FUNCTION(gcc_gp1_clk_b), + MSM_PIN_FUNCTION(gcc_gp2_clk_a), + MSM_PIN_FUNCTION(gcc_gp2_clk_b), + MSM_PIN_FUNCTION(gcc_gp3_clk_a), + MSM_PIN_FUNCTION(gcc_gp3_clk_b), + MSM_PIN_FUNCTION(gcc_plltest), + MSM_PIN_FUNCTION(gcc_tlmm), + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(gsm0_tx), + MSM_PIN_FUNCTION(key_focus), + MSM_PIN_FUNCTION(key_snapshot), + MSM_PIN_FUNCTION(key_volp), + MSM_PIN_FUNCTION(ldo_en), + MSM_PIN_FUNCTION(ldo_update), + MSM_PIN_FUNCTION(lpass_slimbus), + MSM_PIN_FUNCTION(lpass_slimbus0), + MSM_PIN_FUNCTION(lpass_slimbus1), + MSM_PIN_FUNCTION(m_voc), + MSM_PIN_FUNCTION(mag_int), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mipi_dsi0), + MSM_PIN_FUNCTION(modem_tsync), + MSM_PIN_FUNCTION(nav_pps), + MSM_PIN_FUNCTION(nav_pps_in_a), + MSM_PIN_FUNCTION(nav_pps_in_b), + MSM_PIN_FUNCTION(nav_tsync), + MSM_PIN_FUNCTION(nfc_pwr), + MSM_PIN_FUNCTION(ov_ldo), + MSM_PIN_FUNCTION(pa_indicator), + MSM_PIN_FUNCTION(pbs0), + MSM_PIN_FUNCTION(pbs1), + MSM_PIN_FUNCTION(pbs2), + MSM_PIN_FUNCTION(pri_mi2s), + MSM_PIN_FUNCTION(pri_mi2s_mclk_a), + MSM_PIN_FUNCTION(pri_mi2s_mclk_b), + MSM_PIN_FUNCTION(pri_mi2s_ws), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(pwr_crypto_enabled_a), + MSM_PIN_FUNCTION(pwr_crypto_enabled_b), + MSM_PIN_FUNCTION(pwr_modem_enabled_a), + MSM_PIN_FUNCTION(pwr_modem_enabled_b), + MSM_PIN_FUNCTION(pwr_nav_enabled_a), + MSM_PIN_FUNCTION(pwr_nav_enabled_b), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_in_b1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_a1), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b0), + MSM_PIN_FUNCTION(qdss_cti_trig_out_b1), + MSM_PIN_FUNCTION(qdss_traceclk_a), + MSM_PIN_FUNCTION(qdss_traceclk_b), + MSM_PIN_FUNCTION(qdss_tracectl_a), + MSM_PIN_FUNCTION(qdss_tracectl_b), + MSM_PIN_FUNCTION(qdss_tracedata_a), + MSM_PIN_FUNCTION(qdss_tracedata_b), + MSM_PIN_FUNCTION(sd_write), + MSM_PIN_FUNCTION(sdcard_det), + MSM_PIN_FUNCTION(sec_mi2s), + MSM_PIN_FUNCTION(sec_mi2s_mclk_a), + MSM_PIN_FUNCTION(sec_mi2s_mclk_b), + MSM_PIN_FUNCTION(sensor_rst), + MSM_PIN_FUNCTION(smb_int), + MSM_PIN_FUNCTION(ssbi_wtr1), + MSM_PIN_FUNCTION(ts_resout), + MSM_PIN_FUNCTION(ts_sample), + MSM_PIN_FUNCTION(uim1_clk), + MSM_PIN_FUNCTION(uim1_data), + MSM_PIN_FUNCTION(uim1_present), + MSM_PIN_FUNCTION(uim1_reset), + MSM_PIN_FUNCTION(uim2_clk), + MSM_PIN_FUNCTION(uim2_data), + MSM_PIN_FUNCTION(uim2_present), + MSM_PIN_FUNCTION(uim2_reset), + MSM_PIN_FUNCTION(uim_batt), + MSM_PIN_FUNCTION(us_emitter), + MSM_PIN_FUNCTION(us_euro), + MSM_PIN_FUNCTION(wcss_bt), + MSM_PIN_FUNCTION(wcss_fm), + MSM_PIN_FUNCTION(wcss_wlan), + MSM_PIN_FUNCTION(wcss_wlan0), + MSM_PIN_FUNCTION(wcss_wlan1), + MSM_PIN_FUNCTION(wcss_wlan2), + MSM_PIN_FUNCTION(webcam_rst), + MSM_PIN_FUNCTION(webcam_standby), + MSM_PIN_FUNCTION(wsa_io), + MSM_PIN_FUNCTION(wsa_irq), +}; + +static const struct msm_pingroup msm8917_groups[] =3D { + PINGROUP(0, blsp_spi1, blsp_uart1, qdss_tracedata_b, _, _, _, _, + _, _), + PINGROUP(1, blsp_spi1, blsp_uart1, adsp_ext, _, _, _, _, _, + qdss_tracedata_b), + PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, prng_rosc, _, _, _, + _, _), + PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, _, _, _, _, _, _), + PINGROUP(4, blsp_spi2, blsp_uart2, ldo_update, _, + atest_combodac_to_gpio_native, _, _, _, _), + PINGROUP(5, blsp_spi2, blsp_uart2, ldo_en, _, _, _, _, _, _), + PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, gcc_gp1_clk_b, + qdss_tracedata_b, _, _, _, _), + PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, pbs2, _, + qdss_tracedata_b, _, atest_gpsadc_dtest0_native, _), + PINGROUP(8, blsp_spi3, blsp_uart3, pbs0, _, _, _, _, _, _), + PINGROUP(9, blsp_spi3, blsp_uart3, pbs1, pwr_modem_enabled_b, _, _, + _, _, _), + PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, gcc_gp2_clk_b, _, _, + _, _, _), + PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, gcc_gp3_clk_b, _, _, + _, _, _), + PINGROUP(12, blsp_spi4, blsp_uart4, sec_mi2s, pwr_nav_enabled_b, _, + _, _, _, _), + PINGROUP(13, blsp_spi4, blsp_uart4, sec_mi2s, pwr_crypto_enabled_b, _, + _, _, _, _), + PINGROUP(14, blsp_spi4, blsp_uart4, blsp_i2c4, _, _, _, _, _, _), + PINGROUP(15, blsp_spi4, blsp_uart4, blsp_i2c4, _, _, _, _, _, _), + PINGROUP(16, blsp_spi5, blsp_uart5, _, _, _, _, qdss_traceclk_a, + _, atest_bbrx1), + PINGROUP(17, blsp_spi5, blsp_uart5, m_voc, qdss_cti_trig_in_a0, _, + atest_bbrx0, _, _, _), + PINGROUP(18, blsp_spi5, blsp_uart5, blsp_i2c5, qdss_tracectl_a, _, + atest_gpsadc_dtest1_native, _, _, _), + PINGROUP(19, blsp_spi5, blsp_uart5, blsp_i2c5, qdss_tracedata_a, _, + _, _, _, _), + PINGROUP(20, blsp_spi6, blsp_uart6, _, _, _, _, _, _, + qdss_tracectl_b), + PINGROUP(21, blsp_spi6, blsp_uart6, m_voc, _, _, _, _, _, + qdss_cti_trig_in_b0), + PINGROUP(22, blsp_spi6, blsp_uart6, blsp_i2c6, qdss_traceclk_b, _, + atest_wlan0, _, _, _), + PINGROUP(23, blsp_spi6, blsp_uart6, blsp_i2c6, qdss_tracedata_b, _, + atest_wlan1, _, _, _), + PINGROUP(24, mdp_vsync, _, _, _, _, _, _, _, _), + PINGROUP(25, mdp_vsync, pri_mi2s_mclk_a, sec_mi2s_mclk_a, _, _, _, + _, _, _), + PINGROUP(26, cam_mclk, _, _, _, _, _, qdss_tracedata_a, _, _), + PINGROUP(27, cam_mclk, _, _, _, _, _, _, _, qdss_tracedata_a), + PINGROUP(28, cam_mclk, _, _, _, _, _, qdss_tracedata_a, _, + atest_combodac_to_gpio_native), + PINGROUP(29, cci_i2c, pwr_modem_enabled_a, _, _, _, _, _, + qdss_tracedata_a, _), + PINGROUP(30, cci_i2c, _, _, _, _, _, _, _, qdss_tracedata_a), + PINGROUP(31, cci_i2c, _, _, _, _, _, _, _, qdss_tracedata_a), + PINGROUP(32, cci_i2c, _, _, _, _, _, _, _, qdss_tracedata_a), + PINGROUP(33, cci_timer0, _, _, _, _, _, _, _, qdss_tracedata_a), + PINGROUP(34, cci_timer1, _, _, _, _, _, _, _, qdss_tracedata_a), + PINGROUP(35, pwr_nav_enabled_a, _, _, _, _, _, _, _, + qdss_tracedata_a), + PINGROUP(36, pwr_crypto_enabled_a, _, _, _, _, _, _, _, + qdss_tracedata_a), + PINGROUP(37, _, _, _, _, _, qdss_cti_trig_out_b1, _, _, _), + PINGROUP(38, _, qdss_tracedata_a, _, _, _, _, _, _, _), + PINGROUP(39, cci_async, _, _, _, _, _, qdss_tracedata_a, _, + atest_combodac_to_gpio_native), + PINGROUP(40, _, _, _, _, qdss_tracedata_a, _, + atest_combodac_to_gpio_native, _, _), + PINGROUP(41, sd_write, _, _, _, _, _, _, _, + atest_combodac_to_gpio_native), + PINGROUP(42, gcc_gp1_clk_a, qdss_tracedata_b, _, + atest_combodac_to_gpio_native, _, _, _, _, _), + PINGROUP(43, gcc_gp2_clk_a, qdss_tracedata_b, _, + atest_combodac_to_gpio_native, _, _, _, _, _), + PINGROUP(44, gcc_gp3_clk_a, qdss_tracedata_b, _, + atest_combodac_to_gpio_native, _, _, _, _, _), + PINGROUP(45, _, _, atest_combodac_to_gpio_native, _, _, _, _, _, + _), + PINGROUP(46, _, _, atest_combodac_to_gpio_native, _, _, _, _, _, + _), + PINGROUP(47, blsp6_spi, _, qdss_tracedata_b, _, + atest_combodac_to_gpio_native, _, _, _, _), + PINGROUP(48, _, qdss_cti_trig_in_b1, _, + atest_combodac_to_gpio_native, _, _, _, _, _), + PINGROUP(49, uim_batt, _, _, _, _, _, _, _, _), + PINGROUP(50, qdss_tracedata_a, _, _, _, _, _, _, _, _), + PINGROUP(51, uim1_data, _, _, _, _, _, _, _, _), + PINGROUP(52, uim1_clk, _, _, _, _, _, _, _, _), + PINGROUP(53, uim1_reset, _, _, _, _, _, _, _, _), + PINGROUP(54, uim1_present, _, _, _, _, _, _, _, _), + PINGROUP(55, uim2_data, _, _, _, _, _, _, _, _), + PINGROUP(56, uim2_clk, _, _, _, _, _, _, _, _), + PINGROUP(57, uim2_reset, _, _, _, _, _, _, _, _), + PINGROUP(58, uim2_present, _, _, _, _, _, _, _, _), + PINGROUP(59, _, _, _, _, _, _, _, _, _), + PINGROUP(60, _, _, _, _, _, _, _, _, _), + PINGROUP(61, _, _, _, _, _, _, _, _, _), + PINGROUP(62, _, _, _, _, _, _, _, _, _), + PINGROUP(63, atest_char3, dbg_out, bimc_dte0, _, _, _, _, _, _), + PINGROUP(64, _, _, _, _, _, _, _, _, _), + PINGROUP(65, bimc_dte0, _, _, _, _, _, _, _, _), + PINGROUP(66, sec_mi2s_mclk_b, pri_mi2s, _, qdss_tracedata_b, _, _, + _, _, _), + PINGROUP(67, atest_char1, ebi_cdc, _, atest_combodac_to_gpio_native, + _, _, _, _, _), + PINGROUP(68, atest_char0, _, _, _, _, _, _, _, _), + PINGROUP(69, audio_ref, cdc_pdm0, pri_mi2s_mclk_b, ebi_cdc, _, _, _, + _, _), + PINGROUP(70, lpass_slimbus, cdc_pdm0, _, _, _, _, _, _, _), + PINGROUP(71, lpass_slimbus0, cdc_pdm0, _, _, _, _, _, _, _), + PINGROUP(72, lpass_slimbus1, cdc_pdm0, _, _, _, _, _, _, _), + PINGROUP(73, cdc_pdm0, _, _, _, _, _, _, _, _), + PINGROUP(74, cdc_pdm0, _, _, _, _, _, _, _, _), + PINGROUP(75, wcss_bt, atest_char2, _, ebi_ch0, _, _, _, _, _), + PINGROUP(76, wcss_wlan2, _, _, _, _, _, _, _, _), + PINGROUP(77, wcss_wlan1, _, _, _, _, _, _, _, _), + PINGROUP(78, wcss_wlan0, _, _, _, _, _, _, _, _), + PINGROUP(79, wcss_wlan, _, _, _, _, _, _, _, _), + PINGROUP(80, wcss_wlan, _, _, _, _, _, _, _, _), + PINGROUP(81, wcss_fm, ext_lpass, _, _, _, _, _, _, _), + PINGROUP(82, wcss_fm, cri_trng, _, _, _, _, _, _, _), + PINGROUP(83, wcss_bt, cri_trng1, _, _, _, _, _, _, _), + PINGROUP(84, wcss_bt, cri_trng0, _, _, _, _, _, _, _), + PINGROUP(85, pri_mi2s, blsp_spi7, blsp_uart7, _, _, _, _, _, _), + PINGROUP(86, pri_mi2s, blsp_spi7, blsp_uart7, qdss_tracedata_b, _, _, + _, _, _), + PINGROUP(87, pri_mi2s_ws, blsp_spi7, blsp_uart7, blsp_i2c7, + qdss_tracedata_b, gcc_tlmm, _, _, _), + PINGROUP(88, pri_mi2s, blsp_spi7, blsp_uart7, blsp_i2c7, _, _, _, + _, _), + PINGROUP(89, dmic0_clk, _, _, _, _, _, _, _, _), + PINGROUP(90, dmic0_data, _, _, _, _, _, _, _, _), + PINGROUP(91, _, _, _, _, _, qdss_cti_trig_in_a1, _, _, _), + PINGROUP(92, _, _, _, _, _, qdss_tracedata_b, _, _, _), + PINGROUP(93, _, _, _, _, _, _, _, _, _), + PINGROUP(94, wsa_io, sec_mi2s, pri_mi2s, _, _, _, _, _, _), + PINGROUP(95, wsa_io, sec_mi2s, pri_mi2s, _, _, _, _, _, _), + PINGROUP(96, blsp_spi8, blsp_uart8, _, _, _, _, _, _, _), + PINGROUP(97, blsp_spi8, blsp_uart8, _, _, _, _, _, _, _), + PINGROUP(98, blsp_spi8, blsp_uart8, blsp_i2c8, gcc_plltest, _, _, _, + _, _), + PINGROUP(99, blsp_spi8, blsp_uart8, blsp_i2c8, gcc_plltest, _, _, _, + _, _), + PINGROUP(100, _, _, _, _, _, _, _, _, _), + PINGROUP(101, _, _, _, _, _, _, _, _, _), + PINGROUP(102, _, _, _, _, _, _, _, _, _), + PINGROUP(103, _, _, _, _, _, _, _, _, _), + PINGROUP(104, _, _, _, _, _, _, _, _, _), + PINGROUP(105, _, _, _, _, _, _, _, _, _), + PINGROUP(106, _, _, _, _, _, _, _, _, _), + PINGROUP(107, _, _, _, _, _, _, _, _, _), + PINGROUP(108, _, _, _, _, _, _, _, _, _), + PINGROUP(109, _, _, _, _, _, _, _, _, _), + PINGROUP(110, _, _, _, _, _, _, _, _, _), + PINGROUP(111, _, _, _, _, _, _, _, _, _), + PINGROUP(112, _, _, _, _, _, _, _, _, _), + PINGROUP(113, _, _, _, _, _, _, _, _, _), + PINGROUP(114, _, _, _, _, _, _, _, _, _), + PINGROUP(115, _, _, nav_pps_in_a, _, atest_combodac_to_gpio_native, + _, _, _, _), + PINGROUP(116, _, pa_indicator, _, _, _, _, _, _, _), + PINGROUP(117, _, modem_tsync, nav_tsync, nav_pps_in_b, nav_pps, _, + _, _, _), + PINGROUP(118, _, ebi_cdc, _, _, _, _, _, _, _), + PINGROUP(119, gsm0_tx, _, ebi_cdc, _, _, _, _, _, _), + PINGROUP(120, _, atest_char, ebi_cdc, _, atest_tsens, _, _, _, _), + PINGROUP(121, _, _, _, bimc_dte1, _, _, _, _, _), + PINGROUP(122, _, ssbi_wtr1, _, _, bimc_dte1, _, _, _, _), + PINGROUP(123, _, ssbi_wtr1, ebi_cdc, _, _, _, _, _, _), + PINGROUP(124, coex_uart, _, _, _, _, _, _, _, _), + PINGROUP(125, _, _, _, _, _, _, _, _, _), + PINGROUP(126, _, _, _, _, _, _, _, _, _), + PINGROUP(127, coex_uart, _, _, _, _, _, _, _, _), + PINGROUP(128, _, _, _, _, _, _, _, _, _), + PINGROUP(129, _, _, _, _, _, _, _, _, _), + PINGROUP(130, blsp8_spi, _, _, _, _, _, _, _, _), + PINGROUP(131, _, _, _, _, _, _, _, _, _), + PINGROUP(132, qdss_cti_trig_out_a0, _, _, _, _, _, _, _, _), + PINGROUP(133, qdss_cti_trig_out_a1, _, _, _, _, _, _, _, _), + SDC_PINGROUP(sdc1_clk, 0x10a000, 13, 6), + SDC_PINGROUP(sdc1_cmd, 0x10a000, 11, 3), + SDC_PINGROUP(sdc1_data, 0x10a000, 9, 0), + SDC_PINGROUP(sdc1_rclk, 0x10a000, 15, 0), + SDC_PINGROUP(sdc2_clk, 0x109000, 14, 6), + SDC_PINGROUP(sdc2_cmd, 0x109000, 11, 3), + SDC_PINGROUP(sdc2_data, 0x109000, 9, 0), + SDC_PINGROUP(qdsd_clk, 0x19c000, 3, 0), + SDC_PINGROUP(qdsd_cmd, 0x19c000, 8, 5), + SDC_PINGROUP(qdsd_data0, 0x19c000, 13, 10), + SDC_PINGROUP(qdsd_data1, 0x19c000, 18, 15), + SDC_PINGROUP(qdsd_data2, 0x19c000, 23, 20), + SDC_PINGROUP(qdsd_data3, 0x19c000, 28, 25), +}; + +static const struct msm_pinctrl_soc_data msm8917_pinctrl =3D { + .pins =3D msm8917_pins, + .npins =3D ARRAY_SIZE(msm8917_pins), + .functions =3D msm8917_functions, + .nfunctions =3D ARRAY_SIZE(msm8917_functions), + .groups =3D msm8917_groups, + .ngroups =3D ARRAY_SIZE(msm8917_groups), + .ngpios =3D 134, +}; + +static int msm8917_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &msm8917_pinctrl); +} + +static const struct of_device_id msm8917_pinctrl_of_match[] =3D { + { .compatible =3D "qcom,msm8917-pinctrl", }, + { }, +}; +MODULE_DEVICE_TABLE(of, msm8917_pinctrl_of_match); + +static struct platform_driver msm8917_pinctrl_driver =3D { + .driver =3D { + .name =3D "msm8917-pinctrl", + .of_match_table =3D msm8917_pinctrl_of_match, + }, + .probe =3D msm8917_pinctrl_probe, + .remove =3D msm_pinctrl_remove, +}; + +static int __init msm8917_pinctrl_init(void) +{ + return platform_driver_register(&msm8917_pinctrl_driver); +} +arch_initcall(msm8917_pinctrl_init); + +static void __exit msm8917_pinctrl_exit(void) +{ + platform_driver_unregister(&msm8917_pinctrl_driver); +} +module_exit(msm8917_pinctrl_exit); + +MODULE_DESCRIPTION("Qualcomm msm8917 pinctrl driver"); +MODULE_LICENSE("GPL"); --=20 2.47.0 From nobody Sun Nov 24 01:31:42 2024 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54166217F29; Thu, 7 Nov 2024 17:03:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730998989; cv=none; b=OZQcCxDOZChnhOVsMlkHmhmodvB/TRUyf+V1PxcOp55KO5kcxOQFPT3WKbgaUkTOlHewn+AcYfI2WcQvo91v7WjImBqQSMP284KG/cxAfuk7LUYPDIOKqIN0eTuMjBEa+zEzKMBN6g8WThI8jACGDv5ys/G30aDd9Ezb9gLr390= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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08/14] dt-bindings: thermal: tsens: Add MSM8937 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241107-msm8917-v3-8-6ddc5acd978b@mainlining.org> References: <20241107-msm8917-v3-0-6ddc5acd978b@mainlining.org> In-Reply-To: <20241107-msm8917-v3-0-6ddc5acd978b@mainlining.org> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Lee Jones , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Joerg Roedel , Will Deacon , Robin Murphy , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, iommu@lists.linux.dev, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1730998970; l=935; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=HpsJRRqcEB7ubb20AIGzwyE59bS3PSN7BTK6n02gdPE=; b=cGwGyNO8XN/GQLArpKASfGZHiyWTyIaZIA9bC6H45VQ+wd4cQHvoxBAWGmxbKjQI31v4j5AXu cmLOT5488zlBVLWP4B6GTFpqYlaixsNUS8PTl9Ako2h9s45FHMAnEFn X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= Document the compatible string for tsens v1.4 block found in MSM8937. Acked-by: Krzysztof Kozlowski Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Do= cumentation/devicetree/bindings/thermal/qcom-tsens.yaml index a12fddc8195500a0e7bdd51952a558890b35935c..f51656b672030b12ea0405fd392= af11056093be7 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -39,6 +39,7 @@ properties: - description: v1 of TSENS items: - enum: + - qcom,msm8937-tsens - qcom,msm8956-tsens - qcom,msm8976-tsens - qcom,qcs404-tsens --=20 2.47.0 From nobody Sun Nov 24 01:31:42 2024 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B651F217F54; Thu, 7 Nov 2024 17:03:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730998989; cv=none; b=BYIuO9Lic1r9fXA3P+LWlWfzKzVQnZXcPfhseH+76Rv3QVKY+HNmBwGZJdzOvfRFsAC1hHiN3kcOS/vbUeWqQ5n2OOqmSWxFizZa2fOPZgzgvMG6m67MwGiApxnDzr6EkpkxDO69PWE+oCoTgaAmkOXMK9iknC66IlMQ6vXtcoU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730998989; c=relaxed/simple; bh=LA1yHm9JefRTzAcl7oQuKzrTAdjvePqLu6hR07bVDBU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Yh3OyQh9W11mYaJQry0f/hHZIr/3o6Syilf9cJbppUYnA96xgVuKjBNWVibm5cIz+aGDHDdzkrwJHwLV4Q7QsIZVsO4mpasBwtgw6mCXQCct05nZXZjRzYaLXrBlEhByduvnyhkxPSnjxQ/+uL/5BKQsy50cXjPWUkDdPgMf1KI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org; spf=pass smtp.mailfrom=mainlining.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=i2EsQkMK; arc=none smtp.client-ip=5.75.144.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="i2EsQkMK" Received: from [192.168.118.162] (254C2715.nat.pool.telekom.hu [37.76.39.21]) by mail.mainlining.org (Postfix) with ESMTPSA id E0FE0E45C4; Thu, 7 Nov 2024 17:03:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mainlining.org; s=psm; t=1730998986; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=SS6oPEKwC33ey53SPdqjnM/5YgQcFeMfM2H7KRWWuck=; b=i2EsQkMKEJJZhOmzH4LmrThFtjQ6/7eZKAK28UQO6oeGLtLiZvyZrXvMBzB7sKguL1sfrQ PofXoIZkQhRzDBFQJ9YiSn2ZZgUr4o97AKlnR0x54pNTVNxH2ZSjJf0xQPJef35BMVPgdm 4ePVpxjc1dJGwHXFlexaZ9fd1wajwxfB13h6Fe9CgoAvAoVumnIGxkvv69I+uQO7qYa7FN EC6qcdoSkh4Hriuxb36jUgGlNmzE7u9gn7iNZ+nd0lrs+xxnRokiZz3bwbUBGqnQSC23dZ jyhjE1DL/GDNMH9OOgkOGBEKmP1hzTVAZj4tZDXO2DiONw4k+LKJtMP/UX8r5Q== From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Thu, 07 Nov 2024 18:02:50 +0100 Subject: [PATCH v3 09/14] thermal/drivers/qcom/tsens-v1: Add support for MSM8937 tsens Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241107-msm8917-v3-9-6ddc5acd978b@mainlining.org> References: <20241107-msm8917-v3-0-6ddc5acd978b@mainlining.org> In-Reply-To: <20241107-msm8917-v3-0-6ddc5acd978b@mainlining.org> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Lee Jones , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Joerg Roedel , Will Deacon , Robin Murphy , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, iommu@lists.linux.dev, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1730998970; l=2407; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=LA1yHm9JefRTzAcl7oQuKzrTAdjvePqLu6hR07bVDBU=; b=wiEELKM4lZYF5c55Ae0JFmi2JOhhGOoNTAzc1MZcBu3BIhVR0UZZJcINmKMWgZOQPW7GVk2WG K8ctq8AQoVWCcaHSfFCl6KlmpepF4cc8BLGMg4h8Xshe84B597tqHW5 X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= Add support for tsens v1.4 block what can be found in MSM8937 and MSM8917. Reviewed-by: Dmitry Baryshkov Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- drivers/thermal/qcom/tsens-v1.c | 13 +++++++++++++ drivers/thermal/qcom/tsens.c | 3 +++ drivers/thermal/qcom/tsens.h | 2 +- 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v= 1.c index dc1c4ae2d8b01b42a0edbb7f12a5780b25d0c8ac..50787cf68bfae48da6061d8e759= 56308f41053be 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -162,6 +162,19 @@ struct tsens_plat_data data_tsens_v1 =3D { .fields =3D tsens_v1_regfields, }; =20 +static const struct tsens_ops ops_8937 =3D { + .init =3D init_common, + .calibrate =3D tsens_calibrate_common, + .get_temp =3D get_temp_tsens_valid, +}; + +struct tsens_plat_data data_8937 =3D { + .num_sensors =3D 11, + .ops =3D &ops_8937, + .feat =3D &tsens_v1_feat, + .fields =3D tsens_v1_regfields, +}; + static const struct tsens_ops ops_8956 =3D { .init =3D init_8956, .calibrate =3D tsens_calibrate_common, diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 0b4421bf478544dfa071c792dc812ffaedc9c635..d2db804692f01d300b555d491e8= a1acc597b3819 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -1119,6 +1119,9 @@ static const struct of_device_id tsens_table[] =3D { }, { .compatible =3D "qcom,msm8916-tsens", .data =3D &data_8916, + }, { + .compatible =3D "qcom,msm8937-tsens", + .data =3D &data_8937, }, { .compatible =3D "qcom,msm8939-tsens", .data =3D &data_8939, diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index cab39de045b100030de6a1209c58bb09561a3224..7b36a0318fa6a078e73ce26dfe7= 387e4435148b4 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -647,7 +647,7 @@ extern struct tsens_plat_data data_8960; extern struct tsens_plat_data data_8226, data_8909, data_8916, data_8939, = data_8974, data_9607; =20 /* TSENS v1 targets */ -extern struct tsens_plat_data data_tsens_v1, data_8976, data_8956; +extern struct tsens_plat_data data_tsens_v1, data_8937, data_8976, data_89= 56; =20 /* TSENS v2 targets */ extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2; --=20 2.47.0 From nobody Sun Nov 24 01:31:42 2024 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E7EAC218314; Thu, 7 Nov 2024 17:03:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730998991; cv=none; b=G4nZeEtCGNSMn6DX4na9bEU8vs3cgzZa+hHrtpxqvMg0Hv17WtD63DCK2XZ9MHmS1tHTsnRn8Qvm+/480ju5a+U/7Oc9PUqBU7IIGH74VdsvwL0k/5ee78v+MbCcvvUWEecE1L2GyaTLUT8NFyAy768KMbpuqNviLclx2wNP5Ug= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241107-msm8917-v3-10-6ddc5acd978b@mainlining.org> References: <20241107-msm8917-v3-0-6ddc5acd978b@mainlining.org> In-Reply-To: <20241107-msm8917-v3-0-6ddc5acd978b@mainlining.org> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Lee Jones , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Joerg Roedel , Will Deacon , Robin Murphy , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, iommu@lists.linux.dev, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1730998970; l=1003; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=9EpBDn6+VrUhl6s9RDziNCH5FD1n12+IVb+sGxL5HO0=; b=bVSjht3ENoB9eiHK/uMTg79heW+7rE6iPe+yP4DZ4FGQcFwdX2hqZFd4nnpLnmdjxTKY4x/Mp q2HNSsT1vTBAMFxu19L3Bok52z7hneygN4qw1nRwPmivXJKx/APZ6tk X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= Add MSM8917 compatible string with "qcom,msm-iommu-v1" as fallback for the MSM8917 IOMMU which is compatible with Qualcomm's secure fw "SMMU v1" implementation. Acked-by: Krzysztof Kozlowski Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- Documentation/devicetree/bindings/iommu/qcom,iommu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml b/Docu= mentation/devicetree/bindings/iommu/qcom,iommu.yaml index f8cebc9e8cd9d46b449cd297153dbebe5c84bf3f..5ae9a628261fd251c1e991a7066= 2c6d37ef2c4e3 100644 --- a/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml @@ -21,6 +21,7 @@ properties: - items: - enum: - qcom,msm8916-iommu + - qcom,msm8917-iommu - qcom,msm8953-iommu - const: qcom,msm-iommu-v1 - items: --=20 2.47.0 From nobody Sun Nov 24 01:31:42 2024 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6811D218943; Thu, 7 Nov 2024 17:03:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730998992; cv=none; b=FMTHOAc88y0/8bt4qOT2Biw0dN0eymQ58peboG2rQBbMD+++bDiazxnEVnDAV2HBukXsiZLFCNoCnXqn8IFrhIBdv0kuZBrPbMkUKRnsjejK77h6NSqO8qRIBZAu6PZZMru+l4y85PsEAlFQjYWZO1Vz1j8XLSHtQY4Y4UulMQY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730998992; c=relaxed/simple; bh=oSFXD5koz0bnImj9AwyYkdxZ8tPIPU4UsWyonhEengo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=blwodvHpEIYAN4/8dU53Ca/IndAWdWhbUuLHV27GpB83Cl78tVT3rMIPr2N+p7wFylLtQln2Fb/M0rSZJU1n4K8NyObMufFrEr9l3zkX3+C+7k9LKifSqDcv7K53YUZzTBR/OmRT6UfvwvPseWesyn1NuA1ijj6LDbeH1gAKPKE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org; spf=pass smtp.mailfrom=mainlining.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=BpnqCnfK; arc=none smtp.client-ip=5.75.144.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="BpnqCnfK" Received: from [192.168.118.162] (254C2715.nat.pool.telekom.hu [37.76.39.21]) by mail.mainlining.org (Postfix) with ESMTPSA id 8F22EE45C6; Thu, 7 Nov 2024 17:03:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mainlining.org; s=psm; t=1730998988; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=J8Y4yxwqnDss/PAt3TvJTQZaFUiFNkqCyH+WUzWqZ+0=; b=BpnqCnfK6paMF8VZfQRRstEiqTuNScpMIG+3G++5XW5BrMctDBkggFEewyZ/BgZq/IF0d1 sMqPF//On8YSIJQn5ZEV3oMfcp+Wc0HX6V4+u05kTFFd+vD9a3sjyvjvVGxzP6V2jxwgne BDnfVYOgibAncBmXyCvYJ89yLLrHUpDdo8bMa/cfm1h5YRnCK7LI0kFf08sBQ3Yk2/i6Wm SeF7ur38iUAFXruhHaxIUX5Q0eQoJz1WR1WNAzUXFFBBPAykIOdpT1cI+6LTI9ui1gVVlQ VLTZc55/awDuslj/d1qBA06JYThR3IBpftx3ZdxqXMEHF9MMqHY1FTHoH7hpHw== From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Thu, 07 Nov 2024 18:02:52 +0100 Subject: [PATCH v3 11/14] dt-bindings: nvmem: Add compatible for MS8917 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241107-msm8917-v3-11-6ddc5acd978b@mainlining.org> References: <20241107-msm8917-v3-0-6ddc5acd978b@mainlining.org> In-Reply-To: <20241107-msm8917-v3-0-6ddc5acd978b@mainlining.org> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Lee Jones , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Joerg Roedel , Will Deacon , Robin Murphy , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, iommu@lists.linux.dev, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1730998970; l=923; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=oSFXD5koz0bnImj9AwyYkdxZ8tPIPU4UsWyonhEengo=; b=axyFfUUUmlynf287+B+lJntJQpFF7gZ61q6QZ+h1SpZFBfKAWEfcIvyn6otQLPh4MfXuI+oye HZPjM6djw1hBU/qH1KsfK8EF76KMUPXFFZVrwFNu7vCm+H2AkaE4wZf X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= Document the QFPROM block found on MSM8917. Acked-by: Krzysztof Kozlowski Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Doc= umentation/devicetree/bindings/nvmem/qcom,qfprom.yaml index 80845c722ae46611c722effeaaf014a0caf76e4a..4d81f98ed37a3a12f01d444dbfa= 77badcc09c22d 100644 --- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml +++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml @@ -26,6 +26,7 @@ properties: - qcom,ipq9574-qfprom - qcom,msm8226-qfprom - qcom,msm8916-qfprom + - qcom,msm8917-qfprom - qcom,msm8974-qfprom - qcom,msm8976-qfprom - qcom,msm8996-qfprom --=20 2.47.0 From nobody Sun Nov 24 01:31:42 2024 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B6C9216DE7; Thu, 7 Nov 2024 17:03:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730998998; cv=none; b=h1ZI6VSPqTt9nqByt7ZWk+T6TpMDyop9wFDkzJtzQzePM/0g+h5Nta+/o9FzmvSnwVBJycIvs23JGzmjoZpDhzLZFVVp6C+cWDE3JBO8IkfZFgZeJeumUN6ZPs9XmWZmktHdNRx5wdepC+7H6m/H5iIrvVaBGflw6fl0vIcTBV8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730998998; c=relaxed/simple; bh=rpnMxo36Tob8+PWnDpJfJXBBXFt0Kxg9duZR243hjgU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dtjMK3jSw/Eb2EFH/skNvPbNDbOlo6TlGxPf5GrUnqonZUZTmyD7LKrQh2Z2LIsxkNMuc8JzY7FoIH/WmxGwPEUBs+KMHxRxx37jaSll0cCdLMmoUSrtaRcGgvOXOMBGfq/pw99RnnBJ7ROELUjoh9lCE7GznWIZ9OVJ827n5eM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org; spf=pass smtp.mailfrom=mainlining.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=kC4eu8Un; arc=none smtp.client-ip=5.75.144.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="kC4eu8Un" Received: from [192.168.118.162] (254C2715.nat.pool.telekom.hu [37.76.39.21]) by mail.mainlining.org (Postfix) with ESMTPSA id 1A5C2E45C7; Thu, 7 Nov 2024 17:03:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mainlining.org; s=psm; t=1730998990; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=KcVAxQ2qNrm5pTAfHNxkoVCIISQ0fzOXw9ZW+beb0LI=; b=kC4eu8Unqcj2tqnq2ctG93LlM4Onu4dNvpICe8ovX5iRsZaStds6zQI8/Z60hwf5Q1rC8y uik2KNHYQMbcxifJQDZQS57gCG8BudUvVkqua45wZ4FLv5wwNa0x6VDcu9QckXCmYPrnS/ ZtncNsOrEowvjOnPNHikbHCwkfJwl8Sna3kyXGLLOAxF6E7dyWquqeFNrMOAPOezbnHI34 3PHqZC82dRVdmkJs2V9VMVgLMoUNLcVkgP8p+V4tLDWh1gjwQgT1q4m/DAV3kaM8sUXKO3 4VMuNUxeoKjjwMdXYhh0irPX+KOHcKDHFb6UX20a5evIZhtXrhs50Ns5uh5LFg== From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Thu, 07 Nov 2024 18:02:53 +0100 Subject: [PATCH v3 12/14] arm64: dts: qcom: Add initial support for MSM8917 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241107-msm8917-v3-12-6ddc5acd978b@mainlining.org> References: <20241107-msm8917-v3-0-6ddc5acd978b@mainlining.org> In-Reply-To: <20241107-msm8917-v3-0-6ddc5acd978b@mainlining.org> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Lee Jones , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Joerg Roedel , Will Deacon , Robin Murphy , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, iommu@lists.linux.dev, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= , =?utf-8?q?Otto_Pfl=C3=BCger?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1730998970; l=47863; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=B5Z8fPXbvD1BxOhp4pmFnNIL8xcwbzvHS6Wq7l2OA4Y=; b=3ikWQbe+D5fJHD2CKgZQyuXcT3MYAuIjUFKU/mDOSTDF4+uTh95xY+fnaw3mFi6q8k8SnIgZ6 7o6IaBKuHVkCgAHTlKN//v3HpNcd1sXY7DGhiSnFXrJzCgirMYf7ahZ X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= From: Otto Pfl=C3=BCger Add initial support for MSM8917 SoC. Signed-off-by: Otto Pfl=C3=BCger [reword commit, rebase, fix schema errors] Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- arch/arm64/boot/dts/qcom/msm8917.dtsi | 2007 +++++++++++++++++++++++++++++= ++++ 1 file changed, 2007 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8917.dtsi b/arch/arm64/boot/dts/qc= om/msm8917.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..f7446dd7d44c9f2db6d309a817c= 0e58cbd143b5c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8917.dtsi @@ -0,0 +1,2007 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&intc>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + aliases { + mmc0 =3D &sdhc_1; /* SDC1 eMMC slot */ + mmc1 =3D &sdhc_2; /* SDC2 SD card slot */ + }; + + chosen { }; + + clocks { + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + xo_board: xo-board { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x100>; + next-level-cache =3D <&l2_0>; + enable-method =3D "psci"; + clocks =3D <&apcs>; + operating-points-v2 =3D <&cpu_opp_table>; + #cooling-cells =3D <2>; + power-domains =3D <&cpu_pd0>; + power-domain-names =3D "psci"; + }; + + cpu1: cpu@101 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x101>; + next-level-cache =3D <&l2_0>; + enable-method =3D "psci"; + clocks =3D <&apcs>; + operating-points-v2 =3D <&cpu_opp_table>; + #cooling-cells =3D <2>; + power-domains =3D <&cpu_pd1>; + power-domain-names =3D "psci"; + }; + + cpu2: cpu@102 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x102>; + next-level-cache =3D <&l2_0>; + enable-method =3D "psci"; + clocks =3D <&apcs>; + operating-points-v2 =3D <&cpu_opp_table>; + #cooling-cells =3D <2>; + power-domains =3D <&cpu_pd2>; + power-domain-names =3D "psci"; + }; + + cpu3: cpu@103 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x103>; + next-level-cache =3D <&l2_0>; + enable-method =3D "psci"; + clocks =3D <&apcs>; + operating-points-v2 =3D <&cpu_opp_table>; + #cooling-cells =3D <2>; + power-domains =3D <&cpu_pd3>; + power-domain-names =3D "psci"; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + }; + }; + + domain-idle-states { + cluster_pwrdn: cluster-gdhs { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x41000043>; + entry-latency-us =3D <240>; + exit-latency-us =3D <280>; + min-residency-us =3D <806>; + }; + + cluster_pc: cluster-power-collapse { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x41000053>; + entry-latency-us =3D <700>; + exit-latency-us =3D <1000>; + min-residency-us =3D <6500>; + }; + + cluster_ret: cluster-retention { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x41000023>; + entry-latency-us =3D <700>; + exit-latency-us =3D <650>; + min-residency-us =3D <1972>; + }; + + }; + + idle-states { + entry-method =3D "psci"; + + cpu_sleep_0: cpu-sleep-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "standalone-power-collapse"; + arm,psci-suspend-param =3D <0x40000003>; + entry-latency-us =3D <125>; + exit-latency-us =3D <180>; + min-residency-us =3D <595>; + local-timer-stop; + }; + }; + + l2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + }; + + cpu_opp_table: opp-table-cpu { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-960000000 { + opp-hz =3D /bits/ 64 <960000000>; + }; + + opp-1094400000 { + opp-hz =3D /bits/ 64 <1094400000>; + }; + + opp-1248000000 { + opp-hz =3D /bits/ 64 <1248000000>; + }; + + opp-1401600000 { + opp-hz =3D /bits/ 64 <1401600000>; + }; + }; + }; + + firmware { + scm: scm { + compatible =3D "qcom,scm-msm8916", "qcom,scm"; + clocks =3D <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names =3D "core", "bus", "iface"; + #reset-cells =3D <1>; + + qcom,dload-mode =3D <&tcsr 0x6100>; + }; + }; + + memory@80000000 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the reg */ + reg =3D <0 0x80000000 0 0>; + }; + + pmu { + compatible =3D "arm,cortex-a53-pmu"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + + cluster_pd: power-domain-cluster { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cluster_pwrdn>, <&cluster_ret>, <&cluster_pc>; + }; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cpu_sleep_0>; + }; + + cpu_pd1: power-domain-cpu1 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cpu_sleep_0>; + }; + + cpu_pd2: power-domain-cpu2 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cpu_sleep_0>; + }; + + cpu_pd3: power-domain-cpu3 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&cpu_sleep_0>; + }; + }; + + rpm: remoteproc { + compatible =3D "qcom,msm8917-rpm-proc", "qcom,rpm-proc"; + + smd-edge { + interrupts =3D ; + qcom,ipc =3D <&apcs 8 0>; + qcom,smd-edge =3D <15>; + + rpm_requests: rpm-requests { + compatible =3D "qcom,rpm-msm8917", "qcom,smd-rpm"; + qcom,smd-channels =3D "rpm_requests"; + + rpmcc: clock-controller { + compatible =3D "qcom,rpmcc-msm8917", "qcom,rpmcc"; + #clock-cells =3D <1>; + clocks =3D <&xo_board>; + clock-names =3D "xo"; + }; + + rpmpd: power-controller { + compatible =3D "qcom,msm8917-rpmpd"; + #power-domain-cells =3D <1>; + operating-points-v2 =3D <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level =3D ; + }; + + rpmpd_opp_ret_plus: opp2 { + opp-level =3D ; + }; + + rpmpd_opp_min_svs: opp3 { + opp-level =3D ; + }; + + rpmpd_opp_low_svs: opp4 { + opp-level =3D ; + }; + + rpmpd_opp_svs: opp5 { + opp-level =3D ; + }; + + rpmpd_opp_svs_plus: opp6 { + opp-level =3D ; + }; + + rpmpd_opp_nom: opp7 { + opp-level =3D ; + }; + + rpmpd_opp_nom_plus: opp8 { + opp-level =3D ; + }; + + rpmpd_opp_turbo: opp9 { + opp-level =3D ; + }; + }; + }; + }; + }; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + qseecom_mem: qseecom@85b00000 { + reg =3D <0x0 0x85b00000 0x0 0x800000>; + no-map; + }; + + smem@86300000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0x86300000 0x0 0x100000>; + no-map; + + hwlocks =3D <&tcsr_mutex 3>; + qcom,rpm-msg-ram =3D <&rpm_msg_ram>; + }; + + reserved@86400000 { + reg =3D <0x0 0x86400000 0x0 0x400000>; + no-map; + }; + + mpss_mem: mpss@86800000 { + /* + * The memory region for the mpss firmware is generally + * relocatable and could be allocated dynamically. + * However, many firmware versions tend to fail when + * loaded to some special addresses, so it is hard to + * define reliable alloc-ranges. + * + * alignment =3D <0x0 0x400000>; + * alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + */ + reg =3D <0x0 0x86800000 0x0 0>; /* size is device-specific */ + no-map; + status =3D "disabled"; + }; + + rmtfs@92100000 { + compatible =3D "qcom,rmtfs-mem"; + reg =3D <0x0 0x92100000 0x0 0x180000>; + no-map; + + qcom,client-id =3D <1>; + }; + + adsp_mem: adsp { + size =3D <0x0 0x1100000>; + alignment =3D <0x0 0x100000>; + alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + no-map; + status =3D "disabled"; + }; + + mba_mem: mba { + size =3D <0x0 0x100000>; + alignment =3D <0x0 0x100000>; + alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + no-map; + status =3D "disabled"; + }; + + venus_mem: venus { + size =3D <0x0 0x400000>; + alignment =3D <0x0 0x100000>; + alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + no-map; + status =3D "disabled"; + }; + + wcnss_mem: wcnss { + size =3D <0x0 0x700000>; + alignment =3D <0x0 0x100000>; + alloc-ranges =3D <0x0 0x86800000 0x0 0x8000000>; + no-map; + status =3D "disabled"; + }; + }; + + smp2p-adsp { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <443>, <429>; + + interrupts =3D ; + + mboxes =3D <&apcs 10>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + + #qcom,smem-state-cells =3D <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-modem { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <435>, <428>; + + interrupts =3D ; + + qcom,ipc =3D <&apcs 8 14>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + + #qcom,smem-state-cells =3D <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-wcnss { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <451>, <431>; + + interrupts =3D ; + + qcom,ipc =3D <&apcs 8 18>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <4>; + + wcnss_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + + #qcom,smem-state-cells =3D <1>; + }; + + wcnss_smp2p_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smsm { + compatible =3D "qcom,smsm"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + mboxes =3D <0>, <&apcs 13>, <0>, <&apcs 19>; + + apps_smsm: apps@0 { + reg =3D <0>; + + #qcom,smem-state-cells =3D <1>; + }; + + hexagon_smsm: hexagon@1 { + reg =3D <1>; + interrupts =3D ; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + wcnss_smsm: wcnss@6 { + reg =3D <6>; + interrupts =3D ; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + soc: soc@0 { + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0 0 0xffffffff>; + compatible =3D "simple-bus"; + + rpm_msg_ram: sram@60000 { + compatible =3D "qcom,rpm-msg-ram"; + reg =3D <0x60000 0x8000>; + }; + + usb_hs_phy: phy@6c000 { + compatible =3D "qcom,usb-hs-28nm-femtophy"; + reg =3D <0x6c000 0x200>; + #phy-cells =3D <0>; + clocks =3D <&xo_board>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names =3D "ref", "ahb", "sleep"; + resets =3D <&gcc GCC_QUSB2_PHY_BCR>, + <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; + reset-names =3D "phy", "por"; + status =3D "disabled"; + }; + + qfprom: qfprom@a4000 { + compatible =3D "qcom,msm8917-qfprom", "qcom,qfprom"; + reg =3D <0xa4000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + tsens_base1: base1@1d8 { + reg =3D <0x1d8 1>; + bits =3D <0 8>; + }; + + tsens_s5_p1: s5-p1@1d9 { + reg =3D <0x1d9 1>; + bits =3D <0 6>; + }; + + tsens_s5_p2: s5-p2@1d9 { + reg =3D <0x1d9 2>; + bits =3D <6 6>; + }; + + tsens_s6_p1: s6-p1@1da { + reg =3D <0x1da 2>; + bits =3D <4 6>; + }; + + tsens_s6_p2: s6-p2@1db { + reg =3D <0x1db 1>; + bits =3D <2 6>; + }; + + tsens_s7_p1: s7-p1@1dc { + reg =3D <0x1dc 1>; + bits =3D <0 6>; + }; + + tsens_s7_p2: s7-p2@1dc { + reg =3D <0x1dc 2>; + bits =3D <6 6>; + }; + + tsens_s8_p1: s8-p1@1dd { + reg =3D <0x1dd 2>; + bits =3D <4 6>; + }; + + tsens_s8_p2: s8-p2@1de { + reg =3D <0x1de 1>; + bits =3D <2 6>; + }; + + tsens_base2: base2@1df { + reg =3D <0x1df 1>; + bits =3D <0 8>; + }; + + tsens_mode: mode@210 { + reg =3D <0x210 1>; + bits =3D <0 3>; + }; + + tsens_s0_p1: s0-p1@210 { + reg =3D <0x210 2>; + bits =3D <3 6>; + }; + + tsens_s0_p2: s0-p2@211 { + reg =3D <0x211 1>; + bits =3D <1 6>; + }; + + tsens_s1_p1: s1-p1@211 { + reg =3D <0x211 2>; + bits =3D <7 6>; + }; + + tsens_s1_p2: s1-p2@212 { + reg =3D <0x212 2>; + bits =3D <5 6>; + }; + + tsens_s2_p1: s2-p1@213 { + reg =3D <0x213 2>; + bits =3D <3 6>; + }; + + tsens_s2_p2: s2-p2@214 { + reg =3D <0x214 1>; + bits =3D <1 6>; + }; + + tsens_s3_p1: s3-p1@214 { + reg =3D <0x214 2>; + bits =3D <7 6>; + }; + + tsens_s3_p2: s3-p2@215 { + reg =3D <0x215 2>; + bits =3D <5 6>; + }; + + tsens_s4_p1: s4-p1@216 { + reg =3D <0x216 2>; + bits =3D <3 6>; + }; + + tsens_s4_p2: s4-p2@217 { + reg =3D <0x217 1>; + bits =3D <1 6>; + }; + + tsens_s9_p1: s9-p1@230{ + reg =3D <0x230 1>; + bits =3D <0 6>; + }; + + tsens_s9_p2: s9-p2@230 { + reg =3D <0x230 2>; + bits =3D <6 6>; + }; + + tsens_s10_p1: s10-p1@231 { + reg =3D <0x231 2>; + bits =3D <4 6>; + }; + + tsens_s10_p2: s10-p2@232 { + reg =3D <0x232 1>; + bits =3D <2 6>; + }; + }; + + rng@e3000 { + compatible =3D "qcom,prng"; + reg =3D <0xe3000 0x1000>; + clocks =3D <&gcc GCC_PRNG_AHB_CLK>; + clock-names =3D "core"; + }; + + tsens: thermal-sensor@4a9000 { + compatible =3D "qcom,msm8937-tsens", "qcom,tsens-v1"; + reg =3D <0x4a9000 0x1000>, + <0x4a8000 0x1000>; + interrupts =3D ; + interrupt-names =3D "uplow"; + nvmem-cells =3D <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>, + <&tsens_s10_p1>, <&tsens_s10_p2>; + nvmem-cell-names =3D "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2", + "s10_p1", "s10_p2"; + #qcom,sensors =3D <11>; + #thermal-sensor-cells =3D <1>; + }; + + restart@4ab000 { + compatible =3D "qcom,pshold"; + reg =3D <0x4ab000 0x4>; + }; + + tlmm: pinctrl@1000000 { + compatible =3D "qcom,msm8917-pinctrl"; + reg =3D <0x1000000 0x300000>; + interrupts =3D ; + gpio-controller; + gpio-ranges =3D <&tlmm 0 0 134>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + + blsp1_uart1_default: blsp1-uart1-default-state { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "blsp_uart1"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_uart1_sleep: blsp1-uart1-sleep-state { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_uart2_default: blsp1-uart2-default-state { + pins =3D "gpio4", "gpio5"; + function =3D "blsp_uart2"; + drive-strength =3D <2>; + bias-disable; + }; + + blsp1_uart2_sleep: blsp1-uart2-sleep-state { + pins =3D "gpio4", "gpio5"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + i2c2_default: i2c2-default-state { + pins =3D "gpio6", "gpio7"; + function =3D "blsp_i2c2"; + drive-strength =3D <2>; + bias-disable; + }; + + i2c2_sleep: i2c2-sleep-state { + pins =3D "gpio6", "gpio7"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + i2c3_default: i2c3-default-state { + pins =3D "gpio10", "gpio11"; + function =3D "blsp_i2c3"; + drive-strength =3D <2>; + bias-disable; + }; + + i2c3_sleep: i2c3-sleep-state { + pins =3D "gpio10", "gpio11"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + i2c4_default: i2c4-default-state { + pins =3D "gpio14", "gpio15"; + function =3D "blsp_i2c4"; + drive-strength =3D <2>; + bias-disable; + }; + + i2c4_sleep: i2c4-sleep-state { + pins =3D "gpio14", "gpio15"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + i2c5_default: i2c5-default-state { + pins =3D "gpio18", "gpio19"; + function =3D "blsp_i2c5"; + drive-strength =3D <2>; + bias-disable; + }; + + i2c5_sleep: i2c5-sleep-state { + pins =3D "gpio18", "gpio19"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + sdc1_clk_on: sdc1-clk-on-state { + pins =3D "sdc1_clk"; + bias-disable; + drive-strength =3D <16>; + }; + + sdc1_clk_off: sdc1-clk-off-state { + pins =3D "sdc1_clk"; + bias-disable; + drive-strength =3D <2>; + }; + + sdc1_cmd_on: sdc1-cmd-on-state { + pins =3D "sdc1_cmd"; + bias-disable; + drive-strength =3D <10>; + }; + + sdc1_cmd_off: sdc1-cmd-off-state { + pins =3D "sdc1_cmd"; + bias-disable; + drive-strength =3D <2>; + }; + + sdc1_data_on: sdc1-data-on-state { + pins =3D "sdc1_data"; + bias-pull-up; + drive-strength =3D <10>; + }; + + sdc1_data_off: sdc1-data-off-state { + pins =3D "sdc1_data"; + bias-pull-up; + drive-strength =3D <2>; + }; + + sdc1_rclk_on: sdc1-rclk-on-state { + pins =3D "sdc1_rclk"; + bias-pull-down; + }; + + sdc1_rclk_off: sdc1-rclk-off-state { + pins =3D "sdc1_rclk"; + bias-pull-down; + }; + + sdc2_clk_on: sdc2-clk-on-state { + pins =3D "sdc2_clk"; + drive-strength =3D <16>; + bias-disable; + }; + + sdc2_clk_off: sdc2-clk-off-state { + pins =3D "sdc2_clk"; + bias-disable; + drive-strength =3D <2>; + }; + + sdc2_cmd_on: sdc2-cmd-on-state { + pins =3D "sdc2_cmd"; + bias-pull-up; + drive-strength =3D <10>; + }; + + sdc2_cmd_off: sdc2-cmd-off-state { + pins =3D "sdc2_cmd"; + bias-pull-up; + drive-strength =3D <2>; + }; + + sdc2_cd_on: cd-on-state { + pins =3D "gpio67"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + sdc2_cd_off: cd-off-state { + pins =3D "gpio67"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + sdc2_data_on: sdc2-data-on-state { + pins =3D "sdc2_data"; + bias-pull-up; + drive-strength =3D <10>; + }; + + sdc2_data_off: sdc2-data-off-state { + pins =3D "sdc2_data"; + bias-pull-up; + drive-strength =3D <2>; + }; + + spi3_default: spi3-default-state { + cs-pins { + pins =3D "gpio10"; + function =3D "blsp_spi3"; + drive-strength =3D <2>; + bias-disable; + }; + + spi-pins { + pins =3D "gpio8", "gpio9", "gpio11"; + function =3D "blsp_spi3"; + drive-strength =3D <12>; + bias-disable; + }; + }; + + spi3_sleep: spi3-sleep-state { + cs-pins { + pins =3D "gpio10"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + spi-pins { + pins =3D "gpio8", "gpio9", "gpio11"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + spi6_default: spi6-default-state { + cs0-pins { + pins =3D "gpio47"; + function =3D "blsp_spi6"; + drive-strength =3D <16>; + bias-disable; + }; + + cs1-pins { + pins =3D "gpio22"; + function =3D "blsp_spi6"; + drive-strength =3D <16>; + bias-disable; + }; + + spi-pins { + pins =3D "gpio20", "gpio21", "gpio23"; + function =3D "blsp_spi6"; + drive-strength =3D <16>; + bias-disable; + }; + }; + + spi6_sleep: spi6-sleep-state { + cs0-pins { + pins =3D "gpio47"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + cs1-pins { + pins =3D "gpio22"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + spi-pins { + pins =3D "gpio20", "gpio21", "gpio23"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + wcnss_pin_a: wcnss-active-state { + wcss-wlan-pins { + pins =3D "gpio79", "gpio80"; + function =3D "wcss_wlan"; + drive-strength =3D <6>; + bias-pull-up; + + }; + + wcss-wlan0-pins { + pins =3D "gpio78"; + function =3D "wcss_wlan0"; + drive-strength =3D <6>; + bias-pull-up; + + }; + + wcss-wlan1-pins { + pins =3D "gpio77"; + function =3D "wcss_wlan1"; + drive-strength =3D <6>; + bias-pull-up; + + }; + + wcss-wlan2-pins { + pins =3D "gpio76"; + function =3D "wcss_wlan2"; + drive-strength =3D <6>; + bias-pull-up; + + }; + }; + }; + + gcc: clock-controller@1800000 { + compatible =3D "qcom,gcc-msm8917"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + reg =3D <0x1800000 0x80000>; + clocks =3D <&xo_board>, + <&sleep_clk>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>; + clock-names =3D "xo", + "sleep_clk", + "dsi0pll", + "dsi0pllbyte"; + }; + + tcsr_mutex: hwlock@1905000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x1905000 0x20000>; + #hwlock-cells =3D <1>; + }; + + tcsr: syscon@1937000 { + compatible =3D "qcom,tcsr-msm8917", "syscon"; + reg =3D <0x1937000 0x30000>; + }; + + mdss: display-subsystem@1a00000 { + compatible =3D "qcom,mdss"; + reg =3D <0x1a00000 0x1000>, + <0x1ab0000 0x1040>; + reg-names =3D "mdss_phys", "vbif_phys"; + + power-domains =3D <&gcc MDSS_GDSC>; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names =3D "iface", + "bus", + "vsync"; + + interrupts =3D ; + + interrupt-controller; + #interrupt-cells =3D <1>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + status =3D "disabled"; + + mdp: display-controller@1a01000 { + compatible =3D "qcom,msm8917-mdp5", "qcom,mdp5"; + reg =3D <0x1a01000 0x89000>; + reg-names =3D "mdp_phys"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + power-domains =3D <&gcc MDSS_GDSC>; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names =3D "iface", + "bus", + "core", + "vsync"; + + iommus =3D <&apps_iommu 0x15>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdp5_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + }; + }; + + mdss_dsi0: dsi@1a94000 { + compatible =3D "qcom,mdss-dsi-ctrl"; + reg =3D <0x1a94000 0x300>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + assigned-clocks =3D <&gcc BYTE0_CLK_SRC>, + <&gcc PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + clocks =3D <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + clock-names =3D "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + phys =3D <&mdss_dsi0_phy>; + + operating-points-v2 =3D <&mdss_dsi0_opp_table>; + power-domains =3D <&rpmpd MSM8917_VDDCX>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint =3D <&mdp5_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi0_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-125000000 { + opp-hz =3D /bits/ 64 <125000000>; + required-opps =3D <&rpmpd_opp_svs>; + }; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmpd_opp_nom>; + }; + }; + }; + + mdss_dsi0_phy: phy@1a94a00 { + compatible =3D "qcom,dsi-phy-28nm-8937"; + reg =3D <0x1a94a00 0xd4>, + <0x1a94400 0x280>, + <0x1a94b80 0x30>; + reg-names =3D "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&xo_board>; + clock-names =3D "iface", "ref"; + }; + }; + + apps_iommu: iommu@1e20000 { + #address-cells =3D <1>; + #size-cells =3D <1>; + #iommu-cells =3D <1>; + compatible =3D "qcom,msm8917-iommu", "qcom,msm-iommu-v1"; + ranges =3D <0 0x1e20000 0x20000>; + + clocks =3D <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; + clock-names =3D "iface", "bus"; + + qcom,iommu-secure-id =3D <17>; + + /* VFE */ + iommu-ctx@14000 { + compatible =3D "qcom,msm-iommu-v1-ns"; + reg =3D <0x14000 0x1000>; + interrupts =3D ; + }; + + /* MDP_0 */ + iommu-ctx@15000 { + compatible =3D "qcom,msm-iommu-v1-ns"; + reg =3D <0x15000 0x1000>; + interrupts =3D ; + }; + + /* VENUS_NS */ + iommu-ctx@16000 { + compatible =3D "qcom,msm-iommu-v1-ns"; + reg =3D <0x16000 0x1000>; + interrupts =3D ; + }; + }; + + gpu_iommu: iommu@1f08000 { + #address-cells =3D <1>; + #size-cells =3D <1>; + #iommu-cells =3D <1>; + + compatible =3D "qcom,msm8917-iommu", "qcom,msm-iommu-v1"; + + ranges =3D <0 0x1f08000 0x10000>; + clocks =3D <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_GFX_TCU_CLK>; + clock-names =3D "iface", "bus"; + qcom,iommu-secure-id =3D <18>; + + iommu-ctx@0 { + compatible =3D "qcom,msm-iommu-v2-ns"; + reg =3D <0 0x1000>; + interrupts =3D ; + }; + }; + + gpu: gpu@1c00000 { + compatible =3D "qcom,adreno-306.32", "qcom,adreno"; + reg =3D <0x1c00000 0x20000>; + reg-names =3D "kgsl_3d0_reg_memory"; + interrupts =3D ; + interrupt-names =3D "kgsl_3d0_irq"; + clock-names =3D "core", + "iface", + "mem_iface", + "alt_mem_iface", + "gfx3d"; + clocks =3D <&gcc GCC_OXILI_GFX3D_CLK>, + <&gcc GCC_OXILI_AHB_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_BIMC_GPU_CLK>, + <&gcc GFX3D_CLK_SRC>; + power-domains =3D <&gcc OXILI_GX_GDSC>; + operating-points-v2 =3D <&gpu_opp_table>; + #cooling-cells =3D <2>; + + iommus =3D <&gpu_iommu 0>; + + status =3D "disabled"; + + gpu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-598000000 { + opp-hz =3D /bits/ 64 <598000000>; + }; + + opp-523200000 { + opp-hz =3D /bits/ 64 <523200000>; + }; + + opp-484800000 { + opp-hz =3D /bits/ 64 <484800000>; + }; + + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + }; + + opp-270000000 { + opp-hz =3D /bits/ 64 <270000000>; + }; + + opp-19200000 { + opp-hz =3D /bits/ 64 <19200000>; + }; + }; + }; + + spmi_bus: spmi@200f000 { + compatible =3D "qcom,spmi-pmic-arb"; + reg =3D <0x200f000 0x001000>, + <0x2400000 0x800000>, + <0x2c00000 0x800000>, + <0x3800000 0x200000>, + <0x200a000 0x002100>; + reg-names =3D "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + interrupt-names =3D "periph_irq"; + interrupts =3D ; + qcom,ee =3D <0>; + qcom,channel =3D <0>; + #address-cells =3D <2>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <4>; + }; + + bam_dmux_dma: dma-controller@4044000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x4044000 0x19000>; + interrupts =3D ; + #dma-cells =3D <1>; + qcom,ee =3D <0>; + + num-channels =3D <6>; + qcom,num-ees =3D <1>; + qcom,powered-remotely; + + status =3D "disabled"; + }; + + sdhc_1: mmc@7824900 { + compatible =3D "qcom,sdhci-msm-v4"; + reg =3D <0x7824900 0x500>, + <0x7824000 0x800>; + reg-names =3D "hc", "core"; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", "pwr_irq"; + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>; + clock-names =3D "iface", "core", "xo"; + power-domains =3D <&rpmpd MSM8917_VDDCX>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-ddr-1_8v; + bus-width =3D <8>; + non-removable; + status =3D "disabled"; + }; + + sdhc_2: mmc@7864900 { + compatible =3D "qcom,sdhci-msm-v4"; + reg =3D <0x7864900 0x500>, + <0x7864000 0x800>; + reg-names =3D "hc", "core"; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", "pwr_irq"; + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&xo_board>; + clock-names =3D "iface", "core", "xo"; + power-domains =3D <&rpmpd MSM8917_VDDCX>; + bus-width =3D <4>; + status =3D "disabled"; + }; + + blsp1_dma: dma-controller@7884000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x7884000 0x1f000>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "bam_clk"; + qcom,controlled-remotely; + #dma-cells =3D <1>; + num-channels =3D <12>; + qcom,num-ees =3D <4>; + qcom,ee =3D <0>; + }; + + blsp2_dma: dma-controller@7ac4000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x7ac4000 0x1d000>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "bam_clk"; + qcom,controlled-remotely; + #dma-cells =3D <1>; + num-channels =3D <10>; + qcom,num-ees =3D <4>; + qcom,ee =3D <0>; + }; + + blsp1_uart1: serial@78af000 { + compatible =3D "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg =3D <0x78af000 0x200>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_UART1_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 0>, <&blsp1_dma 1>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp1_uart1_default>; + pinctrl-1 =3D <&blsp1_uart1_sleep>; + pinctrl-names =3D "default", "sleep"; + status =3D "disabled"; + }; + + blsp1_uart2: serial@78b0000 { + compatible =3D "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg =3D <0x78b0000 0x200>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 2>, <&blsp1_dma 3>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&blsp1_uart2_default>; + pinctrl-1 =3D <&blsp1_uart2_sleep>; + pinctrl-names =3D "default", "sleep"; + status =3D "disabled"; + }; + + blsp_i2c2: i2c@78b6000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x78b6000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 6>, <&blsp1_dma 7>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&i2c2_default>; + pinctrl-1 =3D <&i2c2_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp_i2c3: i2c@78b7000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x78b7000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 8>, <&blsp1_dma 9>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&i2c3_default>; + pinctrl-1 =3D <&i2c3_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp_spi3: spi@78b7000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x78b7000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 8>, <&blsp1_dma 9>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&spi3_default>; + pinctrl-1 =3D <&spi3_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp_i2c4: i2c@78b8000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x78b8000 0x500>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp1_dma 10>, <&blsp1_dma 11>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&i2c4_default>; + pinctrl-1 =3D <&i2c4_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp_i2c5: i2c@7af5000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x7af5000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp2_dma 4>, <&blsp2_dma 5>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&i2c5_default>; + pinctrl-1 =3D <&i2c5_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp_spi6: spi@7af6000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x7af6000 0x600>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp2_dma 6>, <&blsp2_dma 7>; + dma-names =3D "tx", "rx"; + pinctrl-0 =3D <&spi6_default>; + pinctrl-1 =3D <&spi6_sleep>; + pinctrl-names =3D "default", "sleep"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + usb: usb@78db000 { + compatible =3D "qcom,ci-hdrc"; + reg =3D <0x78db000 0x200>, + <0x78db200 0x200>; + interrupts =3D , + ; + clocks =3D <&gcc GCC_USB_HS_AHB_CLK>, + <&gcc GCC_USB_HS_SYSTEM_CLK>; + clock-names =3D "iface", "core"; + assigned-clocks =3D <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates =3D <80000000>; + resets =3D <&gcc GCC_USB_HS_BCR>; + reset-names =3D "core"; + phy_type =3D "ulpi"; + dr_mode =3D "otg"; + hnp-disable; + srp-disable; + adp-disable; + ahb-burst-config =3D <0>; + phy-names =3D "usb-phy"; + phys =3D <&usb_hs_phy>; + status =3D "disabled"; + #reset-cells =3D <1>; + }; + + wcnss: remoteproc@a204000 { + compatible =3D "qcom,pronto-v3-pil", "qcom,pronto"; + reg =3D <0xa204000 0x2000>, + <0xa202000 0x1000>, + <0xa21b000 0x3000>; + reg-names =3D "ccu", "dxe", "pmu"; + + memory-region =3D <&wcnss_mem>; + + interrupts-extended =3D <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", "fatal", "ready", "handover", "stop-ack"; + + power-domains =3D <&rpmpd MSM8917_VDDCX>, + <&rpmpd MSM8917_VDDMX>; + power-domain-names =3D "cx", "mx"; + + qcom,smem-states =3D <&wcnss_smp2p_out 0>; + qcom,smem-state-names =3D "stop"; + + pinctrl-0 =3D <&wcnss_pin_a>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + + wcnss_iris: iris { + clocks =3D <&rpmcc RPM_SMD_RF_CLK2>; + clock-names =3D "xo"; + }; + + smd-edge { + interrupts =3D ; + + mboxes =3D <&apcs 17>; + qcom,smd-edge =3D <6>; + qcom,remote-pid =3D <4>; + + label =3D "pronto"; + + wcnss_ctrl: wcnss { + compatible =3D "qcom,wcnss"; + qcom,smd-channels =3D "WCNSS_CTRL"; + + qcom,mmio =3D <&wcnss>; + + wcnss_bt: bluetooth { + compatible =3D "qcom,wcnss-bt"; + }; + + wcnss_wifi: wifi { + compatible =3D "qcom,wcnss-wlan"; + + interrupts =3D , + ; + interrupt-names =3D "tx", "rx"; + + qcom,smem-states =3D <&apps_smsm 10>, <&apps_smsm 9>; + qcom,smem-state-names =3D "tx-enable", + "tx-rings-empty"; + }; + }; + }; + }; + + intc: interrupt-controller@b000000 { + compatible =3D "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells =3D <3>; + reg =3D <0xb000000 0x1000>, + <0xb002000 0x1000>; + }; + + apcs: mailbox@b011000 { + compatible =3D "qcom,msm8939-apcs-kpss-global", "syscon"; + reg =3D <0xb011000 0x1000>; + #mbox-cells =3D <1>; + clocks =3D <&a53pll>, <&gcc GPLL0_EARLY>, <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "pll", "aux", "ref"; + #clock-cells =3D <0>; + }; + + a53pll: clock@b016000 { + compatible =3D "qcom,msm8939-a53pll"; + reg =3D <0xb016000 0x40>; + clocks =3D <&xo_board>; + clock-names =3D "xo"; + #clock-cells =3D <0>; + operating-points-v2 =3D <&pll_opp_table>; + + pll_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-960000000 { + opp-hz =3D /bits/ 64 <960000000>; + }; + + opp-1094400000 { + opp-hz =3D /bits/ 64 <1094400000>; + }; + + opp-1248000000 { + opp-hz =3D /bits/ 64 <1248000000>; + }; + + opp-1401600000 { + opp-hz =3D /bits/ 64 <1401600000>; + }; + }; + }; + + watchdog@b017000 { + compatible =3D "qcom,apss-wdt-qcs404", "qcom,kpss-wdt"; + reg =3D <0xb017000 0x1000>; + clocks =3D <&sleep_clk>; + }; + + timer@b120000 { + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0xb120000 0x1000>; + clock-frequency =3D <19200000>; + + frame@b121000 { + frame-number =3D <0>; + interrupts =3D , + ; + reg =3D <0xb121000 0x1000>, + <0xb122000 0x1000>; + }; + + frame@b123000 { + frame-number =3D <1>; + interrupts =3D ; + reg =3D <0xb123000 0x1000>; + status =3D "disabled"; + }; + + frame@b124000 { + frame-number =3D <2>; + interrupts =3D ; + reg =3D <0xb124000 0x1000>; + status =3D "disabled"; + }; + + frame@b125000 { + frame-number =3D <3>; + interrupts =3D ; + reg =3D <0xb125000 0x1000>; + status =3D "disabled"; + }; + + frame@b126000 { + frame-number =3D <4>; + interrupts =3D ; + reg =3D <0xb126000 0x1000>; + status =3D "disabled"; + }; + + frame@b127000 { + frame-number =3D <5>; + interrupts =3D ; + reg =3D <0xb127000 0x1000>; + status =3D "disabled"; + }; + + frame@b128000 { + frame-number =3D <6>; + interrupts =3D ; + reg =3D <0xb128000 0x1000>; + status =3D "disabled"; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + clock-frequency =3D <19200000>; + }; + + thermal_zones: thermal-zones { + aoss-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 0>; + + trips { + aoss_alert0: trip-point0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + camera-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 3>; + + trips { + camera_alert0: trip-point0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + cpuss1-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 4>; + + cooling-maps { + map0 { + trip =3D <&cpuss1_alert0>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpuss1_crit: cpuss1-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + + cpuss1_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpuss1_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + cpu0-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 5>; + + cooling-maps { + map0 { + trip =3D <&cpu0_alert1>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu0_crit: cpu-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + + cpu0_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu0_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 6>; + + cooling-maps { + map0 { + trip =3D <&cpu1_alert1>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu1_crit: cpu-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + + cpu1_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu1_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 7>; + + cooling-maps { + map0 { + trip =3D <&cpu2_alert1>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu2_crit: cpu-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + + cpu2_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu2_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 8>; + + cooling-maps { + map0 { + trip =3D <&cpu3_alert1>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu3_crit: cpu-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + + cpu3_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + + cpu3_alert1: trip-point1 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + }; + }; + + gpu-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 9>; + + cooling-maps { + map0 { + trip =3D <&gpu_alert>; + cooling-device =3D <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + gpu_crit: gpu-crit { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + + gpu_alert: trip-point0 { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + }; + + }; + + mdm-core-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 1>; + + trips { + mdm_core_alert0: trip-point0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + q6-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 2>; + + trips { + q6_alert0: trip-point0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + }; +}; --=20 2.47.0 From nobody Sun Nov 24 01:31:42 2024 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A64221A4CD; Thu, 7 Nov 2024 17:03:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730998995; cv=none; b=j+gJSAUee2mlSPVSryWIZzEirpiA02rz3n7BvVQUKkzOTbNBpQZJ9W2MaIFvmKO3Tk1tffvlkoZp/2+7u4F/hmJeNNujUtsfOxg0IapUUeuSs0EbFKfjTqFAuu/Ncp4AfvNZ/UpEwWqyXeXqExukTiv/1jfI2LV02Ve6TnFVMXw= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241107-msm8917-v3-13-6ddc5acd978b@mainlining.org> References: <20241107-msm8917-v3-0-6ddc5acd978b@mainlining.org> In-Reply-To: <20241107-msm8917-v3-0-6ddc5acd978b@mainlining.org> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Lee Jones , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Joerg Roedel , Will Deacon , Robin Murphy , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, iommu@lists.linux.dev, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1730998970; l=1345; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=xiFBtHsOaU6w5QYdlsV5ffTJLBo8Uh6SeJeMP9eWLsQ=; b=/P3sK25M5DTGiFrW+nRPnr5FzxDixXjoTU3tSStCfFubCjax+HDOETlgjqhpQBwpOfbwBeoFE hSq7KsQm2FkBw3S+0+0eKQZCr8NTzFxXHvvvOmQ/606XqkGBqDe8gJr X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= Document Xiaomi Remi 5A (riva). Add qcom,msm8917 for msm-id, board-id allow-list. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index 7c8c3a97506aa13a843d5e3408b247eae928a55c..0b4a8c8cdbf7d0b4191b1acdd10= b9b83f2b09542 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -32,6 +32,7 @@ description: | mdm9615 msm8226 msm8916 + msm8917 msm8939 msm8953 msm8956 @@ -252,6 +253,11 @@ properties: - yiming,uz801-v3 - const: qcom,msm8916 =20 + - items: + - enum: + - xiaomi,riva + - const: qcom,msm8917 + - items: - enum: - motorola,potter @@ -1177,6 +1183,7 @@ allOf: - qcom,apq8026 - qcom,apq8094 - qcom,apq8096 + - qcom,msm8917 - qcom,msm8939 - qcom,msm8953 - qcom,msm8956 --=20 2.47.0 From nobody Sun Nov 24 01:31:42 2024 Received: from mail.mainlining.org (mail.mainlining.org [5.75.144.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3819021B434; Thu, 7 Nov 2024 17:03:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.75.144.95 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730998997; cv=none; b=MlJWu0VK8r8QqPE2disNzD9Wj2hlfWqax5usH2+j+uaIxxpZ5rn+Snej5xhOycju6zReAU5tmX7zUon8EIiZRBXvzBUgvvaIzSL/RTmTpl8xSiCBteTWsBUhBM24AVxWDiXm1BJ8Fp6I4Pu/aBXOwuHktArHaJ9NwWL482S9q30= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730998997; c=relaxed/simple; bh=VckbUL31Pd2FcReHeF/sNdgZ3yemo1YK4wGHdefvIng=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LWc7o02OVOJmT4TM8lDCAwaYeZz8paaGUStxHFVnOqa/gJG53FOyYCvEOZBHJKTfBbS2D1OE8xIbd824IUgkUA9hbKXVm71tA44nAQi3q4IUFzZsXKN98RPsyJcSJcX4wxFaanJd/eTVW1mB86Q9rnMlmFmjv/w+iF8fJD//dRk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org; spf=pass smtp.mailfrom=mainlining.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b=Sjcpp4uf; arc=none smtp.client-ip=5.75.144.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mainlining.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mainlining.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mainlining.org header.i=@mainlining.org header.b="Sjcpp4uf" Received: from [192.168.118.162] (254C2715.nat.pool.telekom.hu [37.76.39.21]) by mail.mainlining.org (Postfix) with ESMTPSA id 1672BE45C4; Thu, 7 Nov 2024 17:03:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mainlining.org; s=psm; t=1730998993; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=LrWG6kvrw892Zwuq3FzbeCZoxg7K72awOj8OxMICkAU=; b=Sjcpp4uff0MGuFy0GcaTR0h7tTxQOLfqS+R4vV9dPaSc+tB4hGGLSzABwbtzpre/mpFO0T E0Es8iqK42NoJtX3rZYPAsSDQEtxduqkoPFQYyjr0GEICrExyfpCBSRk4yXOeYt32Omvsl ksrChWYH2evwc2hg5Wld+HyQeHhJpg34NsUt0Gc58nKTXu+APjBB/JgQ9Wks+gwUoBJ6BR ygtQjjdzrUpvk3bkLw4l/gSohsc2ZjE3ojPuqqocPkZOhMtobb1ddzRdz/QipuVO5rqGuq V2y8qSpKVgKce/Y9MC+gtxohIvKow7ab2+AYoV7HUV5w1ZQgAEeD2bturP3N7w== From: =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= Date: Thu, 07 Nov 2024 18:02:55 +0100 Subject: [PATCH v3 14/14] arm64: dts: qcom: Add Xiaomi Redmi 5A Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241107-msm8917-v3-14-6ddc5acd978b@mainlining.org> References: <20241107-msm8917-v3-0-6ddc5acd978b@mainlining.org> In-Reply-To: <20241107-msm8917-v3-0-6ddc5acd978b@mainlining.org> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Lee Jones , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Joerg Roedel , Will Deacon , Robin Murphy , Srinivas Kandagatla Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, iommu@lists.linux.dev, =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1730998970; l=8024; i=barnabas.czeman@mainlining.org; s=20240730; h=from:subject:message-id; bh=VckbUL31Pd2FcReHeF/sNdgZ3yemo1YK4wGHdefvIng=; b=xPC6ajjDXS9lV6uw+TTdZAgzBTANXPg+RHWaZucPeYtV/H5yPVjeaHJuy+WGSwQ3nXINbzwb7 HPggIwL+hn3B9ow0kmCPJl36cmR54U2wl6lZpikZPqO0QTMHYfojWU3 X-Developer-Key: i=barnabas.czeman@mainlining.org; a=ed25519; pk=TWUSIGgwW/Sn4xnX25nw+lszj1AT/A3bzkahn7EhOFc= Add initial support for Xiaomi Redmi 5A (riva). Signed-off-by: Barnab=C3=A1s Cz=C3=A9m=C3=A1n --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/msm8917-xiaomi-riva.dts | 297 +++++++++++++++++++= ++++ 2 files changed, 298 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 9bb8b191aeb517e8f1e3a11bca98a3d0c39c5398..7562406843cfd82397c4844d14a= 22e8bcf4bba74 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -62,6 +62,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-wingtech-wt86518.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-wingtech-wt86528.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-wingtech-wt88047.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-yiming-uz801v3.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D msm8917-xiaomi-riva.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8929-wingtech-wt82918hd.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8939-huawei-kiwi.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8939-longcheer-l9100.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8917-xiaomi-riva.dts b/arch/arm64/= boot/dts/qcom/msm8917-xiaomi-riva.dts new file mode 100644 index 0000000000000000000000000000000000000000..df5fa0d27cde1dabacac98667fd= 6d4b8dd7533a6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8917-xiaomi-riva.dts @@ -0,0 +1,297 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023, Barnabas Czeman + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "msm8917.dtsi" +#include "pm8937.dtsi" + +/delete-node/ &qseecom_mem; + +/ { + model =3D "Xiaomi Redmi 5A (riva)"; + compatible =3D "xiaomi,riva", "qcom,msm8917"; + chassis-type =3D "handset"; + + qcom,msm-id =3D ; + qcom,board-id =3D <0x1000b 2>, <0x2000b 2>; + + battery: battery { + compatible =3D "simple-battery"; + charge-full-design-microamp-hours =3D <3000000>; + energy-full-design-microwatt-hours =3D <11500000>; + constant-charge-current-max-microamp =3D <1000000>; + constant-charge-voltage-max-microvolt =3D <4400000>; + precharge-current-microamp =3D <256000>; + charge-term-current-microamp =3D <60000>; + voltage-min-design-microvolt =3D <3400000>; + }; + + chosen { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + stdout-path =3D "framebuffer0"; + + framebuffer0: framebuffer@90001000 { + compatible =3D "simple-framebuffer"; + reg =3D <0x0 0x90001000 0x0 (720 * 1280 * 3)>; + width =3D <720>; + height =3D <1280>; + stride =3D <(720 * 3)>; + format =3D "r8g8b8"; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + power-domains =3D <&gcc MDSS_GDSC>; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + key-volup { + label =3D "Volume Up"; + linux,code =3D ; + gpios =3D <&tlmm 91 GPIO_ACTIVE_LOW>; + debounce-interval =3D <15>; + }; + }; + + vph_pwr: regulator-vph-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + regulator-always-on; + regulator-boot-on; + }; + + reserved-memory { + qseecom_mem: qseecom@84a00000 { + reg =3D <0x0 0x84a00000 0x0 0x1900000>; + no-map; + }; + + framebuffer_mem: memory@90001000 { + reg =3D <0x0 0x90001000 0x0 (720 * 1280 * 3)>; + no-map; + }; + }; +}; + +&blsp_i2c3 { + status =3D "okay"; + + touchscreen@38 { + compatible =3D "edt,edt-ft5306"; + reg =3D <0x38>; + interrupts-extended =3D <&tlmm 65 IRQ_TYPE_LEVEL_LOW>; + reset-gpios =3D <&tlmm 64 GPIO_ACTIVE_LOW>; + vcc-supply =3D <&pm8937_l10>; + iovcc-supply =3D <&pm8937_l5>; + + touchscreen-size-x =3D <720>; + touchscreen-size-y =3D <1280>; + }; +}; + +&blsp_i2c5 { + status =3D "okay"; + + bq27426@55 { + compatible =3D "ti,bq27426"; + reg =3D <0x55>; + monitored-battery =3D <&battery>; + }; + + bq25601@6b{ + compatible =3D "ti,bq25601"; + reg =3D <0x6b>; + monitored-battery =3D <&battery>; + + interrupt-parent =3D <&tlmm>; + interrupts =3D <61 IRQ_TYPE_EDGE_FALLING>; + + input-voltage-limit-microvolt =3D <4400000>; + input-current-limit-microamp =3D <1000000>; + }; +}; + +&pm8937_resin { + linux,code =3D ; + + status =3D "okay"; +}; + +&rpm_requests { + regulators-0 { + compatible =3D "qcom,rpm-pm8937-regulators"; + + vdd_s1-supply =3D <&vph_pwr>; + vdd_s2-supply =3D <&vph_pwr>; + vdd_s3-supply =3D <&vph_pwr>; + vdd_s4-supply =3D <&vph_pwr>; + + vdd_l1_l19-supply =3D <&pm8937_s3>; + vdd_l2_l23-supply =3D <&pm8937_s3>; + vdd_l3-supply =3D <&pm8937_s3>; + vdd_l4_l5_l6_l7_l16-supply =3D <&pm8937_s4>; + vdd_l8_l11_l12_l17_l22-supply =3D <&vph_pwr>; + vdd_l9_l10_l13_l14_l15_l18-supply =3D <&vph_pwr>; + + pm8937_s1: s1 { + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1225000>; + }; + + pm8937_s3: s3 { + regulator-min-microvolt =3D <1300000>; + regulator-max-microvolt =3D <1300000>; + }; + + pm8937_s4: s4 { + regulator-min-microvolt =3D <2050000>; + regulator-max-microvolt =3D <2050000>; + }; + + pm8937_l2: l2 { + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + }; + + pm8937_l5: l5 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8937_l6: l6 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8937_l7: l7 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8937_l8: l8 { + regulator-min-microvolt =3D <2850000>; + regulator-max-microvolt =3D <2900000>; + }; + + pm8937_l9: l9 { + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8937_l10: l10 { + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <3000000>; + }; + + pm8937_l11: l11 { + regulator-min-microvolt =3D <2950000>; + regulator-max-microvolt =3D <2950000>; + }; + + pm8937_l12: l12 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2950000>; + }; + + pm8937_l13: l13 { + regulator-min-microvolt =3D <3075000>; + regulator-max-microvolt =3D <3075000>; + }; + + pm8937_l14: l14 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8937_l15: l15 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8937_l16: l16 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8937_l17: l17 { + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2900000>; + }; + + pm8937_l19: l19 { + regulator-min-microvolt =3D <1225000>; + regulator-max-microvolt =3D <1350000>; + }; + + pm8937_l22: l22 { + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + }; + + pm8937_l23: l23 { + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + }; + }; + +}; + +&sdhc_1 { + vmmc-supply =3D <&pm8937_l8>; + vqmmc-supply =3D <&pm8937_l5>; + + status =3D "okay"; +}; + +&sdhc_2 { + cd-gpios =3D <&tlmm 67 GPIO_ACTIVE_LOW>; + vmmc-supply =3D <&pm8937_l11>; + vqmmc-supply =3D <&pm8937_l12>; + + status =3D "okay"; +}; + +&sleep_clk { + clock-frequency =3D <32768>; +}; + +&wcnss { + vddpx-supply =3D <&pm8937_l5>; + + status =3D "okay"; +}; + +&wcnss_iris { + compatible =3D "qcom,wcn3620"; + vddxo-supply =3D <&pm8937_l7>; + vddrfa-supply =3D <&pm8937_l19>; + vddpa-supply =3D <&pm8937_l9>; + vdddig-supply =3D <&pm8937_l5>; +}; + +&wcnss_mem { + status =3D "okay"; +}; + +&xo_board { + clock-frequency =3D <19200000>; +}; --=20 2.47.0