From nobody Sun Nov 24 04:32:06 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 15A3117C60; Thu, 7 Nov 2024 01:38:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730943540; cv=none; b=j+KhdQSLd7QuKmWg/K5TtHyPZFfH71RJzoDKjpXhvJ0Ho6NeUtd65+E9WACM7PEPNAg0hLoz7A77gGSgDmeM+lrZ5PjZ1EyQD8PsODpKe0YGWBHmCayhJrdml352YjnKcq7GrdYsWtabkME5hmbT6ua97DannKnDhCYiP03/ITE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730943540; c=relaxed/simple; bh=sHgpnAmwrG4+1gtZ1DoGby2CzV9Xqsof8Foy1rHp9dc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=i62rhCGVFx41pOQcdNucI61AXCfkpZ642YAaV/VOQ8lpOov2iOy7hElFMD8K+sjElud23Fw9J4mTJYyECBW98Q5bch0AoJXm8gdtbqFh8vI2r331gXCN+LJYlqb8cCPN16Xk+TJc/dvlMP8qqiV3kt82Rml2diykE9EgD9bWg3o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZZ5deBSt; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZZ5deBSt" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1396CC4CED3; Thu, 7 Nov 2024 01:38:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1730943539; bh=sHgpnAmwrG4+1gtZ1DoGby2CzV9Xqsof8Foy1rHp9dc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ZZ5deBStt9L4pL1S1PrWBtHcGuaq+NcLPe4RNU2Cglos+sUxS+Y9DQBefw22tGLZz 9urb4h+5fNj9kuD4cyp5ySw4onOUztWCX5zuHLu+AU6BB+/cJ1WsWexbN1oeAZzkkE rHHTwwEemO+dc4h8BBmAn58Oxq/18D5RAU7pBPS9DvsfkQdHyFJkKjFNShSjX0/1Gb WvzR8NCbs2RPwTvP1BpNZk6pGhA8CHAPPzipLk1wh/eWy8LeuvASyvMso3O8jCcvlN caWDuH9arf2jtczKWR3BKNaKD2Y6t6UgTk33WUMIrftCsdHn9UDNmzT7kJhkV2Ryzb jKHQb3zs9Xozw== From: Mark Brown Date: Thu, 07 Nov 2024 01:38:04 +0000 Subject: [PATCH 1/4] kselftets/arm64: Use flag bits for features in fp-ptrace assembler code Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241107-arm64-fp-ptrace-fpmr-v1-1-3e5e0b6e3be9@kernel.org> References: <20241107-arm64-fp-ptrace-fpmr-v1-0-3e5e0b6e3be9@kernel.org> In-Reply-To: <20241107-arm64-fp-ptrace-fpmr-v1-0-3e5e0b6e3be9@kernel.org> To: Catalin Marinas , Will Deacon , Shuah Khan Cc: Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-9b746 X-Developer-Signature: v=1; a=openpgp-sha256; l=5038; i=broonie@kernel.org; h=from:subject:message-id; bh=sHgpnAmwrG4+1gtZ1DoGby2CzV9Xqsof8Foy1rHp9dc=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBnLBosVLcUCeHCcFI93H9y5DQcwWYH0KaO9ZpY9ZuG PYJhcOeJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZywaLAAKCRAk1otyXVSH0BuEB/ kBfDFCsdJlYaLADzG66C/1Ew3Su1ykSAhp0U835snXXbIgvLsGv47hVdCiUAs/flLcnp4u7GWnd1IS uFmAejsXoSKl62Z6gBGsB8kya91sbr6I2buljDCx+G4dYLnFw6+B+ViU3j2Z31UMZaAPq6z5PKlwb9 n+RxtOroqzN3aLvHHUBYW5wZo17pcI1Jjknp2ausrCkMnpcJ27ZsV4USyongTVa0IfRUd0hJeElAkl Bl29S+uG6qkQ07D3uWHLmrExMlI8W/sy5QT5YM38yJ/5iORXzupqEAH8W1SdHtMlWqlGXRDHEnG2l5 rU9RvkgYfiX0KUK7kLK2WxmlH4lhhc X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB The assembler portions of fp-ptrace are passed feature flags by the C code indicating which architectural features are supported. Currently these use an entire register for each flag which is wasteful and gets cumbersome as new flags are added. Switch to using flag bits in a single register to make things easier to maintain. No functional change. Signed-off-by: Mark Brown --- tools/testing/selftests/arm64/fp/fp-ptrace-asm.S | 32 +++++++++++++-------= ---- tools/testing/selftests/arm64/fp/fp-ptrace.c | 17 ++++++++++--- tools/testing/selftests/arm64/fp/fp-ptrace.h | 10 ++++++++ 3 files changed, 41 insertions(+), 18 deletions(-) diff --git a/tools/testing/selftests/arm64/fp/fp-ptrace-asm.S b/tools/testi= ng/selftests/arm64/fp/fp-ptrace-asm.S index 7ad59d92d02b28e4a6b328fde96039329ea8862a..5e7e9c878f2ce797e3ba5f4033a= 42526830393e6 100644 --- a/tools/testing/selftests/arm64/fp/fp-ptrace-asm.S +++ b/tools/testing/selftests/arm64/fp/fp-ptrace-asm.S @@ -15,10 +15,7 @@ =20 // Load and save register values with pauses for ptrace // -// x0 - SVE in use -// x1 - SME in use -// x2 - SME2 in use -// x3 - FA64 supported +// x0 - HAVE_ flags indicating which features are in use =20 .globl load_and_save load_and_save: @@ -44,7 +41,7 @@ load_and_save: ldp q30, q31, [x7, #16 * 30] =20 // SME? - cbz x1, check_sve_in + tbz x0, #HAVE_SME_SHIFT, check_sve_in =20 adrp x7, svcr_in ldr x7, [x7, :lo12:svcr_in] @@ -64,7 +61,7 @@ load_and_save: bne 1b =20 // ZT? - cbz x2, check_sm_in + tbz x0, #HAVE_SME2_SHIFT, check_sm_in adrp x6, zt_in add x6, x6, :lo12:zt_in _ldr_zt 6 @@ -72,12 +69,16 @@ load_and_save: // In streaming mode? check_sm_in: tbz x7, #SVCR_SM_SHIFT, check_sve_in - mov x4, x3 // Load FFR if we have FA64 + + // Load FFR if we have FA64 + mov x4, #0 + tbz x0, #HAVE_FA64_SHIFT, load_sve + mov x4, #1 b load_sve =20 // SVE? check_sve_in: - cbz x0, wait_for_writes + tbz x0, #HAVE_SVE_SHIFT, wait_for_writes mov x4, #1 =20 load_sve: @@ -165,8 +166,7 @@ wait_for_writes: stp q28, q29, [x7, #16 * 28] stp q30, q31, [x7, #16 * 30] =20 - // SME? - cbz x1, check_sve_out + tbz x0, #HAVE_SME_SHIFT, check_sve_out =20 rdsvl 11, 1 adrp x6, sme_vl_out @@ -187,7 +187,7 @@ wait_for_writes: bne 1b =20 // ZT? - cbz x2, check_sm_out + tbz x0, #HAVE_SME2_SHIFT, check_sm_out adrp x6, zt_out add x6, x6, :lo12:zt_out _str_zt 6 @@ -195,12 +195,16 @@ wait_for_writes: // In streaming mode? check_sm_out: tbz x7, #SVCR_SM_SHIFT, check_sve_out - mov x4, x3 // FFR? + + // Do we have FA64 and FFR? + mov x4, #0 + tbz x0, #HAVE_FA64_SHIFT, read_sve + mov x4, #1 b read_sve =20 // SVE? check_sve_out: - cbz x0, wait_for_reads + tbz x0, #HAVE_SVE_SHIFT, wait_for_reads mov x4, #1 =20 rdvl x7, #1 @@ -271,7 +275,7 @@ wait_for_reads: brk #0 =20 // Ensure we don't leave ourselves in streaming mode - cbz x1, out + tbz x0, #HAVE_SME_SHIFT, out msr S3_3_C4_C2_2, xzr =20 out: diff --git a/tools/testing/selftests/arm64/fp/fp-ptrace.c b/tools/testing/s= elftests/arm64/fp/fp-ptrace.c index c7ceafe5f4712b2c93823c1025f3a23ac0594325..d96af27487fa642e94ecc971f53= cb78c233e7b44 100644 --- a/tools/testing/selftests/arm64/fp/fp-ptrace.c +++ b/tools/testing/selftests/arm64/fp/fp-ptrace.c @@ -82,7 +82,7 @@ uint64_t sve_vl_out; uint64_t sme_vl_out; uint64_t svcr_in, svcr_expected, svcr_out; =20 -void load_and_save(int sve, int sme, int sme2, int fa64); +void load_and_save(int flags); =20 static bool got_alarm; =20 @@ -198,7 +198,7 @@ static int vl_expected(struct test_config *config) =20 static void run_child(struct test_config *config) { - int ret; + int ret, flags; =20 /* Let the parent attach to us */ ret =3D ptrace(PTRACE_TRACEME, 0, 0, 0); @@ -224,8 +224,17 @@ static void run_child(struct test_config *config) } =20 /* Load values and wait for the parent */ - load_and_save(sve_supported(), sme_supported(), - sme2_supported(), fa64_supported()); + flags =3D 0; + if (sve_supported()) + flags |=3D HAVE_SVE; + if (sme_supported()) + flags |=3D HAVE_SME; + if (sme2_supported()) + flags |=3D HAVE_SME2; + if (fa64_supported()) + flags |=3D HAVE_FA64; + + load_and_save(flags); =20 exit(0); } diff --git a/tools/testing/selftests/arm64/fp/fp-ptrace.h b/tools/testing/s= elftests/arm64/fp/fp-ptrace.h index db4f2c4d750c5c04e3d257e37a1966296ca74956..36ca627e1980f6a384d9ed0f2e9= d4bd32d90f893 100644 --- a/tools/testing/selftests/arm64/fp/fp-ptrace.h +++ b/tools/testing/selftests/arm64/fp/fp-ptrace.h @@ -10,4 +10,14 @@ #define SVCR_SM (1 << SVCR_SM_SHIFT) #define SVCR_ZA (1 << SVCR_ZA_SHIFT) =20 +#define HAVE_SVE_SHIFT 0 +#define HAVE_SME_SHIFT 1 +#define HAVE_SME2_SHIFT 2 +#define HAVE_FA64_SHIFT 3 + +#define HAVE_SVE (1 << HAVE_SVE_SHIFT) +#define HAVE_SME (1 << HAVE_SME_SHIFT) +#define HAVE_SME2 (1 << HAVE_SME2_SHIFT) +#define HAVE_FA64 (1 << HAVE_FA64_SHIFT) + #endif --=20 2.39.2 From nobody Sun Nov 24 04:32:06 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BBA3B28689; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FcbnYj6p" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0F1E0C4CECC; Thu, 7 Nov 2024 01:38:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1730943541; bh=xEt/GuYUc1T9GgP1WKMvPTj91jfRIyjXPBA0FfOjlmo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=FcbnYj6pNPCownppWPz9g3BOYuf0qtvn8EI/+FXdiefIiTwh6JPdy3yvnIxtbniyY Qo3swFx2VtluDzWQvgH/6YmdZfIkqsVGJaZv8rLZ1gDeRfSg/QeFgoDDCBZs2/qXLu IsoaIndGp2bJcrMDVVcpzwxkPull6XiF3k3YmV0HK7NNPsdR0haoSdggGvo9GtTE9B Syqt9HRiDzc/ZdcPszYNxy2cD/oZ0c22LNPgWsrZQ2WXLxzLczo3aBAfxnr9gwg/g7 8Xcvfeg4d+qPCzGXCLweTlU08bQG1PKELHUf8AkRqzs80HXCF0y+fttOFv+gWRvVjL gdR947cLmVnug== From: Mark Brown Date: Thu, 07 Nov 2024 01:38:05 +0000 Subject: [PATCH 2/4] kselftest/arm64: Use a define for SVCR Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241107-arm64-fp-ptrace-fpmr-v1-2-3e5e0b6e3be9@kernel.org> References: <20241107-arm64-fp-ptrace-fpmr-v1-0-3e5e0b6e3be9@kernel.org> In-Reply-To: <20241107-arm64-fp-ptrace-fpmr-v1-0-3e5e0b6e3be9@kernel.org> To: Catalin Marinas , Will Deacon , Shuah Khan Cc: Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-9b746 X-Developer-Signature: v=1; a=openpgp-sha256; l=9048; i=broonie@kernel.org; h=from:subject:message-id; bh=xEt/GuYUc1T9GgP1WKMvPTj91jfRIyjXPBA0FfOjlmo=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBnLBot0iYhrXXS1NhlawJ/mRd21YVB/8pIGXMBsIab kM7AwVuJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZywaLQAKCRAk1otyXVSH0CnPB/ 4lgz8hA8FciW1nHlseNZvf/8dnW5DCVdcdPYyR8611uKFzozwpy5zD2fYJNhgL9cBx9jTvSnnmjBad 46VGA9vqxoTeri342M0Gf2e4MaHMbu2X0fWVr7CytWvpiJgT8RdNzpAIezh1QDKdlzgOfrpiQM0wFp xXMu88I5h+8wZW5Mufa2INlLMZZ7OdD5xfl4ECC4BXpfqVfHWVii84Aw6/okJ0KnYpBXgU3nZtMfI+ rnLvpMz9mNbG4WZPlO34AJlkAwhtwOW0/GDxvjA6o/wda/qrOb4CIbBp0Q34Yes56DML8qQQ2KNEzd cXNeeZlnOAecoKyFlWqMhEVh+u2ivm X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB For some reason when we're accessing SVCR in the FP tests we use the raw numerical version of the register name rather than hiding that behind a preprocessor macro for readability. Since we already use the generated defines for sysreg bitfields in other the KVM selftests let's do the same thing here, also replacing the defines for the SVCR bitfields which we have. The build setup for fp-ptrace is a little fun so we have to manually define __ASSEMBLY__ in the source code for that. Signed-off-by: Mark Brown --- tools/testing/selftests/arm64/fp/Makefile | 20 +++++++++++++------- tools/testing/selftests/arm64/fp/fp-ptrace-asm.S | 11 ++++++++--- tools/testing/selftests/arm64/fp/fp-ptrace.c | 2 ++ tools/testing/selftests/arm64/fp/fp-ptrace.h | 6 +----- tools/testing/selftests/arm64/fp/sve-test.S | 5 +++-- tools/testing/selftests/arm64/fp/za-fork-asm.S | 3 ++- tools/testing/selftests/arm64/fp/za-test.S | 6 ++++-- tools/testing/selftests/arm64/fp/zt-test.S | 5 +++-- 8 files changed, 36 insertions(+), 22 deletions(-) diff --git a/tools/testing/selftests/arm64/fp/Makefile b/tools/testing/self= tests/arm64/fp/Makefile index d171021e4cdd1a880f842c7d58b1b149e79e4794..da808074e6ca9388c0ab7a71663= 2742d1a8acbf4 100644 --- a/tools/testing/selftests/arm64/fp/Makefile +++ b/tools/testing/selftests/arm64/fp/Makefile @@ -3,7 +3,13 @@ # A proper top_srcdir is needed by KSFT(lib.mk) top_srcdir =3D $(realpath ../../../../../) =20 -CFLAGS +=3D $(KHDR_INCLUDES) +ARCH_TOOLS_INCLUDES=3D\ + -I${top_srcdir}/tools/include \ + -I${top_srcdir}/tools/arch/arm64/include \ + -I${top_srcdir}/tools/arch/arm64/include/generated + +CFLAGS +=3D $(KHDR_INCLUDES) $(ARCH_TOOLS_INCLUDES) +ASFLAGS +=3D -D__ASSEMBLY__ $(ARCH_TOOLS_INCLUDES) =20 TEST_GEN_PROGS :=3D \ fp-ptrace \ @@ -26,18 +32,18 @@ EXTRA_CLEAN +=3D $(OUTPUT)/asm-utils.o $(OUTPUT)/rdvl.o= $(OUTPUT)/za-fork-asm.o =20 # Build with nolibc to avoid effects due to libc's clone() support $(OUTPUT)/fp-pidbench: fp-pidbench.S $(OUTPUT)/asm-utils.o - $(CC) -nostdlib $^ -o $@ + $(CC) $(ASFLAGS) -nostdlib $^ -o $@ $(OUTPUT)/fp-ptrace: fp-ptrace.c fp-ptrace-asm.S $(OUTPUT)/fpsimd-test: fpsimd-test.S $(OUTPUT)/asm-utils.o - $(CC) -nostdlib $^ -o $@ + $(CC) $(ASFLAGS) -nostdlib $^ -o $@ $(OUTPUT)/rdvl-sve: rdvl-sve.c $(OUTPUT)/rdvl.o $(OUTPUT)/rdvl-sme: rdvl-sme.c $(OUTPUT)/rdvl.o $(OUTPUT)/sve-ptrace: sve-ptrace.c $(OUTPUT)/sve-probe-vls: sve-probe-vls.c $(OUTPUT)/rdvl.o $(OUTPUT)/sve-test: sve-test.S $(OUTPUT)/asm-utils.o - $(CC) -nostdlib $^ -o $@ + $(CC) $(ASFLAGS) -nostdlib $^ -o $@ $(OUTPUT)/ssve-test: sve-test.S $(OUTPUT)/asm-utils.o - $(CC) -DSSVE -nostdlib $^ -o $@ + $(CC) -DSSVE $(ASFLAGS) -nostdlib $^ -o $@ $(OUTPUT)/vec-syscfg: vec-syscfg.c $(OUTPUT)/rdvl.o $(OUTPUT)/vlset: vlset.c $(OUTPUT)/za-fork: za-fork.c $(OUTPUT)/za-fork-asm.o @@ -46,9 +52,9 @@ $(OUTPUT)/za-fork: za-fork.c $(OUTPUT)/za-fork-asm.o -static -ffreestanding -Wall $^ -o $@ $(OUTPUT)/za-ptrace: za-ptrace.c $(OUTPUT)/za-test: za-test.S $(OUTPUT)/asm-utils.o - $(CC) -nostdlib $^ -o $@ + $(CC) $(ASFLAGS) -nostdlib $^ -o $@ $(OUTPUT)/zt-ptrace: zt-ptrace.c $(OUTPUT)/zt-test: zt-test.S $(OUTPUT)/asm-utils.o - $(CC) -nostdlib $^ -o $@ + $(CC) $(ASFLAGS) -nostdlib $^ -o $@ =20 include ../../lib.mk diff --git a/tools/testing/selftests/arm64/fp/fp-ptrace-asm.S b/tools/testi= ng/selftests/arm64/fp/fp-ptrace-asm.S index 5e7e9c878f2ce797e3ba5f4033a42526830393e6..4a9242296ef75cf1a83ec561cda= 11a31e9f69bd4 100644 --- a/tools/testing/selftests/arm64/fp/fp-ptrace-asm.S +++ b/tools/testing/selftests/arm64/fp/fp-ptrace-asm.S @@ -8,6 +8,11 @@ // break on a further breakpoint // =20 +/* The build system is dumb and doesn't do this for us */ +#define __ASSEMBLY__ + +#include + #include "fp-ptrace.h" #include "sme-inst.h" =20 @@ -47,7 +52,7 @@ load_and_save: ldr x7, [x7, :lo12:svcr_in] // SVCR is 0 by default, avoid triggering SME if not in use cbz x7, check_sve_in - msr S3_3_C4_C2_2, x7 + msr REG_SVCR, x7 =20 // ZA? tbz x7, #SVCR_ZA_SHIFT, check_sm_in @@ -172,7 +177,7 @@ wait_for_writes: adrp x6, sme_vl_out str x11, [x6, :lo12:sme_vl_out] =20 - mrs x7, S3_3_C4_C2_2 + mrs x7, REG_SVCR adrp x6, svcr_out str x7, [x6, :lo12:svcr_out] =20 @@ -276,7 +281,7 @@ wait_for_reads: =20 // Ensure we don't leave ourselves in streaming mode tbz x0, #HAVE_SME_SHIFT, out - msr S3_3_C4_C2_2, xzr + msr REG_SVCR, xzr =20 out: ldp x11, x12, [sp, #-0x10] diff --git a/tools/testing/selftests/arm64/fp/fp-ptrace.c b/tools/testing/s= elftests/arm64/fp/fp-ptrace.c index d96af27487fa642e94ecc971f53cb78c233e7b44..22d52a75ac9687673c4354f66ab= cf7204ce17875 100644 --- a/tools/testing/selftests/arm64/fp/fp-ptrace.c +++ b/tools/testing/selftests/arm64/fp/fp-ptrace.c @@ -27,6 +27,8 @@ #include #include =20 +#include + #include "../../kselftest.h" =20 #include "fp-ptrace.h" diff --git a/tools/testing/selftests/arm64/fp/fp-ptrace.h b/tools/testing/s= elftests/arm64/fp/fp-ptrace.h index 36ca627e1980f6a384d9ed0f2e9d4bd32d90f893..a3849817cf4ee23879da835cb7f= 66821b5e09bd0 100644 --- a/tools/testing/selftests/arm64/fp/fp-ptrace.h +++ b/tools/testing/selftests/arm64/fp/fp-ptrace.h @@ -4,11 +4,7 @@ #ifndef FP_PTRACE_H #define FP_PTRACE_H =20 -#define SVCR_SM_SHIFT 0 -#define SVCR_ZA_SHIFT 1 - -#define SVCR_SM (1 << SVCR_SM_SHIFT) -#define SVCR_ZA (1 << SVCR_ZA_SHIFT) +#include =20 #define HAVE_SVE_SHIFT 0 #define HAVE_SME_SHIFT 1 diff --git a/tools/testing/selftests/arm64/fp/sve-test.S b/tools/testing/se= lftests/arm64/fp/sve-test.S index fff60e2a25addfd4850ef71aa3cf6535ac880ffd..20da6398f98afaa410d81b2d776= 643b4d7716f35 100644 --- a/tools/testing/selftests/arm64/fp/sve-test.S +++ b/tools/testing/selftests/arm64/fp/sve-test.S @@ -10,6 +10,7 @@ // (leave it running for as long as you want...) // kill $pids =20 +#include #include #include "assembler.h" #include "asm-offsets.h" @@ -474,7 +475,7 @@ function _start // svc #0 =20 #ifdef SSVE - mrs x0, S3_3_C4_C2_2 // SVCR should have ZA=3D0,SM=3D1 + mrs x0, REG_SVCR // SVCR should have ZA=3D0,SM=3D1 and x1, x0, #3 cmp x1, #1 b.ne svcr_barf @@ -516,7 +517,7 @@ function barf mov x12, x2 // data size =20 #ifdef SSVE - mrs x13, S3_3_C4_C2_2 + mrs x13, REG_SVCR #endif =20 puts "Mismatch: PID=3D" diff --git a/tools/testing/selftests/arm64/fp/za-fork-asm.S b/tools/testing= /selftests/arm64/fp/za-fork-asm.S index 2fafadd491c326a31d6193551d6b26835ac7ade0..13d882ec40f2f5ab9fb6ab776e9= a3e498594680d 100644 --- a/tools/testing/selftests/arm64/fp/za-fork-asm.S +++ b/tools/testing/selftests/arm64/fp/za-fork-asm.S @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only // Copyright (C) 2021 ARM Limited. =20 +#include #include "sme-inst.h" =20 .arch_extension sve @@ -35,7 +36,7 @@ fork_test: .globl verify_fork verify_fork: // SVCR should have ZA=3D1, SM=3D0 - mrs x0, S3_3_C4_C2_2 + mrs x0, REG_SVCR and x1, x0, #3 cmp x1, #2 beq 1f diff --git a/tools/testing/selftests/arm64/fp/za-test.S b/tools/testing/sel= ftests/arm64/fp/za-test.S index 095b45531640966e685408057c08ada67e68998b..fc8e1f47d6463efd8e59221b14b= 2502e960e64c4 100644 --- a/tools/testing/selftests/arm64/fp/za-test.S +++ b/tools/testing/selftests/arm64/fp/za-test.S @@ -10,6 +10,8 @@ // (leave it running for as long as you want...) // kill $pids =20 + +#include #include #include "assembler.h" #include "asm-offsets.h" @@ -305,7 +307,7 @@ function _start 1: svc #0 =20 - mrs x0, S3_3_C4_C2_2 // SVCR should have ZA=3D1,SM=3D0 + mrs x0, REG_SVCR // SVCR should have ZA=3D1,SM=3D0 and x1, x0, #3 cmp x1, #2 b.ne svcr_barf @@ -334,7 +336,7 @@ function barf // svc #0 // end hack =20 - mrs x13, S3_3_C4_C2_2 + mrs x13, REG_SVCR =20 smstop mov x10, x0 // expected data diff --git a/tools/testing/selftests/arm64/fp/zt-test.S b/tools/testing/sel= ftests/arm64/fp/zt-test.S index b5c81e81a37946c1bffe810568855939e9ceb08e..0066ba3d5818beda9901bead872= 5d3909714ddeb 100644 --- a/tools/testing/selftests/arm64/fp/zt-test.S +++ b/tools/testing/selftests/arm64/fp/zt-test.S @@ -6,6 +6,7 @@ // Repeatedly writes unique test patterns into ZT0 // and reads them back to verify integrity. =20 +#include #include #include "assembler.h" #include "asm-offsets.h" @@ -244,7 +245,7 @@ function _start mov x8, #__NR_sched_yield // Encourage preemption svc #0 =20 - mrs x0, S3_3_C4_C2_2 // SVCR should have ZA=3D1,SM=3D0 + mrs x0, REG_SVCR // SVCR should have ZA=3D1,SM=3D0 and x1, x0, #3 cmp x1, #2 b.ne svcr_barf @@ -268,7 +269,7 @@ function barf // svc #0 // end hack =20 - mrs x13, S3_3_C4_C2_2 + mrs x13, REG_SVCR smstop mov x10, x0 // expected data mov x11, x1 // actual data --=20 2.39.2 From nobody Sun Nov 24 04:32:06 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F9D96EB4C; Thu, 7 Nov 2024 01:39:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730943544; cv=none; b=tDlewKc0x6v6ZLFHNAQ7zqFVPvjYjgMVqILcpPYJJc4eCMurBWzDPdd6lCsYoKpgbSJEu7jcDDtqLbNFdXV4S6i9Snx4tM/fjH7tlrDFLfytWKsxfk4S/brWZguDM5TDpCkSDFZKZY+jx/G2od+5aLTlJD1wGmO1gXV9RadFETg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730943544; c=relaxed/simple; bh=KklDMIgTg/IOEK6oxdwvdnPBCakPUdGsPPh8gcrBzcE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sAQT0C7ughLtj3do/tV0sGQ/kMFIK1JsuKjyfPCi5TYYkfRBGRKfa7lZb+/xPpTFR364lCKrSXS1x2fz3daSZUryx474KaX+bPKORFWmgolMkRnguHiXegu1SsAigFEautouh1Xyze4wPDMEMgndrHOC2PXZx8i7MqjX/P4Vox8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=UihTm/GH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="UihTm/GH" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 13874C4CEC6; Thu, 7 Nov 2024 01:39:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1730943543; bh=KklDMIgTg/IOEK6oxdwvdnPBCakPUdGsPPh8gcrBzcE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=UihTm/GHRtLziJ5MHQKpNiGQVbYwHV4s7wXIXepK/uTo3Hcu4gdAqhS6M/WfR/vM8 /z3TGvCgxn/ebUpIcQtmJ/jLqqgtdplkymYX6HA2fdZj3vyu5gK6kncipxyjJ90SmV 7kXRkjOLDYSazv0BRB8jEU4tsJ3FvM0uiHiYm8mvnrDLSgkKB35OtqbFe4Feq8a2RG ZL6gYFybgHgvb/n9QoxiOvcvwyTMHBrIg5sbyT0wmN9or6yNnes0lSN+ng4XjlT15k tJSVtN67TK21bf6pwh+MSVyUJHHDGoXSou7ND8daNQcobAKlM3oTERj7x/EAO1PJ54 5Nm4O81+qbbpg== From: Mark Brown Date: Thu, 07 Nov 2024 01:38:06 +0000 Subject: [PATCH 3/4] kselftest/arm64: Expand the set of ZA writes fp-ptrace does Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241107-arm64-fp-ptrace-fpmr-v1-3-3e5e0b6e3be9@kernel.org> References: <20241107-arm64-fp-ptrace-fpmr-v1-0-3e5e0b6e3be9@kernel.org> In-Reply-To: <20241107-arm64-fp-ptrace-fpmr-v1-0-3e5e0b6e3be9@kernel.org> To: Catalin Marinas , Will Deacon , Shuah Khan Cc: Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-9b746 X-Developer-Signature: v=1; a=openpgp-sha256; l=1674; i=broonie@kernel.org; h=from:subject:message-id; bh=KklDMIgTg/IOEK6oxdwvdnPBCakPUdGsPPh8gcrBzcE=; b=owGbwMvMwMWocq27KDak/QLjabUkhnQdKb0Q/VNPg0Pm2klw5ssbN95+tDtay8dsohPz91d7387x +prTyWjMwsDIxSArpsiy9lnGqvRwia3zH81/BTOIlQlkCgMXpwBMpK+B/Z99llzGdrcXVg7+HX/mn6 /e8K6TaUe/l2bCVFHD1bXaOS9tivgbuTfPf3ov66HptM6ohUuTeEPe39z51jfo02OWlUt3xGl4XT6n MEtVeqf5RqvUAA7eGVUFWgrN15gdWHW1bnoeytsckHpw2crysx5NnTdl9XYskGRdWFj4MOGzh/7Uaw wtp+2FP1hZ7I2Yl97s8iHQRFU5avHB4vAXTFlFsYXP5wg/F81fGGWuyZ7wPbxsZWphyJQLzKG6qu+O x0tecV7bvqItqmTR1oyct3tFmOb1Vn903cDufnlW/rsTFmEHl6+SCGSb++cIczRzn3/UVIFv0stS+z m7rRv4Wa+t2ySctObrvO2S8gK2AA== X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Currently our test for implementable ZA writes is written in a bit of a convoluted fashion which excludes all changes where we clear SVCR.SM even though we can actually support that since changing the vector length resets SVCR. Make the logic more direct, enabling us to actually run these cases. Signed-off-by: Mark Brown --- tools/testing/selftests/arm64/fp/fp-ptrace.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/tools/testing/selftests/arm64/fp/fp-ptrace.c b/tools/testing/s= elftests/arm64/fp/fp-ptrace.c index 22d52a75ac9687673c4354f66abcf7204ce17875..a35dc6d8f82af47bf6adedba7e6= 9a6577ee9f7de 100644 --- a/tools/testing/selftests/arm64/fp/fp-ptrace.c +++ b/tools/testing/selftests/arm64/fp/fp-ptrace.c @@ -1080,21 +1080,19 @@ static void sve_write(pid_t child, struct test_conf= ig *config) =20 static bool za_write_supported(struct test_config *config) { - if (config->svcr_expected & SVCR_SM) { - if (!(config->svcr_in & SVCR_SM)) + if (config->sme_vl_in !=3D config->sme_vl_expected) { + /* Changing the SME VL exits streaming mode. */ + if (config->svcr_expected & SVCR_SM) { return false; - - /* Changing the SME VL exits streaming mode */ - if (config->sme_vl_in !=3D config->sme_vl_expected) { + } + } else { + /* Otherwise we can't change streaming mode */ + if ((config->svcr_in & SVCR_SM) !=3D + (config->svcr_expected & SVCR_SM)) { return false; } } =20 - /* Can't disable SM outside a VL change */ - if ((config->svcr_in & SVCR_SM) && - !(config->svcr_expected & SVCR_SM)) - return false; - return true; } =20 --=20 2.39.2 From nobody Sun Nov 24 04:32:06 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 94740143C69; Thu, 7 Nov 2024 01:39:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730943546; cv=none; b=j8PQaHY3y1LN+bvqAF/7Mj9EalC4PM6TyoJm0iZ1jmqd/FrMtro8PNIolKt0eAHp29hgl9LZ9J7w0RhTlbk7+XirZM350dNj6+CloZP0fzqa1ZuI8LJuUWjrM902HhuMJcGHtUifWvTlYTRABlNVRkO2dbAnaAPDVKOz6Mmr1dI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730943546; c=relaxed/simple; bh=AvfdUHt4SQuoQ2J04ipwQPtmRhlm71W6ng8XXWEK82g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sPfY4p4WBb7TnKIaOlgJ554t+ZIJbaKEarvANYdaDTI/g65jS4bKRyOJhmgMVA+B9cl9X56TpuGS2JhOMLNovodZIyencZmRSAbsNC8MugZ5zCsbHqGnJMqYCiU4hRa1mHeh5waX87klFFkCJV6h0g6cWnNMSfZznpePE0cIjQM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tHMljWkB; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tHMljWkB" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2541FC4CECC; Thu, 7 Nov 2024 01:39:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1730943546; bh=AvfdUHt4SQuoQ2J04ipwQPtmRhlm71W6ng8XXWEK82g=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=tHMljWkBPI2SCqvPL/EMb4S9H+DWsn6YMSzVcoi2SoMmIOdw0RrpgHDVSwvvI/Zhn QGX+rGmnZ2HPv3dfKtqMN02YEBM553pZ54Fucevd1f/9nDZg2l3PRU6dx3saWf339R DFF4I8o+92Ct3JkkxkQfMoupMNvNMlptQjnVZmNQRKzH04aawR5MCC3gbYPoWbSk/Q UmSoxMXef/NHnV+VCOrByeE+pHzj2w4RBmRBH5zSoXO+dzVUS6hO5shq6hZb0cME13 UQomXyH29jpewNPFJAC628idZ+Mhha1lz3GVSVxJC3VO5O8uqa2XLXUmJuXaf6ajt4 ZeU/k0d+O7DlQ== From: Mark Brown Date: Thu, 07 Nov 2024 01:38:07 +0000 Subject: [PATCH 4/4] kselftest/arm64: Add FPMR coverage to fp-ptrace Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241107-arm64-fp-ptrace-fpmr-v1-4-3e5e0b6e3be9@kernel.org> References: <20241107-arm64-fp-ptrace-fpmr-v1-0-3e5e0b6e3be9@kernel.org> In-Reply-To: <20241107-arm64-fp-ptrace-fpmr-v1-0-3e5e0b6e3be9@kernel.org> To: Catalin Marinas , Will Deacon , Shuah Khan Cc: Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-9b746 X-Developer-Signature: v=1; a=openpgp-sha256; l=9267; i=broonie@kernel.org; h=from:subject:message-id; bh=AvfdUHt4SQuoQ2J04ipwQPtmRhlm71W6ng8XXWEK82g=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBnLBovl35MBXeoYycpA4o04Wersh+02idNHyCXuSne 65zpa+qJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZywaLwAKCRAk1otyXVSH0M5/B/ wIppYByRrA4iVVTVno97ME/7h9kZX7ztzmdd2zDga5nBAWwJNB34tg31nyZEK0hKv8HgA/mRvy789k LotZQhDDraEWN/i5SXWp11Y96VQvcUCR/nMCFlXPo0RyvAcR+fVVP968LiSCDJKJ9HjAK/J7QPIBM1 xKrVSUUoVHNtMwL688K1TJRYoUnoHambmbsT/zOhOW05ZAzgrbuh7XDMcMdEdJ816Iw7wtdRZO8n8A FLtDUKr151rm1rg7WfUKSvMQnwmGl55GzlHdHPbCt8m6gB4hV2A6t34i+StV6XBQGVnY7dWD2UgjHe qIhDdi4bwf0xqlVOlB9Fa3J1FfDvoN X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Add coverage for FPMR to fp-ptrace. FPMR can be available independently of SVE and SME, if SME is supported then FPMR is cleared by entering and exiting streaming mode. As with other registers we generate random values to load into the register, we restrict these to bitfields which are always defined. We also leave bitfields where the valid values are affected by the set of supported FP8 formats zero to reduce complexity, it is unlikely that specific bitfields will be affected by ptrace issues. Signed-off-by: Mark Brown --- tools/testing/selftests/arm64/fp/fp-ptrace-asm.S | 23 +++-- tools/testing/selftests/arm64/fp/fp-ptrace.c | 118 +++++++++++++++++++= ++++ tools/testing/selftests/arm64/fp/fp-ptrace.h | 2 + 3 files changed, 136 insertions(+), 7 deletions(-) diff --git a/tools/testing/selftests/arm64/fp/fp-ptrace-asm.S b/tools/testi= ng/selftests/arm64/fp/fp-ptrace-asm.S index 4a9242296ef75cf1a83ec561cda11a31e9f69bd4..5c4cf6da2a79702f424f4beaf2f= 91b2ee6067eff 100644 --- a/tools/testing/selftests/arm64/fp/fp-ptrace-asm.S +++ b/tools/testing/selftests/arm64/fp/fp-ptrace-asm.S @@ -76,14 +76,12 @@ check_sm_in: tbz x7, #SVCR_SM_SHIFT, check_sve_in =20 // Load FFR if we have FA64 - mov x4, #0 - tbz x0, #HAVE_FA64_SHIFT, load_sve - mov x4, #1 + ubfx x4, x0, #HAVE_FA64_SHIFT, #1 b load_sve =20 // SVE? check_sve_in: - tbz x0, #HAVE_SVE_SHIFT, wait_for_writes + tbz x0, #HAVE_SVE_SHIFT, check_fpmr_in mov x4, #1 =20 load_sve: @@ -148,6 +146,13 @@ load_sve: ldr p14, [x7, #14, MUL VL] ldr p15, [x7, #15, MUL VL] =20 + // This has to come after we set PSTATE.SM +check_fpmr_in: + tbz x0, #HAVE_FPMR_SHIFT, wait_for_writes + adrp x7, fpmr_in + ldr x7, [x7, :lo12:fpmr_in] + msr FPMR, x7 + wait_for_writes: // Wait for the parent brk #0 @@ -171,6 +176,12 @@ wait_for_writes: stp q28, q29, [x7, #16 * 28] stp q30, q31, [x7, #16 * 30] =20 + tbz x0, #HAVE_FPMR_SHIFT, check_sme_out + mrs x7, REG_FPMR + adrp x6, fpmr_out + str x7, [x6, :lo12:fpmr_out] + +check_sme_out: tbz x0, #HAVE_SME_SHIFT, check_sve_out =20 rdsvl 11, 1 @@ -202,9 +213,7 @@ check_sm_out: tbz x7, #SVCR_SM_SHIFT, check_sve_out =20 // Do we have FA64 and FFR? - mov x4, #0 - tbz x0, #HAVE_FA64_SHIFT, read_sve - mov x4, #1 + ubfx x4, x0, #HAVE_FA64_SHIFT, #1 b read_sve =20 // SVE? diff --git a/tools/testing/selftests/arm64/fp/fp-ptrace.c b/tools/testing/s= elftests/arm64/fp/fp-ptrace.c index a35dc6d8f82af47bf6adedba7e69a6577ee9f7de..14e88f867fb02784afe61a01873= ae2676c869e8a 100644 --- a/tools/testing/selftests/arm64/fp/fp-ptrace.c +++ b/tools/testing/selftests/arm64/fp/fp-ptrace.c @@ -50,11 +50,22 @@ #define NT_ARM_ZT 0x40d #endif =20 +#ifndef NT_ARM_FPMR +#define NT_ARM_FPMR 0x40e +#endif + #define ARCH_VQ_MAX 256 =20 /* VL 128..2048 in powers of 2 */ #define MAX_NUM_VLS 5 =20 +/* + * FPMR bits we can set without doing feature checks to see if values + * are valid. + */ +#define FPMR_SAFE_BITS (FPMR_LSCALE2_MASK | FPMR_NSCALE_MASK | \ + FPMR_LSCALE_MASK | FPMR_OSC_MASK | FPMR_OSM_MASK) + #define NUM_FPR 32 __uint128_t v_in[NUM_FPR]; __uint128_t v_expected[NUM_FPR]; @@ -80,6 +91,8 @@ char zt_in[ZT_SIG_REG_BYTES]; char zt_expected[ZT_SIG_REG_BYTES]; char zt_out[ZT_SIG_REG_BYTES]; =20 +uint64_t fpmr_in, fpmr_expected, fpmr_out; + uint64_t sve_vl_out; uint64_t sme_vl_out; uint64_t svcr_in, svcr_expected, svcr_out; @@ -130,6 +143,11 @@ static bool fa64_supported(void) return getauxval(AT_HWCAP2) & HWCAP2_SME_FA64; } =20 +static bool fpmr_supported(void) +{ + return getauxval(AT_HWCAP2) & HWCAP2_FPMR; +} + static bool compare_buffer(const char *name, void *out, void *expected, size_t size) { @@ -235,6 +253,8 @@ static void run_child(struct test_config *config) flags |=3D HAVE_SME2; if (fa64_supported()) flags |=3D HAVE_FA64; + if (fpmr_supported()) + flags |=3D HAVE_FPMR; =20 load_and_save(flags); =20 @@ -323,6 +343,14 @@ static void read_child_regs(pid_t child) iov_child.iov_len =3D sizeof(zt_out); read_one_child_regs(child, "ZT", &iov_parent, &iov_child); } + + if (fpmr_supported()) { + iov_parent.iov_base =3D &fpmr_out; + iov_parent.iov_len =3D sizeof(fpmr_out); + iov_child.iov_base =3D &fpmr_out; + iov_child.iov_len =3D sizeof(fpmr_out); + read_one_child_regs(child, "FPMR", &iov_parent, &iov_child); + } } =20 static bool continue_breakpoint(pid_t child, @@ -597,6 +625,26 @@ static bool check_ptrace_values_zt(pid_t child, struct= test_config *config) return compare_buffer("initial ZT", buf, zt_in, ZT_SIG_REG_BYTES); } =20 +static bool check_ptrace_values_fpmr(pid_t child, struct test_config *conf= ig) +{ + uint64_t val; + struct iovec iov; + int ret; + + if (!fpmr_supported()) + return true; + + iov.iov_base =3D &val; + iov.iov_len =3D sizeof(val); + ret =3D ptrace(PTRACE_GETREGSET, child, NT_ARM_FPMR, &iov); + if (ret !=3D 0) { + ksft_print_msg("Failed to read initial FPMR: %s (%d)\n", + strerror(errno), errno); + return false; + } + + return compare_buffer("initial FPMR", &val, &fpmr_in, sizeof(val)); +} =20 static bool check_ptrace_values(pid_t child, struct test_config *config) { @@ -631,6 +679,9 @@ static bool check_ptrace_values(pid_t child, struct tes= t_config *config) if (!check_ptrace_values_zt(child, config)) pass =3D false; =20 + if (!check_ptrace_values_fpmr(child, config)) + pass =3D false; + return pass; } =20 @@ -834,11 +885,18 @@ static void set_initial_values(struct test_config *co= nfig) { int vq =3D __sve_vq_from_vl(vl_in(config)); int sme_vq =3D __sve_vq_from_vl(config->sme_vl_in); + bool sm_change; =20 svcr_in =3D config->svcr_in; svcr_expected =3D config->svcr_expected; svcr_out =3D 0; =20 + if (sme_supported() && + (svcr_in & SVCR_SM) !=3D (svcr_expected & SVCR_SM)) + sm_change =3D true; + else + sm_change =3D false; + fill_random(&v_in, sizeof(v_in)); memcpy(v_expected, v_in, sizeof(v_in)); memset(v_out, 0, sizeof(v_out)); @@ -885,6 +943,21 @@ static void set_initial_values(struct test_config *con= fig) memset(zt_expected, 0, ZT_SIG_REG_BYTES); memset(zt_out, 0, sizeof(zt_out)); } + + if (fpmr_supported()) { + fill_random(&fpmr_in, sizeof(fpmr_in)); + fpmr_in &=3D FPMR_SAFE_BITS; + + /* Entering or exiting streaming mode clears FPMR */ + if (sm_change) + fpmr_expected =3D 0; + else + fpmr_expected =3D fpmr_in; + } else { + fpmr_in =3D 0; + fpmr_expected =3D 0; + fpmr_out =3D 0; + } } =20 static bool check_memory_values(struct test_config *config) @@ -935,6 +1008,12 @@ static bool check_memory_values(struct test_config *c= onfig) if (!compare_buffer("saved ZT", zt_out, zt_expected, ZT_SIG_REG_BYTES)) pass =3D false; =20 + if (fpmr_out !=3D fpmr_expected) { + ksft_print_msg("Mismatch in saved FPMR: %lx !=3D %lx\n", + fpmr_out, fpmr_expected); + pass =3D false; + } + return pass; } =20 @@ -1012,6 +1091,36 @@ static void fpsimd_write(pid_t child, struct test_co= nfig *test_config) strerror(errno), errno); } =20 +static bool fpmr_write_supported(struct test_config *config) +{ + if (!fpmr_supported()) + return false; + + if (!sve_sme_same(config)) + return false; + + return true; +} + +static void fpmr_write_expected(struct test_config *config) +{ + fill_random(&fpmr_expected, sizeof(fpmr_expected)); + fpmr_expected &=3D FPMR_SAFE_BITS; +} + +static void fpmr_write(pid_t child, struct test_config *config) +{ + struct iovec iov; + int ret; + + iov.iov_len =3D sizeof(fpmr_expected); + iov.iov_base =3D &fpmr_expected; + ret =3D ptrace(PTRACE_SETREGSET, child, NT_ARM_FPMR, &iov); + if (ret !=3D 0) + ksft_print_msg("Failed to write FPMR: %s (%d)\n", + strerror(errno), errno); +} + static void sve_write_expected(struct test_config *config) { int vl =3D vl_expected(config); @@ -1268,6 +1377,12 @@ static struct test_definition base_test_defs[] =3D { .set_expected_values =3D fpsimd_write_expected, .modify_values =3D fpsimd_write, }, + { + .name =3D "FPMR write", + .supported =3D fpmr_write_supported, + .set_expected_values =3D fpmr_write_expected, + .modify_values =3D fpmr_write, + }, }; =20 static struct test_definition sve_test_defs[] =3D { @@ -1477,6 +1592,9 @@ int main(void) if (fa64_supported()) ksft_print_msg("FA64 supported\n"); =20 + if (fpmr_supported()) + ksft_print_msg("FPMR supported\n"); + ksft_set_plan(tests); =20 /* Get signal handers ready before we start any children */ diff --git a/tools/testing/selftests/arm64/fp/fp-ptrace.h b/tools/testing/s= elftests/arm64/fp/fp-ptrace.h index a3849817cf4ee23879da835cb7f66821b5e09bd0..1234394841303affd9aaba5cfcb= a0fcef2b5d30e 100644 --- a/tools/testing/selftests/arm64/fp/fp-ptrace.h +++ b/tools/testing/selftests/arm64/fp/fp-ptrace.h @@ -10,10 +10,12 @@ #define HAVE_SME_SHIFT 1 #define HAVE_SME2_SHIFT 2 #define HAVE_FA64_SHIFT 3 +#define HAVE_FPMR_SHIFT 4 =20 #define HAVE_SVE (1 << HAVE_SVE_SHIFT) #define HAVE_SME (1 << HAVE_SME_SHIFT) #define HAVE_SME2 (1 << HAVE_SME2_SHIFT) #define HAVE_FA64 (1 << HAVE_FA64_SHIFT) +#define HAVE_FPMR (1 << HAVE_FPMR_SHIFT) =20 #endif --=20 2.39.2