From nobody Sun Nov 24 04:07:12 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07C091F4286; Thu, 7 Nov 2024 10:59:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730977195; cv=none; b=BXC+aHjWbpM2v9EzRCA4HQpUPKc4D0aC0ELOY7QMp8uGo5WBdNLEQWXUyWyi7go7VxmrzyExN09oEGRbgoUiNBUmZeelFsIXiN3vADxN4ncyrLgVrQLHvUVHpgNo5agRAt+iUtnGC+ccd98W/W0O0ib3wkjcYYJKZKXGJdEC99M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730977195; c=relaxed/simple; bh=HPc5ze3TbELjcDwZYAJI6ddll1xN2pLq9zB9zwJ+2Gs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UEyHR/Bi+yJq/Ovizjr4PP8mpHKDcufKRCl1exdXTWSZKAuDwFepbpFfvI0a0vvNXwiGZSIZf1iP2IX6LE3R7jWcqAUVVLUlN8JzjJD8HHuRi57Hkjx5dcyasBrCwAiwqCLayTYkAwAlkz1353lvE0gg2TdfYwCsHb1LBrESlow= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=klJZYvXR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="klJZYvXR" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 05BA4C4CED2; Thu, 7 Nov 2024 10:59:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1730977194; bh=HPc5ze3TbELjcDwZYAJI6ddll1xN2pLq9zB9zwJ+2Gs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=klJZYvXRHdgwgdv6u9NAnQjf/LXN1AULw/vpEpZK5ax+TttiYm4rSufB/1KzjSX1O 0qxmg/LngZ1cFEwxEPTyciAZH5qTaTHZ8gLH7AytLWHPfS7osjcKf7Y6GHrr5gP7Y0 2JfF/hMrMoXZ7nTAwgUPm7UMqBBtoZhCT04uzX9xe9C0Gokf36UUQzd3ksqI/mSad5 7PCoVhNoCX1UDfcniUi9AWnsqwy0vlkbZDWEAUHkxsmJHLs2ckHiB9vz1xN2CF+ZBZ zKhO9ZMXUqwX1Jn0blErs/pQHdpuI1rHta45NElrWPYPBh2O+1gyzR2vzzxBCXhj9D 5i/i2Gi3d2rgA== From: Conor Dooley To: linux-pci@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Krzysztof Kozlowski Subject: [PATCH v6 1/2] dt-bindings: PCI: microchip,pcie-host: fix reg properties Date: Thu, 7 Nov 2024 10:59:34 +0000 Message-ID: <20241107-barcode-whinny-b1a4e8834b4f@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241107-aqueduct-petroleum-c002480ba291@spud> References: <20241107-aqueduct-petroleum-c002480ba291@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3806; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=2DkXC2f5tzh8PSbgqwQZfzocIDjsb3rmEl4kleL3pQ4=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDOk6c2fz93M/2lOY1HfmceDmvON5XwKzwm5f45raoLZya XfRAtWLHaUsDGIcDLJiiiyJt/tapNb/cdnh3PMWZg4rE8gQBi5OAZhI3j9GhjvnV1Y6mU3S/XnV cLZyzusXAmJMiRUrq3qnrDx75V1D7jWG/8kvLGp47PiM+/nznbSmfP9w3yckvdOX+9qT1sZp/+/ LMwIA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The PCI host controller on PolarFire SoC has multiple root port instances, each with their own bridge and ctrl address spaces. The original binding has an "apb" register region, and it is expected to be set to the base address of the root complex' register space. Some defines in the Linux driver were used to compute the addresses of the bridge and ctrl address ranges corresponding to root port instance 1. Some customers want to use root port instance 2 however, which requires changing the defines in the driver, which is clearly not a portable solution. Remove this "apb" register region from the binding and add "bridge" & "ctrl" regions instead, that will directly communicate the address of these regions for a specific root port. Fixes: 6ee6c89aac35 ("dt-bindings: PCI: microchip: Add Microchip PolarFire = host binding") Acked-by: Krzysztof Kozlowski Acked-by: Daire McNamara Signed-off-by: Conor Dooley --- .../bindings/pci/microchip,pcie-host.yaml | 11 +++++++++-- .../bindings/pci/plda,xpressrich3-axi-common.yaml | 14 ++++++++++---- .../bindings/pci/starfive,jh7110-pcie.yaml | 7 +++++++ 3 files changed, 26 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml= b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml index 612633ba59e2..2e1547569702 100644 --- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml @@ -17,6 +17,12 @@ properties: compatible: const: microchip,pcie-host-1.0 # PolarFire =20 + reg: + minItems: 3 + + reg-names: + minItems: 3 + clocks: description: Fabric Interface Controllers, FICs, are the interface between the FP= GA @@ -62,8 +68,9 @@ examples: pcie0: pcie@2030000000 { compatible =3D "microchip,pcie-host-1.0"; reg =3D <0x0 0x70000000 0x0 0x08000000>, - <0x0 0x43000000 0x0 0x00010000>; - reg-names =3D "cfg", "apb"; + <0x0 0x43008000 0x0 0x00002000>, + <0x0 0x4300a000 0x0 0x00002000>; + reg-names =3D "cfg", "bridge", "ctrl"; device_type =3D "pci"; #address-cells =3D <3>; #size-cells =3D <2>; diff --git a/Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-com= mon.yaml b/Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-commo= n.yaml index 7a57a80052a0..039eecdbd6aa 100644 --- a/Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml +++ b/Documentation/devicetree/bindings/pci/plda,xpressrich3-axi-common.yaml @@ -18,12 +18,18 @@ allOf: =20 properties: reg: - maxItems: 2 + maxItems: 3 + minItems: 2 =20 reg-names: - items: - - const: cfg - - const: apb + oneOf: + - items: + - const: cfg + - const: apb + - items: + - const: cfg + - const: bridge + - const: ctrl =20 interrupts: minItems: 1 diff --git a/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yam= l b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml index 67151aaa3948..5f432452c815 100644 --- a/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml @@ -16,6 +16,13 @@ properties: compatible: const: starfive,jh7110-pcie =20 + + reg: + maxItems: 2 + + reg-names: + maxItems: 2 + clocks: items: - description: NOC bus clock --=20 2.45.2 From nobody Sun Nov 24 04:07:12 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B46A31F472E; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="h51p51XQ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 00ED6C4CED8; Thu, 7 Nov 2024 10:59:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1730977197; bh=EGlVT0GltYE24uSQNhmhyipgdYLOMXDQftjyAz5Fjnw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=h51p51XQ8o0S59s760CfPn7xoxTCT8nDuF2HH9W360JB0r6JvsLWVOYOl/EfUmI06 yYfGRvHa6JZmWaB/IFu/wFoC2yw4ThzjcB5etCiPLmoaqGX7mFWeuopyJelW7m6WFl xydybsCt/lBuQxA62mKE7RL0lz7jKnY4gnmXePf6NdmTFhZBgIEtW0Dr2Ca+1JjaUd 4wlUcGbZaeCq6w6Edz/MXiFRbAvJ10CegAo8h/s16aULK7fWnK6IusdW8+TElZzAjD wrejzqe5Kn7f4MBeQw4vnSJP3CXTgZl0yqKKvIzBLHUMzgYfSr12ljZdtfF1i0qPPZ F5itzMucri+Ag== From: Conor Dooley To: linux-pci@vger.kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v6 2/2] PCI: microchip: rework reg region handing to support using either root port 1 or 2 Date: Thu, 7 Nov 2024 10:59:35 +0000 Message-ID: <20241107-surrender-brisket-287d563a5de1@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241107-aqueduct-petroleum-c002480ba291@spud> References: <20241107-aqueduct-petroleum-c002480ba291@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=12361; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=H4M32FMAjmsOTMK9JUjxGro8H3bHDCHFANNY2zSuR4g=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDOk6c2fn9EiHuFlWmv46OLd6QsOcT5P83905ZyUpsnHyy 021dTdXd5SyMIhxMMiKKbIk3u5rkVr/x2WHc89bmDmsTCBDGLg4BWAiZzYzMvzT/iUdmryxkIfH KvHKwabFWya9644VKf2qKxb5zHjXAkdGhs/35li03J+9pPKhdF3kzv+RZyqnG1gfvl857cmr42u tP/ACAA== X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The PCI host controller on PolarFire SoC has multiple root port instances, each with their own bridge and ctrl address spaces. The original binding has an "apb" register region, and it is expected to be set to the base address of the root complex' register space. Some defines in the Linux driver were used to compute the addresses of the bridge and ctrl address ranges corresponding to root port instance 1. Some customers want to use root port instance 2 however, which requires changing the defines in the driver, which is clearly not a portable solution. The binding has been changed from a single register region to a pair, corresponding to the bridge and ctrl regions respectively, so modify the driver to read these regions directly from the devicetree rather than compute them from the base address of the abp region. To maintain backwards compatibility with the existing binding, the driver retains code to handle the "abp" reg and computes the base address of the bridge and ctrl regions using the defines if it is present. reg-names has always been a required property, so this is safe to do. Signed-off-by: Conor Dooley --- Dropped Daire's Ack due to substantial rebasing. --- .../pci/controller/plda/pcie-microchip-host.c | 116 +++++++++--------- 1 file changed, 61 insertions(+), 55 deletions(-) diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pc= i/controller/plda/pcie-microchip-host.c index 48f60a04b740..57f35290c83b 100644 --- a/drivers/pci/controller/plda/pcie-microchip-host.c +++ b/drivers/pci/controller/plda/pcie-microchip-host.c @@ -25,9 +25,6 @@ #define MC_PCIE1_BRIDGE_ADDR 0x00008000u #define MC_PCIE1_CTRL_ADDR 0x0000a000u =20 -#define MC_PCIE_BRIDGE_ADDR (MC_PCIE1_BRIDGE_ADDR) -#define MC_PCIE_CTRL_ADDR (MC_PCIE1_CTRL_ADDR) - /* PCIe Controller Phy Regs */ #define SEC_ERROR_EVENT_CNT 0x20 #define DED_ERROR_EVENT_CNT 0x24 @@ -128,7 +125,6 @@ [EVENT_LOCAL_ ## x] =3D { __stringify(x), s } =20 #define PCIE_EVENT(x) \ - .base =3D MC_PCIE_CTRL_ADDR, \ .offset =3D PCIE_EVENT_INT, \ .mask_offset =3D PCIE_EVENT_INT, \ .mask_high =3D 1, \ @@ -136,7 +132,6 @@ .enb_mask =3D PCIE_EVENT_INT_ENB_MASK =20 #define SEC_EVENT(x) \ - .base =3D MC_PCIE_CTRL_ADDR, \ .offset =3D SEC_ERROR_INT, \ .mask_offset =3D SEC_ERROR_INT_MASK, \ .mask =3D SEC_ERROR_INT_ ## x ## _INT, \ @@ -144,7 +139,6 @@ .enb_mask =3D 0 =20 #define DED_EVENT(x) \ - .base =3D MC_PCIE_CTRL_ADDR, \ .offset =3D DED_ERROR_INT, \ .mask_offset =3D DED_ERROR_INT_MASK, \ .mask_high =3D 1, \ @@ -152,7 +146,6 @@ .enb_mask =3D 0 =20 #define LOCAL_EVENT(x) \ - .base =3D MC_PCIE_BRIDGE_ADDR, \ .offset =3D ISTATUS_LOCAL, \ .mask_offset =3D IMASK_LOCAL, \ .mask_high =3D 0, \ @@ -179,7 +172,8 @@ struct event_map { =20 struct mc_pcie { struct plda_pcie_rp plda; - void __iomem *axi_base_addr; + void __iomem *bridge_base_addr; + void __iomem *ctrl_base_addr; }; =20 struct cause { @@ -253,7 +247,6 @@ static struct event_map local_status_to_event[] =3D { }; =20 static struct { - u32 base; u32 offset; u32 mask; u32 shift; @@ -325,8 +318,7 @@ static inline u32 reg_to_event(u32 reg, struct event_ma= p field) =20 static u32 pcie_events(struct mc_pcie *port) { - void __iomem *ctrl_base_addr =3D port->axi_base_addr + MC_PCIE_CTRL_ADDR; - u32 reg =3D readl_relaxed(ctrl_base_addr + PCIE_EVENT_INT); + u32 reg =3D readl_relaxed(port->ctrl_base_addr + PCIE_EVENT_INT); u32 val =3D 0; int i; =20 @@ -338,8 +330,7 @@ static u32 pcie_events(struct mc_pcie *port) =20 static u32 sec_errors(struct mc_pcie *port) { - void __iomem *ctrl_base_addr =3D port->axi_base_addr + MC_PCIE_CTRL_ADDR; - u32 reg =3D readl_relaxed(ctrl_base_addr + SEC_ERROR_INT); + u32 reg =3D readl_relaxed(port->ctrl_base_addr + SEC_ERROR_INT); u32 val =3D 0; int i; =20 @@ -351,8 +342,7 @@ static u32 sec_errors(struct mc_pcie *port) =20 static u32 ded_errors(struct mc_pcie *port) { - void __iomem *ctrl_base_addr =3D port->axi_base_addr + MC_PCIE_CTRL_ADDR; - u32 reg =3D readl_relaxed(ctrl_base_addr + DED_ERROR_INT); + u32 reg =3D readl_relaxed(port->ctrl_base_addr + DED_ERROR_INT); u32 val =3D 0; int i; =20 @@ -364,8 +354,7 @@ static u32 ded_errors(struct mc_pcie *port) =20 static u32 local_events(struct mc_pcie *port) { - void __iomem *bridge_base_addr =3D port->axi_base_addr + MC_PCIE_BRIDGE_A= DDR; - u32 reg =3D readl_relaxed(bridge_base_addr + ISTATUS_LOCAL); + u32 reg =3D readl_relaxed(port->bridge_base_addr + ISTATUS_LOCAL); u32 val =3D 0; int i; =20 @@ -412,8 +401,12 @@ static void mc_ack_event_irq(struct irq_data *data) void __iomem *addr; u32 mask; =20 - addr =3D mc_port->axi_base_addr + event_descs[event].base + - event_descs[event].offset; + if (event_descs[event].offset =3D=3D ISTATUS_LOCAL) + addr =3D mc_port->bridge_base_addr; + else + addr =3D mc_port->ctrl_base_addr; + + addr +=3D event_descs[event].offset; mask =3D event_descs[event].mask; mask |=3D event_descs[event].enb_mask; =20 @@ -429,8 +422,12 @@ static void mc_mask_event_irq(struct irq_data *data) u32 mask; u32 val; =20 - addr =3D mc_port->axi_base_addr + event_descs[event].base + - event_descs[event].mask_offset; + if (event_descs[event].offset =3D=3D ISTATUS_LOCAL) + addr =3D mc_port->bridge_base_addr; + else + addr =3D mc_port->ctrl_base_addr; + + addr +=3D event_descs[event].mask_offset; mask =3D event_descs[event].mask; if (event_descs[event].enb_mask) { mask <<=3D PCIE_EVENT_INT_ENB_SHIFT; @@ -460,8 +457,12 @@ static void mc_unmask_event_irq(struct irq_data *data) u32 mask; u32 val; =20 - addr =3D mc_port->axi_base_addr + event_descs[event].base + - event_descs[event].mask_offset; + if (event_descs[event].offset =3D=3D ISTATUS_LOCAL) + addr =3D mc_port->bridge_base_addr; + else + addr =3D mc_port->ctrl_base_addr; + + addr +=3D event_descs[event].mask_offset; mask =3D event_descs[event].mask; =20 if (event_descs[event].enb_mask) @@ -554,26 +555,20 @@ static const struct plda_event mc_event =3D { =20 static inline void mc_clear_secs(struct mc_pcie *port) { - void __iomem *ctrl_base_addr =3D port->axi_base_addr + MC_PCIE_CTRL_ADDR; - - writel_relaxed(SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT, ctrl_base_addr + + writel_relaxed(SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT, port->ctrl_base_addr + SEC_ERROR_INT); - writel_relaxed(0, ctrl_base_addr + SEC_ERROR_EVENT_CNT); + writel_relaxed(0, port->ctrl_base_addr + SEC_ERROR_EVENT_CNT); } =20 static inline void mc_clear_deds(struct mc_pcie *port) { - void __iomem *ctrl_base_addr =3D port->axi_base_addr + MC_PCIE_CTRL_ADDR; - - writel_relaxed(DED_ERROR_INT_ALL_RAM_DED_ERR_INT, ctrl_base_addr + + writel_relaxed(DED_ERROR_INT_ALL_RAM_DED_ERR_INT, port->ctrl_base_addr + DED_ERROR_INT); - writel_relaxed(0, ctrl_base_addr + DED_ERROR_EVENT_CNT); + writel_relaxed(0, port->ctrl_base_addr + DED_ERROR_EVENT_CNT); } =20 static void mc_disable_interrupts(struct mc_pcie *port) { - void __iomem *bridge_base_addr =3D port->axi_base_addr + MC_PCIE_BRIDGE_A= DDR; - void __iomem *ctrl_base_addr =3D port->axi_base_addr + MC_PCIE_CTRL_ADDR; u32 val; =20 /* Ensure ECC bypass is enabled */ @@ -581,22 +576,22 @@ static void mc_disable_interrupts(struct mc_pcie *por= t) ECC_CONTROL_RX_RAM_ECC_BYPASS | ECC_CONTROL_PCIE2AXI_RAM_ECC_BYPASS | ECC_CONTROL_AXI2PCIE_RAM_ECC_BYPASS; - writel_relaxed(val, ctrl_base_addr + ECC_CONTROL); + writel_relaxed(val, port->ctrl_base_addr + ECC_CONTROL); =20 /* Disable SEC errors and clear any outstanding */ - writel_relaxed(SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT, ctrl_base_addr + + writel_relaxed(SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT, port->ctrl_base_addr + SEC_ERROR_INT_MASK); mc_clear_secs(port); =20 /* Disable DED errors and clear any outstanding */ - writel_relaxed(DED_ERROR_INT_ALL_RAM_DED_ERR_INT, ctrl_base_addr + + writel_relaxed(DED_ERROR_INT_ALL_RAM_DED_ERR_INT, port->ctrl_base_addr + DED_ERROR_INT_MASK); mc_clear_deds(port); =20 /* Disable local interrupts and clear any outstanding */ - writel_relaxed(0, bridge_base_addr + IMASK_LOCAL); - writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_LOCAL); - writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_MSI); + writel_relaxed(0, port->bridge_base_addr + IMASK_LOCAL); + writel_relaxed(GENMASK(31, 0), port->bridge_base_addr + ISTATUS_LOCAL); + writel_relaxed(GENMASK(31, 0), port->bridge_base_addr + ISTATUS_MSI); =20 /* Disable PCIe events and clear any outstanding */ val =3D PCIE_EVENT_INT_L2_EXIT_INT | @@ -605,11 +600,11 @@ static void mc_disable_interrupts(struct mc_pcie *por= t) PCIE_EVENT_INT_L2_EXIT_INT_MASK | PCIE_EVENT_INT_HOTRST_EXIT_INT_MASK | PCIE_EVENT_INT_DLUP_EXIT_INT_MASK; - writel_relaxed(val, ctrl_base_addr + PCIE_EVENT_INT); + writel_relaxed(val, port->ctrl_base_addr + PCIE_EVENT_INT); =20 /* Disable host interrupts and clear any outstanding */ - writel_relaxed(0, bridge_base_addr + IMASK_HOST); - writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST); + writel_relaxed(0, port->bridge_base_addr + IMASK_HOST); + writel_relaxed(GENMASK(31, 0), port->bridge_base_addr + ISTATUS_HOST); } =20 static int mc_platform_init(struct pci_config_window *cfg) @@ -617,12 +612,10 @@ static int mc_platform_init(struct pci_config_window = *cfg) struct device *dev =3D cfg->parent; struct platform_device *pdev =3D to_platform_device(dev); struct pci_host_bridge *bridge =3D platform_get_drvdata(pdev); - void __iomem *bridge_base_addr =3D - port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; int ret; =20 /* Configure address translation table 0 for PCIe config space */ - plda_pcie_setup_window(bridge_base_addr, 0, cfg->res.start, + plda_pcie_setup_window(port->bridge_base_addr, 0, cfg->res.start, cfg->res.start, resource_size(&cfg->res)); =20 @@ -649,7 +642,7 @@ static int mc_platform_init(struct pci_config_window *c= fg) static int mc_host_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; - void __iomem *bridge_base_addr; + void __iomem *apb_base_addr; struct plda_pcie_rp *plda; int ret; u32 val; @@ -661,30 +654,43 @@ static int mc_host_probe(struct platform_device *pdev) plda =3D &port->plda; plda->dev =3D dev; =20 - port->axi_base_addr =3D devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(port->axi_base_addr)) - return PTR_ERR(port->axi_base_addr); + port->bridge_base_addr =3D devm_platform_ioremap_resource_byname(pdev, "b= ridge"); + port->ctrl_base_addr =3D devm_platform_ioremap_resource_byname(pdev, "ctr= l"); + if (!IS_ERR(port->bridge_base_addr) && !IS_ERR(port->ctrl_base_addr)) + goto addrs_set; =20 + /* + * The original, incorrect, binding that lumped the control and + * bridge addresses together still needs to be handled by the driver. + */ + apb_base_addr =3D devm_platform_ioremap_resource_byname(pdev, "apb"); + if (IS_ERR(apb_base_addr)) + return dev_err_probe(dev, PTR_ERR(apb_base_addr), + "both legacy apb register and ctrl/bridge regions missing"); + + port->bridge_base_addr =3D apb_base_addr + MC_PCIE1_BRIDGE_ADDR; + port->ctrl_base_addr =3D apb_base_addr + MC_PCIE1_CTRL_ADDR; + +addrs_set: mc_disable_interrupts(port); =20 - bridge_base_addr =3D port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; - plda->bridge_addr =3D bridge_base_addr; + plda->bridge_addr =3D port->bridge_base_addr; plda->num_events =3D NUM_EVENTS; =20 /* Allow enabling MSI by disabling MSI-X */ - val =3D readl(bridge_base_addr + PCIE_PCI_IRQ_DW0); + val =3D readl(port->bridge_base_addr + PCIE_PCI_IRQ_DW0); val &=3D ~MSIX_CAP_MASK; - writel(val, bridge_base_addr + PCIE_PCI_IRQ_DW0); + writel(val, port->bridge_base_addr + PCIE_PCI_IRQ_DW0); =20 /* Pick num vectors from bitfile programmed onto FPGA fabric */ - val =3D readl(bridge_base_addr + PCIE_PCI_IRQ_DW0); + val =3D readl(port->bridge_base_addr + PCIE_PCI_IRQ_DW0); val &=3D NUM_MSI_MSGS_MASK; val >>=3D NUM_MSI_MSGS_SHIFT; =20 plda->msi.num_vectors =3D 1 << val; =20 /* Pick vector address from design */ - plda->msi.vector_phy =3D readl_relaxed(bridge_base_addr + IMSI_ADDR); + plda->msi.vector_phy =3D readl_relaxed(port->bridge_base_addr + IMSI_ADDR= ); =20 ret =3D mc_pcie_init_clks(dev); if (ret) { --=20 2.45.2