From nobody Sun Nov 24 08:34:22 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8AA2320CCC6; Wed, 6 Nov 2024 22:14:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730931256; cv=none; b=YJOS/gxah+5tqY0c05s4CJGeB+kwg7yuSR0jbTmIO+hDJl0TxWgxJRP4lMnzbjpu5HRZxdmvBpHqWEO3duWwqsljd85aJyt+yaU+6hoRgLF/v3UKeWVj8v4w94MNtW4xj7IUVEJg0MD6bMf4u+DmPxOiHNy1hGubijSZw9OV0cs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730931256; c=relaxed/simple; bh=KRGj942UvE+uLjnvQ1RnPKt7mrlSaWFQ5enJ5cOt4xQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Gu0gWJprPGJJEDY9qskeGDd1X3xTK86agcBk3lzjFG0sR8SAUv6neY77nxZmuzyV17dPiSd8OdPS7M3Md5W8KQv68Cw1sXoLaKS1+hQJcO5g6pt9LtaCxOVDYC0MzmSDx12nZv4+q6SJHHSkzBz4v6ZzK5Wma+XroFfLmf2sKCw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=jLhjvmot; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="jLhjvmot" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4A6G2ocd013219; Wed, 6 Nov 2024 22:14:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= bIcFx6LoYs55AK/fOEYhEuqBF9RZPZfLcL/g1CWM5l4=; b=jLhjvmotv9OMm+oC yYwQeKqfojVBCy7HdSy1kwNQPvcD3i+XkHbQJQNzuO21zy9WyVcrvMdv/40epKq+ N6YcfIprpiWBajYsiDknjBtjALo9Fc2dAZvrzUs5p9TXWuPA0EOUxe6YgbefjZgE PLgDmemE5vL0PdWgikElxCYq429QW2tIQzNpdCQNFv8IJf/CSXGlyjs7hTWNA8YH bgEqbzfOIU4Eb3DWAiwIwga1ZZMtKaooLa1iBzqFycTp7KQKL3y0GU9w+4T/GbRX CwwwxI76Jx6zCjrigeFEomi68Ti7jyzr+HlFQS8g6+yIhSWHPgCVdnqhGxU+fnkR uXEB+g== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42qp2rvcgf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 06 Nov 2024 22:14:06 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4A6ME4Qv016602 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 6 Nov 2024 22:14:04 GMT Received: from hu-mrana-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 6 Nov 2024 14:14:04 -0800 From: Mayank Rana To: , , , , , , , CC: , , , , Mayank Rana Subject: [PATCH v3 1/4] PCI: dwc: Export dwc MSI controller related APIs Date: Wed, 6 Nov 2024 14:13:38 -0800 Message-ID: <20241106221341.2218416-2-quic_mrana@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241106221341.2218416-1-quic_mrana@quicinc.com> References: <20241106221341.2218416-1-quic_mrana@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: TTf5raw4Njl36L2INkEmqzpX-JNJz01M X-Proofpoint-ORIG-GUID: TTf5raw4Njl36L2INkEmqzpX-JNJz01M X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 bulkscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 mlxlogscore=999 suspectscore=0 spamscore=0 mlxscore=0 phishscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411060170 Content-Type: text/plain; charset="utf-8" To allow dwc PCIe controller based MSI functionality from ECAM pcie driver, export dw_pcie_msi_host_init(), dw_pcie_msi_init() and dw_pcie_msi_free() APIs. Also move MSI IRQ related initialization code into dw_pcie_msi_init() as this code executes before dw_pcie_msi_init() API to use with ECAM driver. Signed-off-by: Mayank Rana --- .../pci/controller/dwc/pcie-designware-host.c | 38 ++++++++++--------- drivers/pci/controller/dwc/pcie-designware.h | 14 +++++++ 2 files changed, 34 insertions(+), 18 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 3e41865c7290..25020a090db8 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -250,7 +250,7 @@ int dw_pcie_allocate_domains(struct dw_pcie_rp *pp) return 0; } =20 -static void dw_pcie_free_msi(struct dw_pcie_rp *pp) +void dw_pcie_free_msi(struct dw_pcie_rp *pp) { u32 ctrl; =20 @@ -263,19 +263,34 @@ static void dw_pcie_free_msi(struct dw_pcie_rp *pp) irq_domain_remove(pp->msi_domain); irq_domain_remove(pp->irq_domain); } +EXPORT_SYMBOL_GPL(dw_pcie_free_msi); =20 -static void dw_pcie_msi_init(struct dw_pcie_rp *pp) +void dw_pcie_msi_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); u64 msi_target =3D (u64)pp->msi_data; + u32 ctrl, num_ctrls; =20 if (!pci_msi_enabled() || !pp->has_msi_ctrl) return; =20 + num_ctrls =3D pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; + + /* Initialize IRQ Status array */ + for (ctrl =3D 0; ctrl < num_ctrls; ctrl++) { + dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), + pp->irq_mask[ctrl]); + dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE + + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), + ~0); + } + /* Program the msi_data */ dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target)); dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target)); } +EXPORT_SYMBOL_GPL(dw_pcie_msi_init); =20 static int dw_pcie_parse_split_msi_irq(struct dw_pcie_rp *pp) { @@ -317,7 +332,7 @@ static int dw_pcie_parse_split_msi_irq(struct dw_pcie_r= p *pp) return 0; } =20 -static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) +int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); struct device *dev =3D pci->dev; @@ -391,6 +406,7 @@ static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) =20 return 0; } +EXPORT_SYMBOL_GPL(dw_pcie_msi_host_init); =20 static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp) { @@ -802,7 +818,7 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) int dw_pcie_setup_rc(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); - u32 val, ctrl, num_ctrls; + u32 val; int ret; =20 /* @@ -813,20 +829,6 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) =20 dw_pcie_setup(pci); =20 - if (pp->has_msi_ctrl) { - num_ctrls =3D pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; - - /* Initialize IRQ Status array */ - for (ctrl =3D 0; ctrl < num_ctrls; ctrl++) { - dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + - (ctrl * MSI_REG_CTRL_BLOCK_SIZE), - pp->irq_mask[ctrl]); - dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE + - (ctrl * MSI_REG_CTRL_BLOCK_SIZE), - ~0); - } - } - dw_pcie_msi_init(pp); =20 /* Setup RC BARs */ diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index 347ab74ac35a..ef748d82c663 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -679,6 +679,9 @@ static inline enum dw_pcie_ltssm dw_pcie_get_ltssm(stru= ct dw_pcie *pci) =20 #ifdef CONFIG_PCIE_DW_HOST irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp); +void dw_pcie_msi_init(struct dw_pcie_rp *pp); +int dw_pcie_msi_host_init(struct dw_pcie_rp *pp); +void dw_pcie_free_msi(struct dw_pcie_rp *pp); int dw_pcie_setup_rc(struct dw_pcie_rp *pp); int dw_pcie_host_init(struct dw_pcie_rp *pp); void dw_pcie_host_deinit(struct dw_pcie_rp *pp); @@ -691,6 +694,17 @@ static inline irqreturn_t dw_handle_msi_irq(struct dw_= pcie_rp *pp) return IRQ_NONE; } =20 +static void dw_pcie_msi_init(struct dw_pcie_rp *pp) +{ } + +static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) +{ + return -ENODEV; +} + +static void dw_pcie_free_msi(struct dw_pcie_rp *pp) +{ } + static inline int dw_pcie_setup_rc(struct dw_pcie_rp *pp) { return 0; --=20 2.25.1