From nobody Sun Nov 24 06:37:30 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8AA2320CCC6; Wed, 6 Nov 2024 22:14:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730931256; cv=none; b=YJOS/gxah+5tqY0c05s4CJGeB+kwg7yuSR0jbTmIO+hDJl0TxWgxJRP4lMnzbjpu5HRZxdmvBpHqWEO3duWwqsljd85aJyt+yaU+6hoRgLF/v3UKeWVj8v4w94MNtW4xj7IUVEJg0MD6bMf4u+DmPxOiHNy1hGubijSZw9OV0cs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730931256; c=relaxed/simple; bh=KRGj942UvE+uLjnvQ1RnPKt7mrlSaWFQ5enJ5cOt4xQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Gu0gWJprPGJJEDY9qskeGDd1X3xTK86agcBk3lzjFG0sR8SAUv6neY77nxZmuzyV17dPiSd8OdPS7M3Md5W8KQv68Cw1sXoLaKS1+hQJcO5g6pt9LtaCxOVDYC0MzmSDx12nZv4+q6SJHHSkzBz4v6ZzK5Wma+XroFfLmf2sKCw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=jLhjvmot; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="jLhjvmot" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4A6G2ocd013219; Wed, 6 Nov 2024 22:14:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= bIcFx6LoYs55AK/fOEYhEuqBF9RZPZfLcL/g1CWM5l4=; b=jLhjvmotv9OMm+oC yYwQeKqfojVBCy7HdSy1kwNQPvcD3i+XkHbQJQNzuO21zy9WyVcrvMdv/40epKq+ N6YcfIprpiWBajYsiDknjBtjALo9Fc2dAZvrzUs5p9TXWuPA0EOUxe6YgbefjZgE PLgDmemE5vL0PdWgikElxCYq429QW2tIQzNpdCQNFv8IJf/CSXGlyjs7hTWNA8YH bgEqbzfOIU4Eb3DWAiwIwga1ZZMtKaooLa1iBzqFycTp7KQKL3y0GU9w+4T/GbRX CwwwxI76Jx6zCjrigeFEomi68Ti7jyzr+HlFQS8g6+yIhSWHPgCVdnqhGxU+fnkR uXEB+g== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42qp2rvcgf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 06 Nov 2024 22:14:06 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4A6ME4Qv016602 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 6 Nov 2024 22:14:04 GMT Received: from hu-mrana-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 6 Nov 2024 14:14:04 -0800 From: Mayank Rana To: , , , , , , , CC: , , , , Mayank Rana Subject: [PATCH v3 1/4] PCI: dwc: Export dwc MSI controller related APIs Date: Wed, 6 Nov 2024 14:13:38 -0800 Message-ID: <20241106221341.2218416-2-quic_mrana@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241106221341.2218416-1-quic_mrana@quicinc.com> References: <20241106221341.2218416-1-quic_mrana@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: TTf5raw4Njl36L2INkEmqzpX-JNJz01M X-Proofpoint-ORIG-GUID: TTf5raw4Njl36L2INkEmqzpX-JNJz01M X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 bulkscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 mlxlogscore=999 suspectscore=0 spamscore=0 mlxscore=0 phishscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411060170 Content-Type: text/plain; charset="utf-8" To allow dwc PCIe controller based MSI functionality from ECAM pcie driver, export dw_pcie_msi_host_init(), dw_pcie_msi_init() and dw_pcie_msi_free() APIs. Also move MSI IRQ related initialization code into dw_pcie_msi_init() as this code executes before dw_pcie_msi_init() API to use with ECAM driver. Signed-off-by: Mayank Rana --- .../pci/controller/dwc/pcie-designware-host.c | 38 ++++++++++--------- drivers/pci/controller/dwc/pcie-designware.h | 14 +++++++ 2 files changed, 34 insertions(+), 18 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 3e41865c7290..25020a090db8 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -250,7 +250,7 @@ int dw_pcie_allocate_domains(struct dw_pcie_rp *pp) return 0; } =20 -static void dw_pcie_free_msi(struct dw_pcie_rp *pp) +void dw_pcie_free_msi(struct dw_pcie_rp *pp) { u32 ctrl; =20 @@ -263,19 +263,34 @@ static void dw_pcie_free_msi(struct dw_pcie_rp *pp) irq_domain_remove(pp->msi_domain); irq_domain_remove(pp->irq_domain); } +EXPORT_SYMBOL_GPL(dw_pcie_free_msi); =20 -static void dw_pcie_msi_init(struct dw_pcie_rp *pp) +void dw_pcie_msi_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); u64 msi_target =3D (u64)pp->msi_data; + u32 ctrl, num_ctrls; =20 if (!pci_msi_enabled() || !pp->has_msi_ctrl) return; =20 + num_ctrls =3D pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; + + /* Initialize IRQ Status array */ + for (ctrl =3D 0; ctrl < num_ctrls; ctrl++) { + dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), + pp->irq_mask[ctrl]); + dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE + + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), + ~0); + } + /* Program the msi_data */ dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target)); dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target)); } +EXPORT_SYMBOL_GPL(dw_pcie_msi_init); =20 static int dw_pcie_parse_split_msi_irq(struct dw_pcie_rp *pp) { @@ -317,7 +332,7 @@ static int dw_pcie_parse_split_msi_irq(struct dw_pcie_r= p *pp) return 0; } =20 -static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) +int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); struct device *dev =3D pci->dev; @@ -391,6 +406,7 @@ static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) =20 return 0; } +EXPORT_SYMBOL_GPL(dw_pcie_msi_host_init); =20 static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp) { @@ -802,7 +818,7 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) int dw_pcie_setup_rc(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); - u32 val, ctrl, num_ctrls; + u32 val; int ret; =20 /* @@ -813,20 +829,6 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) =20 dw_pcie_setup(pci); =20 - if (pp->has_msi_ctrl) { - num_ctrls =3D pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; - - /* Initialize IRQ Status array */ - for (ctrl =3D 0; ctrl < num_ctrls; ctrl++) { - dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + - (ctrl * MSI_REG_CTRL_BLOCK_SIZE), - pp->irq_mask[ctrl]); - dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE + - (ctrl * MSI_REG_CTRL_BLOCK_SIZE), - ~0); - } - } - dw_pcie_msi_init(pp); =20 /* Setup RC BARs */ diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index 347ab74ac35a..ef748d82c663 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -679,6 +679,9 @@ static inline enum dw_pcie_ltssm dw_pcie_get_ltssm(stru= ct dw_pcie *pci) =20 #ifdef CONFIG_PCIE_DW_HOST irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp); +void dw_pcie_msi_init(struct dw_pcie_rp *pp); +int dw_pcie_msi_host_init(struct dw_pcie_rp *pp); +void dw_pcie_free_msi(struct dw_pcie_rp *pp); int dw_pcie_setup_rc(struct dw_pcie_rp *pp); int dw_pcie_host_init(struct dw_pcie_rp *pp); void dw_pcie_host_deinit(struct dw_pcie_rp *pp); @@ -691,6 +694,17 @@ static inline irqreturn_t dw_handle_msi_irq(struct dw_= pcie_rp *pp) return IRQ_NONE; } =20 +static void dw_pcie_msi_init(struct dw_pcie_rp *pp) +{ } + +static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) +{ + return -ENODEV; +} + +static void dw_pcie_free_msi(struct dw_pcie_rp *pp) +{ } + static inline int dw_pcie_setup_rc(struct dw_pcie_rp *pp) { return 0; --=20 2.25.1 From nobody Sun Nov 24 06:37:30 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 397B920E00C; Wed, 6 Nov 2024 22:14:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Export gen_pci_init() API to create ECAM and initialized ECAM OPs from PCIe driver which don't have way to populate driver_data as just ECAM ops. Signed-off-by: Mayank Rana --- drivers/pci/controller/pci-host-common.c | 3 ++- include/linux/pci-ecam.h | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pci-host-common.c b/drivers/pci/control= ler/pci-host-common.c index cf5f59a745b3..b9460a4c5b7e 100644 --- a/drivers/pci/controller/pci-host-common.c +++ b/drivers/pci/controller/pci-host-common.c @@ -20,7 +20,7 @@ static void gen_pci_unmap_cfg(void *ptr) pci_ecam_free((struct pci_config_window *)ptr); } =20 -static struct pci_config_window *gen_pci_init(struct device *dev, +struct pci_config_window *gen_pci_init(struct device *dev, struct pci_host_bridge *bridge, const struct pci_ecam_ops *ops) { int err; @@ -48,6 +48,7 @@ static struct pci_config_window *gen_pci_init(struct devi= ce *dev, =20 return cfg; } +EXPORT_SYMBOL_GPL(gen_pci_init); =20 int pci_host_common_probe(struct platform_device *pdev) { diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h index 3a4860bd2758..386c08349169 100644 --- a/include/linux/pci-ecam.h +++ b/include/linux/pci-ecam.h @@ -94,5 +94,7 @@ extern const struct pci_ecam_ops loongson_pci_ecam_ops; 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charset="utf-8" On SA8255p, PCIe root complex is managed by firmware using power-domain based handling. This root complex is configured as ECAM compliant. Document required configuration to enable PCIe root complex. Signed-off-by: Mayank Rana --- .../bindings/pci/qcom,pcie-sa8255p.yaml | 103 ++++++++++++++++++ 1 file changed, 103 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p= .yaml diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml b= /Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml new file mode 100644 index 000000000000..9b09c3923ba0 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-sa8255p.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SA8255p based firmware managed and ECAM compliant PCIe Roo= t Complex + +maintainers: + - Bjorn Andersson + - Manivannan Sadhasivam + +description: + Qualcomm SA8255p SoC PCIe root complex controller is based on the Synops= ys + DesignWare PCIe IP which is managed by firmware, and configured in ECAM = mode. + +properties: + compatible: + const: qcom,pcie-sa8255p + + reg: + description: + The Configuration Space base address and size, as accessed from the = parent + bus. The base address corresponds to the first bus in the "bus-range" + property. If no "bus-range" is specified, this will be bus 0 (the + default). + maxItems: 1 + + ranges: + description: + As described in IEEE Std 1275-1994, but must provide at least a + definition of non-prefetchable memory. One or both of prefetchable M= emory + may also be provided. + minItems: 1 + maxItems: 2 + + interrupts: + minItems: 8 + maxItems: 8 + + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + + power-domains: + maxItems: 1 + + dma-coherent: true + iommu-map: true + +required: + - compatible + - reg + - ranges + - power-domains + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pci@1c00000 { + compatible =3D "qcom,pcie-sa8255p"; + reg =3D <0x4 0x00000000 0 0x10000000>; + device_type =3D "pci"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x02000000 0x0 0x40100000 0x0 0x40100000 0x0 0x1ff0= 0000>, + <0x43000000 0x4 0x10100000 0x4 0x10100000 0x0 0x400000= 00>; + bus-range =3D <0x00 0xff>; + dma-coherent; + linux,pci-domain =3D <0>; + power-domains =3D <&scmi5_pd 0>; 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charset="utf-8" On SA8255p ride platform, PCIe root complex is firmware managed as well configured into ECAM compliant mode. This change adds functionality to enable resource management (system resource as well PCIe controller and PHY configuration) through firmware, and enumerating ECAM compliant root complex. Signed-off-by: Mayank Rana --- drivers/pci/controller/dwc/Kconfig | 1 + drivers/pci/controller/dwc/pcie-qcom.c | 116 +++++++++++++++++++++++-- 2 files changed, 108 insertions(+), 9 deletions(-) diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dw= c/Kconfig index b6d6778b0698..0fe76bd39d69 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -275,6 +275,7 @@ config PCIE_QCOM select PCIE_DW_HOST select CRC8 select PCIE_QCOM_COMMON + select PCI_HOST_COMMON help Say Y here to enable PCIe controller support on Qualcomm SoCs. The PCIe controller uses the DesignWare core plus Qualcomm-specific diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index ef44a82be058..2cb74f902baf 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -21,7 +21,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -254,10 +256,12 @@ struct qcom_pcie_ops { * @ops: qcom PCIe ops structure * @override_no_snoop: Override NO_SNOOP attribute in TLP to enable cache * snooping + * @firmware_managed: Set if PCIe root complex is firmware managed */ struct qcom_pcie_cfg { const struct qcom_pcie_ops *ops; bool override_no_snoop; + bool firmware_managed; bool no_l0s; }; =20 @@ -1415,6 +1419,10 @@ static const struct qcom_pcie_cfg cfg_sc8280xp =3D { .no_l0s =3D true, }; =20 +static const struct qcom_pcie_cfg cfg_fw_managed =3D { + .firmware_managed =3D true, +}; + static const struct dw_pcie_ops dw_pcie_ops =3D { .link_up =3D qcom_pcie_link_up, .start_link =3D qcom_pcie_start_link, @@ -1566,6 +1574,51 @@ static irqreturn_t qcom_pcie_global_irq_thread(int i= rq, void *data) return IRQ_HANDLED; } =20 +static void qcom_pci_free_msi(void *ptr) +{ + struct dw_pcie_rp *pp =3D (struct dw_pcie_rp *)ptr; + + if (pp && pp->has_msi_ctrl) + dw_pcie_free_msi(pp); +} + +static int qcom_pcie_ecam_host_init(struct pci_config_window *cfg) +{ + struct device *dev =3D cfg->parent; + struct dw_pcie_rp *pp; + struct dw_pcie *pci; + int ret; + + pci =3D devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); + if (!pci) + return -ENOMEM; + + pci->dev =3D dev; + pp =3D &pci->pp; + pci->dbi_base =3D cfg->win; + pp->num_vectors =3D MSI_DEF_NUM_VECTORS; + + ret =3D dw_pcie_msi_host_init(pp); + if (ret) + return ret; + + pp->has_msi_ctrl =3D true; + dw_pcie_msi_init(pp); + + ret =3D devm_add_action_or_reset(dev, qcom_pci_free_msi, pp); + return ret; +} + +/* ECAM ops */ +const struct pci_ecam_ops pci_qcom_ecam_ops =3D { + .init =3D qcom_pcie_ecam_host_init, + .pci_ops =3D { + .map_bus =3D pci_ecam_map_bus, + .read =3D pci_generic_config_read, + .write =3D pci_generic_config_write, + } +}; + static int qcom_pcie_probe(struct platform_device *pdev) { const struct qcom_pcie_cfg *pcie_cfg; @@ -1580,11 +1633,52 @@ static int qcom_pcie_probe(struct platform_device *= pdev) char *name; =20 pcie_cfg =3D of_device_get_match_data(dev); - if (!pcie_cfg || !pcie_cfg->ops) { - dev_err(dev, "Invalid platform data\n"); + if (!pcie_cfg) { + dev_err(dev, "No platform data\n"); + return -EINVAL; + } + + if (!pcie_cfg->firmware_managed && !pcie_cfg->ops) { + dev_err(dev, "No platform ops\n"); return -EINVAL; } =20 + pm_runtime_enable(dev); + ret =3D pm_runtime_get_sync(dev); + if (ret < 0) + goto err_pm_runtime_put; + + if (pcie_cfg->firmware_managed) { + struct pci_host_bridge *bridge; + struct pci_config_window *cfg; + + bridge =3D devm_pci_alloc_host_bridge(dev, 0); + if (!bridge) { + ret =3D -ENOMEM; + goto err_pm_runtime_put; + } + + of_pci_check_probe_only(); + /* Parse and map our Configuration Space windows */ + cfg =3D gen_pci_init(dev, bridge, &pci_qcom_ecam_ops); + if (IS_ERR(cfg)) { + ret =3D PTR_ERR(cfg); + goto err_pm_runtime_put; + } + + bridge->sysdata =3D cfg; + bridge->ops =3D (struct pci_ops *)&pci_qcom_ecam_ops.pci_ops; + bridge->msi_domain =3D true; + + ret =3D pci_host_probe(bridge); + if (ret) { + dev_err(dev, "pci_host_probe() failed:%d\n", ret); + goto err_pm_runtime_put; + } + + return ret; + } + pcie =3D devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); if (!pcie) return -ENOMEM; @@ -1593,11 +1687,6 @@ static int qcom_pcie_probe(struct platform_device *p= dev) if (!pci) return -ENOMEM; =20 - pm_runtime_enable(dev); - ret =3D pm_runtime_get_sync(dev); - if (ret < 0) - goto err_pm_runtime_put; - pci->dev =3D dev; pci->ops =3D &dw_pcie_ops; pp =3D &pci->pp; @@ -1739,9 +1828,13 @@ static int qcom_pcie_probe(struct platform_device *p= dev) =20 static int qcom_pcie_suspend_noirq(struct device *dev) { - struct qcom_pcie *pcie =3D dev_get_drvdata(dev); + struct qcom_pcie *pcie; int ret =3D 0; =20 + if (of_device_is_compatible(dev->of_node, "qcom,pcie-sa8255p")) + return 0; + + pcie =3D dev_get_drvdata(dev); /* * Set minimum bandwidth required to keep data path functional during * suspend. @@ -1795,9 +1888,13 @@ static int qcom_pcie_suspend_noirq(struct device *de= v) =20 static int qcom_pcie_resume_noirq(struct device *dev) { - struct qcom_pcie *pcie =3D dev_get_drvdata(dev); + struct qcom_pcie *pcie; int ret; =20 + if (of_device_is_compatible(dev->of_node, "qcom,pcie-sa8255p")) + return 0; + + pcie =3D dev_get_drvdata(dev); if (pm_suspend_target_state !=3D PM_SUSPEND_MEM) { ret =3D icc_enable(pcie->icc_cpu); if (ret) { @@ -1830,6 +1927,7 @@ static const struct of_device_id qcom_pcie_match[] = =3D { { .compatible =3D "qcom,pcie-ipq8074-gen3", .data =3D &cfg_2_9_0 }, { .compatible =3D "qcom,pcie-msm8996", .data =3D &cfg_2_3_2 }, { .compatible =3D "qcom,pcie-qcs404", .data =3D &cfg_2_4_0 }, + { .compatible =3D "qcom,pcie-sa8255p", .data =3D &cfg_fw_managed }, { .compatible =3D "qcom,pcie-sa8540p", .data =3D &cfg_sc8280xp }, { .compatible =3D "qcom,pcie-sa8775p", .data =3D &cfg_1_34_0}, { .compatible =3D "qcom,pcie-sc7280", .data =3D &cfg_1_9_0 }, --=20 2.25.1