From nobody Sun Nov 24 07:43:53 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B28C207A16; Wed, 6 Nov 2024 19:21:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730920870; cv=none; b=L9MrydFK9m/h3LlXUGUd9dOpr95zAFQ87XLN7ZeE3dRFCOQbsAzlO48O2DD0xh71JUDgJKihcbryABVeTWEnL3Nqt5jq/6Uv/qI4Zz8Rcl8PR2iIgcKI6pzqjQtqDv5mjHRDeAk/3sKhHjkf0G+vpYpU6xpn7FJy+AKy4iq/fgY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730920870; c=relaxed/simple; bh=8jyV13JKHn0vIl+wBpuhM8EZ+NN4RHEftxJMCaIna00=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=m1/ZolQ3nLTzE2bYixzbtzECgizpOn52itL7J2y6fbvki9BMrJ0tE3cP7oP7DudRVKktwFgzo0O8C4q1bwP2GZOp7Eo2swmJGCd99SD4RCEL6Y4wAqv4XFVfP66o2yO91WNl2opnuZA0xld0EVF1YQpAKL0MZ9casI/fihJEH1Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=i12ueRiK; arc=none smtp.client-ip=198.175.65.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="i12ueRiK" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730920869; x=1762456869; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8jyV13JKHn0vIl+wBpuhM8EZ+NN4RHEftxJMCaIna00=; b=i12ueRiKEzsuHtoKOBMsMhW52m33V8zrBJzfRCB9nx8QbQpVITuBgssV QYmqvJAuLGgzN65wRjsG7Oxvaa7wDp7i2L5h3Rrm4LkMHeVd9bn01weeK 4Jfo0HmPH/S7APMY81uHVZyKoNFFCaJs7rs9Kiqb7Kw/kNHaQ4gY1sFeV jOvxkd6knDbn2oGCXMeKxjnkE/05bxvtE5hEor9NPdB5u0QGNjtgUMKpW 2tfTuEmbbQOzthL8p0+FeK6bAF2/Y9bXgf+5zMNX69zKu8YmfFxZkXTge 12sSnwAZZ2c/w056ML0q2KMkFyjlkwVqEUsqnNDuQ6O5xwjCzU/G38V1K A==; X-CSE-ConnectionGUID: yJy8s8MgTJ2NAz6yJBjzuw== X-CSE-MsgGUID: o6mLaOb9RT2s1FhpCfp2Yg== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="41291933" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="41291933" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2024 11:21:07 -0800 X-CSE-ConnectionGUID: 7GLWqB4ETRmTzg1kJtlu0g== X-CSE-MsgGUID: NcmQoX70Qnihkta38JlJxQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,263,1725346800"; d="scan'208";a="88695359" Received: from unknown (HELO JF5300-B11A338T.jf.intel.com) ([10.242.51.115]) by fmviesa003.fm.intel.com with ESMTP; 06 Nov 2024 11:21:06 -0800 From: Kanchana P Sridhar To: linux-kernel@vger.kernel.org, linux-mm@kvack.org, hannes@cmpxchg.org, yosryahmed@google.com, nphamcs@gmail.com, chengming.zhou@linux.dev, usamaarif642@gmail.com, ryan.roberts@arm.com, ying.huang@intel.com, 21cnbao@gmail.com, akpm@linux-foundation.org, linux-crypto@vger.kernel.org, herbert@gondor.apana.org.au, davem@davemloft.net, clabbe@baylibre.com, ardb@kernel.org, ebiggers@google.com, surenb@google.com, kristen.c.accardi@intel.com, zanussi@kernel.org Cc: wajdi.k.feghali@intel.com, vinodh.gopal@intel.com, kanchana.p.sridhar@intel.com Subject: [PATCH v3 01/13] crypto: acomp - Define two new interfaces for compress/decompress batching. Date: Wed, 6 Nov 2024 11:20:53 -0800 Message-Id: <20241106192105.6731-2-kanchana.p.sridhar@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20241106192105.6731-1-kanchana.p.sridhar@intel.com> References: <20241106192105.6731-1-kanchana.p.sridhar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This commit adds batch_compress() and batch_decompress() interfaces to: struct acomp_alg struct crypto_acomp This allows the iaa_crypto Intel IAA driver to register implementation for batch_compress() and batch_decompress() API, that can subsequently be invoked from the kernel zswap/zram swap modules to compress/decompress up to CRYPTO_BATCH_SIZE (i.e. 8) pages in parallel in the IAA hardware accelerator to improve swapout/swapin performance. Signed-off-by: Kanchana P Sridhar --- crypto/acompress.c | 2 + include/crypto/acompress.h | 82 +++++++++++++++++++++++++++++ include/crypto/internal/acompress.h | 16 ++++++ 3 files changed, 100 insertions(+) diff --git a/crypto/acompress.c b/crypto/acompress.c index 6fdf0ff9f3c0..a506db499a37 100644 --- a/crypto/acompress.c +++ b/crypto/acompress.c @@ -71,6 +71,8 @@ static int crypto_acomp_init_tfm(struct crypto_tfm *tfm) =20 acomp->compress =3D alg->compress; acomp->decompress =3D alg->decompress; + acomp->batch_compress =3D alg->batch_compress; + acomp->batch_decompress =3D alg->batch_decompress; acomp->dst_free =3D alg->dst_free; acomp->reqsize =3D alg->reqsize; =20 diff --git a/include/crypto/acompress.h b/include/crypto/acompress.h index 54937b615239..ab0d9987bde1 100644 --- a/include/crypto/acompress.h +++ b/include/crypto/acompress.h @@ -37,12 +37,20 @@ struct acomp_req { void *__ctx[] CRYPTO_MINALIGN_ATTR; }; =20 +/* + * The max compress/decompress batch size, for crypto algorithms + * that support batch_compress and batch_decompress API. + */ +#define CRYPTO_BATCH_SIZE 8UL + /** * struct crypto_acomp - user-instantiated objects which encapsulate * algorithms and core processing logic * * @compress: Function performs a compress operation * @decompress: Function performs a de-compress operation + * @batch_compress: Function performs a batch compress operation + * @batch_decompress: Function performs a batch decompress operation * @dst_free: Frees destination buffer if allocated inside the * algorithm * @reqsize: Context size for (de)compression requests @@ -51,6 +59,20 @@ struct acomp_req { struct crypto_acomp { int (*compress)(struct acomp_req *req); int (*decompress)(struct acomp_req *req); + void (*batch_compress)(struct acomp_req *reqs[], + struct crypto_wait *wait, + struct page *pages[], + u8 *dsts[], + unsigned int dlens[], + int errors[], + int nr_pages); + void (*batch_decompress)(struct acomp_req *reqs[], + struct crypto_wait *wait, + u8 *srcs[], + struct page *pages[], + unsigned int slens[], + int errors[], + int nr_pages); void (*dst_free)(struct scatterlist *dst); unsigned int reqsize; struct crypto_tfm base; @@ -265,4 +287,64 @@ static inline int crypto_acomp_decompress(struct acomp= _req *req) return crypto_acomp_reqtfm(req)->decompress(req); } =20 +/** + * crypto_acomp_batch_compress() -- compress a batch of requests + * + * Function invokes the batch compress operation + * + * @reqs: @nr_pages asynchronous compress requests. + * @wait: crypto_wait for synchronous acomp batch compress. If NULL, the + * driver must provide a way to process completions asynchronously. + * @pages: Pages to be compressed. + * @dsts: Pre-allocated destination buffers to store results of compressio= n. + * @dlens: Will contain the compressed lengths. + * @errors: zero on successful compression of the corresponding + * req, or error code in case of error. + * @nr_pages: The number of pages, up to CRYPTO_BATCH_SIZE, + * to be compressed. + */ +static inline void crypto_acomp_batch_compress(struct acomp_req *reqs[], + struct crypto_wait *wait, + struct page *pages[], + u8 *dsts[], + unsigned int dlens[], + int errors[], + int nr_pages) +{ + struct crypto_acomp *tfm =3D crypto_acomp_reqtfm(reqs[0]); + + return tfm->batch_compress(reqs, wait, pages, dsts, + dlens, errors, nr_pages); +} + +/** + * crypto_acomp_batch_decompress() -- decompress a batch of requests + * + * Function invokes the batch decompress operation + * + * @reqs: @nr_pages asynchronous decompress requests. + * @wait: crypto_wait for synchronous acomp batch decompress. If NULL, the + * driver must provide a way to process completions asynchronously. + * @srcs: The src buffers to be decompressed. + * @pages: The pages to store the decompressed buffers. + * @slens: Compressed lengths of @srcs. + * @errors: zero on successful compression of the corresponding + * req, or error code in case of error. + * @nr_pages: The number of pages, up to CRYPTO_BATCH_SIZE, + * to be decompressed. + */ +static inline void crypto_acomp_batch_decompress(struct acomp_req *reqs[], + struct crypto_wait *wait, + u8 *srcs[], + struct page *pages[], + unsigned int slens[], + int errors[], + int nr_pages) +{ + struct crypto_acomp *tfm =3D crypto_acomp_reqtfm(reqs[0]); + + return tfm->batch_decompress(reqs, wait, srcs, pages, + slens, errors, nr_pages); +} + #endif diff --git a/include/crypto/internal/acompress.h b/include/crypto/internal/= acompress.h index 8831edaafc05..acfe2d9d5a83 100644 --- a/include/crypto/internal/acompress.h +++ b/include/crypto/internal/acompress.h @@ -17,6 +17,8 @@ * * @compress: Function performs a compress operation * @decompress: Function performs a de-compress operation + * @batch_compress: Function performs a batch compress operation + * @batch_decompress: Function performs a batch decompress operation * @dst_free: Frees destination buffer if allocated inside the algorithm * @init: Initialize the cryptographic transformation object. * This function is used to initialize the cryptographic @@ -37,6 +39,20 @@ struct acomp_alg { int (*compress)(struct acomp_req *req); int (*decompress)(struct acomp_req *req); + void (*batch_compress)(struct acomp_req *reqs[], + struct crypto_wait *wait, + struct page *pages[], + u8 *dsts[], + unsigned int dlens[], + int errors[], + int nr_pages); + void (*batch_decompress)(struct acomp_req *reqs[], + struct crypto_wait *wait, + u8 *srcs[], + struct page *pages[], + unsigned int slens[], + int errors[], + int nr_pages); void (*dst_free)(struct scatterlist *dst); int (*init)(struct crypto_acomp *tfm); void (*exit)(struct crypto_acomp *tfm); --=20 2.27.0 From nobody Sun Nov 24 07:43:53 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D15F320ADC2; Wed, 6 Nov 2024 19:21:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730920871; 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06 Nov 2024 11:21:08 -0800 X-CSE-ConnectionGUID: 45D0axoXRkqG1lvhXbXrLQ== X-CSE-MsgGUID: I5t60IOLTB+NwG+Q6dcZ5A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,263,1725346800"; d="scan'208";a="88695369" Received: from unknown (HELO JF5300-B11A338T.jf.intel.com) ([10.242.51.115]) by fmviesa003.fm.intel.com with ESMTP; 06 Nov 2024 11:21:07 -0800 From: Kanchana P Sridhar To: linux-kernel@vger.kernel.org, linux-mm@kvack.org, hannes@cmpxchg.org, yosryahmed@google.com, nphamcs@gmail.com, chengming.zhou@linux.dev, usamaarif642@gmail.com, ryan.roberts@arm.com, ying.huang@intel.com, 21cnbao@gmail.com, akpm@linux-foundation.org, linux-crypto@vger.kernel.org, herbert@gondor.apana.org.au, davem@davemloft.net, clabbe@baylibre.com, ardb@kernel.org, ebiggers@google.com, surenb@google.com, kristen.c.accardi@intel.com, zanussi@kernel.org Cc: wajdi.k.feghali@intel.com, vinodh.gopal@intel.com, kanchana.p.sridhar@intel.com Subject: [PATCH v3 02/13] crypto: iaa - Add an acomp_req flag CRYPTO_ACOMP_REQ_POLL to enable async mode. Date: Wed, 6 Nov 2024 11:20:54 -0800 Message-Id: <20241106192105.6731-3-kanchana.p.sridhar@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20241106192105.6731-1-kanchana.p.sridhar@intel.com> References: <20241106192105.6731-1-kanchana.p.sridhar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If the iaa_crypto driver has async_mode set to true, and use_irq set to false, it can still be forced to use synchronous mode by turning off the CRYPTO_ACOMP_REQ_POLL flag in req->flags. All three of the following need to be true for a request to be processed in fully async poll mode: 1) async_mode should be "true" 2) use_irq should be "false" 3) req->flags & CRYPTO_ACOMP_REQ_POLL should be "true" Suggested-by: Herbert Xu Signed-off-by: Kanchana P Sridhar --- drivers/crypto/intel/iaa/iaa_crypto_main.c | 11 ++++++++++- include/crypto/acompress.h | 5 +++++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/intel/iaa/iaa_crypto_main.c b/drivers/crypto/in= tel/iaa/iaa_crypto_main.c index 237f87000070..2edaecd42cc6 100644 --- a/drivers/crypto/intel/iaa/iaa_crypto_main.c +++ b/drivers/crypto/intel/iaa/iaa_crypto_main.c @@ -1510,6 +1510,10 @@ static int iaa_comp_acompress(struct acomp_req *req) return -EINVAL; } =20 + /* If the caller has requested no polling, disable async. */ + if (!(req->flags & CRYPTO_ACOMP_REQ_POLL)) + disable_async =3D true; + cpu =3D get_cpu(); wq =3D wq_table_next_wq(cpu); put_cpu(); @@ -1702,6 +1706,7 @@ static int iaa_comp_adecompress(struct acomp_req *req) { struct crypto_tfm *tfm =3D req->base.tfm; dma_addr_t src_addr, dst_addr; + bool disable_async =3D false; int nr_sgs, cpu, ret =3D 0; struct iaa_wq *iaa_wq; struct device *dev; @@ -1717,6 +1722,10 @@ static int iaa_comp_adecompress(struct acomp_req *re= q) return -EINVAL; } =20 + /* If the caller has requested no polling, disable async. */ + if (!(req->flags & CRYPTO_ACOMP_REQ_POLL)) + disable_async =3D true; + if (!req->dst) return iaa_comp_adecompress_alloc_dest(req); =20 @@ -1765,7 +1774,7 @@ static int iaa_comp_adecompress(struct acomp_req *req) req->dst, req->dlen, sg_dma_len(req->dst)); =20 ret =3D iaa_decompress(tfm, req, wq, src_addr, req->slen, - dst_addr, &req->dlen, false); + dst_addr, &req->dlen, disable_async); if (ret =3D=3D -EINPROGRESS) return ret; =20 diff --git a/include/crypto/acompress.h b/include/crypto/acompress.h index ab0d9987bde1..5973f5f67954 100644 --- a/include/crypto/acompress.h +++ b/include/crypto/acompress.h @@ -14,6 +14,11 @@ #include =20 #define CRYPTO_ACOMP_ALLOC_OUTPUT 0x00000001 +/* + * If set, the driver must have a way to submit the req, then + * poll its completion status for success/error. + */ +#define CRYPTO_ACOMP_REQ_POLL 0x00000002 #define CRYPTO_ACOMP_DST_MAX 131072 =20 /** --=20 2.27.0 From nobody Sun Nov 24 07:43:53 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B9E520ADD0; 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a="41291958" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="41291958" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2024 11:21:09 -0800 X-CSE-ConnectionGUID: YnR07wRTSxqUng2Og5HOsw== X-CSE-MsgGUID: VUfqMGvuRHiegyDSKYUhJA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,263,1725346800"; d="scan'208";a="88695374" Received: from unknown (HELO JF5300-B11A338T.jf.intel.com) ([10.242.51.115]) by fmviesa003.fm.intel.com with ESMTP; 06 Nov 2024 11:21:08 -0800 From: Kanchana P Sridhar To: linux-kernel@vger.kernel.org, linux-mm@kvack.org, hannes@cmpxchg.org, yosryahmed@google.com, nphamcs@gmail.com, chengming.zhou@linux.dev, usamaarif642@gmail.com, ryan.roberts@arm.com, ying.huang@intel.com, 21cnbao@gmail.com, akpm@linux-foundation.org, linux-crypto@vger.kernel.org, herbert@gondor.apana.org.au, davem@davemloft.net, clabbe@baylibre.com, ardb@kernel.org, ebiggers@google.com, surenb@google.com, kristen.c.accardi@intel.com, zanussi@kernel.org Cc: wajdi.k.feghali@intel.com, vinodh.gopal@intel.com, kanchana.p.sridhar@intel.com Subject: [PATCH v3 03/13] crypto: iaa - Implement compress/decompress batching API in iaa_crypto. Date: Wed, 6 Nov 2024 11:20:55 -0800 Message-Id: <20241106192105.6731-4-kanchana.p.sridhar@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20241106192105.6731-1-kanchana.p.sridhar@intel.com> References: <20241106192105.6731-1-kanchana.p.sridhar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch provides iaa_crypto driver implementations for the newly added crypto_acomp batch_compress() and batch_decompress() interfaces. This allows swap modules such as zswap/zram to invoke batch parallel compression/decompression of pages on systems with Intel IAA, by invoking these API, respectively: crypto_acomp_batch_compress(...); crypto_acomp_batch_decompress(...); This enables zswap_store() compress batching code to be developed in a manner similar to the current single-page synchronous calls to: crypto_acomp_compress(...); crypto_acomp_decompress(...); thereby, facilitating encapsulated and modular hand-off between the kernel zswap/zram code and the crypto_acomp layer. Suggested-by: Yosry Ahmed Suggested-by: Herbert Xu Signed-off-by: Kanchana P Sridhar --- drivers/crypto/intel/iaa/iaa_crypto_main.c | 313 +++++++++++++++++++++ 1 file changed, 313 insertions(+) diff --git a/drivers/crypto/intel/iaa/iaa_crypto_main.c b/drivers/crypto/in= tel/iaa/iaa_crypto_main.c index 2edaecd42cc6..3ac3a37fd2e6 100644 --- a/drivers/crypto/intel/iaa/iaa_crypto_main.c +++ b/drivers/crypto/intel/iaa/iaa_crypto_main.c @@ -1797,6 +1797,317 @@ static void compression_ctx_init(struct iaa_compres= sion_ctx *ctx) ctx->use_irq =3D use_irq; } =20 +static int iaa_comp_poll(struct acomp_req *req) +{ + struct idxd_desc *idxd_desc; + struct idxd_device *idxd; + struct iaa_wq *iaa_wq; + struct pci_dev *pdev; + struct device *dev; + struct idxd_wq *wq; + bool compress_op; + int ret; + + idxd_desc =3D req->base.data; + if (!idxd_desc) + return -EAGAIN; + + compress_op =3D (idxd_desc->iax_hw->opcode =3D=3D IAX_OPCODE_COMPRESS); + wq =3D idxd_desc->wq; + iaa_wq =3D idxd_wq_get_private(wq); + idxd =3D iaa_wq->iaa_device->idxd; + pdev =3D idxd->pdev; + dev =3D &pdev->dev; + + ret =3D check_completion(dev, idxd_desc->iax_completion, true, true); + if (ret =3D=3D -EAGAIN) + return ret; + if (ret) + goto out; + + req->dlen =3D idxd_desc->iax_completion->output_size; + + /* Update stats */ + if (compress_op) { + update_total_comp_bytes_out(req->dlen); + update_wq_comp_bytes(wq, req->dlen); + } else { + update_total_decomp_bytes_in(req->slen); + update_wq_decomp_bytes(wq, req->slen); + } + + if (iaa_verify_compress && (idxd_desc->iax_hw->opcode =3D=3D IAX_OPCODE_C= OMPRESS)) { + struct crypto_tfm *tfm =3D req->base.tfm; + dma_addr_t src_addr, dst_addr; + u32 compression_crc; + + compression_crc =3D idxd_desc->iax_completion->crc; + + dma_sync_sg_for_device(dev, req->dst, 1, DMA_FROM_DEVICE); + dma_sync_sg_for_device(dev, req->src, 1, DMA_TO_DEVICE); + + src_addr =3D sg_dma_address(req->src); + dst_addr =3D sg_dma_address(req->dst); + + ret =3D iaa_compress_verify(tfm, req, wq, src_addr, req->slen, + dst_addr, &req->dlen, compression_crc); + } +out: + /* caller doesn't call crypto_wait_req, so no acomp_request_complete() */ + + dma_unmap_sg(dev, req->dst, sg_nents(req->dst), DMA_FROM_DEVICE); + dma_unmap_sg(dev, req->src, sg_nents(req->src), DMA_TO_DEVICE); + + idxd_free_desc(idxd_desc->wq, idxd_desc); + + dev_dbg(dev, "%s: returning ret=3D%d\n", __func__, ret); + + return ret; +} + +static void iaa_set_req_poll( + struct acomp_req *reqs[], + int nr_reqs, + bool set_flag) +{ + int i; + + for (i =3D 0; i < nr_reqs; ++i) { + set_flag ? (reqs[i]->flags |=3D CRYPTO_ACOMP_REQ_POLL) : + (reqs[i]->flags &=3D ~CRYPTO_ACOMP_REQ_POLL); + } +} + +/** + * This API provides IAA compress batching functionality for use by swap + * modules. + * + * @reqs: @nr_pages asynchronous compress requests. + * @wait: crypto_wait for synchronous acomp batch compress. If NULL, the + * completions will be processed asynchronously. + * @pages: Pages to be compressed by IAA in parallel. + * @dsts: Pre-allocated destination buffers to store results of IAA + * compression. Each element of @dsts must be of size "PAGE_SIZE * = 2". + * @dlens: Will contain the compressed lengths. + * @errors: zero on successful compression of the corresponding + * req, or error code in case of error. + * @nr_pages: The number of pages, up to CRYPTO_BATCH_SIZE, + * to be compressed. + */ +static void iaa_comp_acompress_batch( + struct acomp_req *reqs[], + struct crypto_wait *wait, + struct page *pages[], + u8 *dsts[], + unsigned int dlens[], + int errors[], + int nr_pages) +{ + struct scatterlist inputs[CRYPTO_BATCH_SIZE]; + struct scatterlist outputs[CRYPTO_BATCH_SIZE]; + bool compressions_done =3D false; + bool poll =3D (async_mode && !use_irq); + int i; + + BUG_ON(nr_pages > CRYPTO_BATCH_SIZE); + BUG_ON(!poll && !wait); + + if (poll) + iaa_set_req_poll(reqs, nr_pages, true); + else + iaa_set_req_poll(reqs, nr_pages, false); + + /* + * Prepare and submit acomp_reqs to IAA. IAA will process these + * compress jobs in parallel if async-poll mode is enabled. + * If IAA is used in sync mode, the jobs will be processed sequentially + * using "wait". + */ + for (i =3D 0; i < nr_pages; ++i) { + sg_init_table(&inputs[i], 1); + sg_set_page(&inputs[i], pages[i], PAGE_SIZE, 0); + + /* + * Each dst buffer should be of size (PAGE_SIZE * 2). + * Reflect same in sg_list. + */ + sg_init_one(&outputs[i], dsts[i], PAGE_SIZE * 2); + acomp_request_set_params(reqs[i], &inputs[i], + &outputs[i], PAGE_SIZE, dlens[i]); + + /* + * If poll is in effect, submit the request now, and poll for + * a completion status later, after all descriptors have been + * submitted. If polling is not enabled, submit the request + * and wait for it to complete, i.e., synchronously, before + * moving on to the next request. + */ + if (poll) { + errors[i] =3D iaa_comp_acompress(reqs[i]); + + if (errors[i] !=3D -EINPROGRESS) + errors[i] =3D -EINVAL; + else + errors[i] =3D -EAGAIN; + } else { + acomp_request_set_callback(reqs[i], + CRYPTO_TFM_REQ_MAY_BACKLOG, + crypto_req_done, wait); + errors[i] =3D crypto_wait_req(iaa_comp_acompress(reqs[i]), + wait); + if (!errors[i]) + dlens[i] =3D reqs[i]->dlen; + } + } + + /* + * If not doing async compressions, the batch has been processed at + * this point and we can return. + */ + if (!poll) + return; + + /* + * Poll for and process IAA compress job completions + * in out-of-order manner. + */ + while (!compressions_done) { + compressions_done =3D true; + + for (i =3D 0; i < nr_pages; ++i) { + /* + * Skip, if the compression has already completed + * successfully or with an error. + */ + if (errors[i] !=3D -EAGAIN) + continue; + + errors[i] =3D iaa_comp_poll(reqs[i]); + + if (errors[i]) { + if (errors[i] =3D=3D -EAGAIN) + compressions_done =3D false; + } else { + dlens[i] =3D reqs[i]->dlen; + } + } + } +} + +/** + * This API provides IAA decompress batching functionality for use by swap + * modules. + * + * @reqs: @nr_pages asynchronous decompress requests. + * @wait: crypto_wait for synchronous acomp batch decompress. If NULL, the + * driver must provide a way to process completions asynchronously. + * @srcs: The src buffers to be decompressed by IAA in parallel. + * @pages: The pages to store the decompressed buffers. + * @slens: Compressed lengths of @srcs. + * @errors: zero on successful compression of the corresponding + * req, or error code in case of error. + * @nr_pages: The number of pages, up to CRYPTO_BATCH_SIZE, + * to be decompressed. + */ +static void iaa_comp_adecompress_batch( + struct acomp_req *reqs[], + struct crypto_wait *wait, + u8 *srcs[], + struct page *pages[], + unsigned int slens[], + int errors[], + int nr_pages) +{ + struct scatterlist inputs[CRYPTO_BATCH_SIZE]; + struct scatterlist outputs[CRYPTO_BATCH_SIZE]; + unsigned int dlens[CRYPTO_BATCH_SIZE]; + bool decompressions_done =3D false; + bool poll =3D (async_mode && !use_irq); + int i; + + BUG_ON(nr_pages > CRYPTO_BATCH_SIZE); + BUG_ON(!poll && !wait); + + if (poll) + iaa_set_req_poll(reqs, nr_pages, true); + else + iaa_set_req_poll(reqs, nr_pages, false); + + /* + * Prepare and submit acomp_reqs to IAA. IAA will process these + * decompress jobs in parallel if async-poll mode is enabled. + * If IAA is used in sync mode, the jobs will be processed sequentially + * using "wait". + */ + for (i =3D 0; i < nr_pages; ++i) { + dlens[i] =3D PAGE_SIZE; + sg_init_one(&inputs[i], srcs[i], slens[i]); + sg_init_table(&outputs[i], 1); + sg_set_page(&outputs[i], pages[i], PAGE_SIZE, 0); + acomp_request_set_params(reqs[i], &inputs[i], + &outputs[i], slens[i], dlens[i]); + /* + * If poll is in effect, submit the request now, and poll for + * a completion status later, after all descriptors have been + * submitted. If polling is not enabled, submit the request + * and wait for it to complete, i.e., synchronously, before + * moving on to the next request. + */ + if (poll) { + errors[i] =3D iaa_comp_adecompress(reqs[i]); + + if (errors[i] !=3D -EINPROGRESS) + errors[i] =3D -EINVAL; + else + errors[i] =3D -EAGAIN; + } else { + acomp_request_set_callback(reqs[i], + CRYPTO_TFM_REQ_MAY_BACKLOG, + crypto_req_done, wait); + errors[i] =3D crypto_wait_req(iaa_comp_adecompress(reqs[i]), + wait); + if (!errors[i]) { + dlens[i] =3D reqs[i]->dlen; + BUG_ON(dlens[i] !=3D PAGE_SIZE); + } + } + } + + /* + * If not doing async decompressions, the batch has been processed at + * this point and we can return. + */ + if (!poll) + return; + + /* + * Poll for and process IAA decompress job completions + * in out-of-order manner. + */ + while (!decompressions_done) { + decompressions_done =3D true; + + for (i =3D 0; i < nr_pages; ++i) { + /* + * Skip, if the decompression has already completed + * successfully or with an error. + */ + if (errors[i] !=3D -EAGAIN) + continue; + + errors[i] =3D iaa_comp_poll(reqs[i]); + + if (errors[i]) { + if (errors[i] =3D=3D -EAGAIN) + decompressions_done =3D false; + } else { + dlens[i] =3D reqs[i]->dlen; + BUG_ON(dlens[i] !=3D PAGE_SIZE); + } + } + } +} + static int iaa_comp_init_fixed(struct crypto_acomp *acomp_tfm) { struct crypto_tfm *tfm =3D crypto_acomp_tfm(acomp_tfm); @@ -1822,6 +2133,8 @@ static struct acomp_alg iaa_acomp_fixed_deflate =3D { .compress =3D iaa_comp_acompress, .decompress =3D iaa_comp_adecompress, .dst_free =3D dst_free, + .batch_compress =3D iaa_comp_acompress_batch, + .batch_decompress =3D iaa_comp_adecompress_batch, .base =3D { .cra_name =3D "deflate", .cra_driver_name =3D "deflate-iaa", --=20 2.27.0 From nobody Sun Nov 24 07:43:53 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 298EB20ADE4; Wed, 6 Nov 2024 19:21:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a="41291972" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="41291972" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2024 11:21:09 -0800 X-CSE-ConnectionGUID: npxTDlYWQ0e93T1biJ33MA== X-CSE-MsgGUID: tQcgnDEyR0mPpreuHOVDRQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,263,1725346800"; d="scan'208";a="88695381" Received: from unknown (HELO JF5300-B11A338T.jf.intel.com) ([10.242.51.115]) by fmviesa003.fm.intel.com with ESMTP; 06 Nov 2024 11:21:08 -0800 From: Kanchana P Sridhar To: linux-kernel@vger.kernel.org, linux-mm@kvack.org, hannes@cmpxchg.org, yosryahmed@google.com, nphamcs@gmail.com, chengming.zhou@linux.dev, usamaarif642@gmail.com, ryan.roberts@arm.com, ying.huang@intel.com, 21cnbao@gmail.com, akpm@linux-foundation.org, linux-crypto@vger.kernel.org, herbert@gondor.apana.org.au, davem@davemloft.net, clabbe@baylibre.com, ardb@kernel.org, ebiggers@google.com, surenb@google.com, kristen.c.accardi@intel.com, zanussi@kernel.org Cc: wajdi.k.feghali@intel.com, vinodh.gopal@intel.com, kanchana.p.sridhar@intel.com Subject: [PATCH v3 04/13] crypto: iaa - Make async mode the default. Date: Wed, 6 Nov 2024 11:20:56 -0800 Message-Id: <20241106192105.6731-5-kanchana.p.sridhar@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20241106192105.6731-1-kanchana.p.sridhar@intel.com> References: <20241106192105.6731-1-kanchana.p.sridhar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch makes it easier for IAA hardware acceleration in the iaa_crypto driver to be loaded by default in the most efficient/recommended "async" mode for parallel compressions/decompressions, namely, asynchronous submission of descriptors, followed by polling for job completions. Earlier, the "sync" mode used to be the default. This way, anyone that wants to use IAA can do so after building the kernel, and without having to go through these steps to use async poll: 1) disable all the IAA device/wq bindings that happen at boot time 2) rmmod iaa_crypto 3) modprobe iaa_crypto 4) echo async > /sys/bus/dsa/drivers/crypto/sync_mode 5) re-run initialization of the IAA devices and wqs Signed-off-by: Kanchana P Sridhar --- drivers/crypto/intel/iaa/iaa_crypto_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/crypto/intel/iaa/iaa_crypto_main.c b/drivers/crypto/in= tel/iaa/iaa_crypto_main.c index 3ac3a37fd2e6..13f9d22811ff 100644 --- a/drivers/crypto/intel/iaa/iaa_crypto_main.c +++ b/drivers/crypto/intel/iaa/iaa_crypto_main.c @@ -153,7 +153,7 @@ static DRIVER_ATTR_RW(verify_compress); */ =20 /* Use async mode */ -static bool async_mode; +static bool async_mode =3D true; /* Use interrupts */ static bool use_irq; =20 --=20 2.27.0 From nobody Sun Nov 24 07:43:53 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BDD1D20B1ED; Wed, 6 Nov 2024 19:21:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730920873; cv=none; b=PM1VQVIV+GqguVHHn5XPpr/t7m+sPT7pxBdomWa2b0RoAUPrk0bFy4DnkGiaxKMKyfaxFlkMRzhWKNHyFOB+ASz7x+eIHC0Nklcu7thGYvaqcNpOZGgE97IbxTsLlY62ZWY0UYd15bDjSgN6PbKk/JYytrFK2teujP7lLJazFzc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730920873; c=relaxed/simple; bh=yFcfU2b3t6Krq275SHD6OXxnKnpJ7Jmrcy/87R0bztw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hF2BxYrjP/vJROk5uL8o/2zIEKHhEEOrqh0Wpa1qF/JrU6Ae9GauL4RW7zJ8bd5waxSTZCmN3QwYUdIkn+iGJU5PcXoqh4Bm3oYZ1MJnlXkJfoZHdB5tsSrVRkvAMCMUZfH2K5d09z4KuwgoP5tPqdggwQmIYTSBPt/c+0EK7yo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=RWxPAdgx; arc=none smtp.client-ip=198.175.65.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="RWxPAdgx" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730920872; x=1762456872; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yFcfU2b3t6Krq275SHD6OXxnKnpJ7Jmrcy/87R0bztw=; b=RWxPAdgxylYjUG53rTJ8A4T/7bkhZo95xssy3o/3sj1GmK/FpKVEzAeR DYLRyB/rcfhGvjGeh9+SBTddYjFTRQ3JxLjnvvFse4NCZC9cvHUedhmzA VF4xZXq2xQrVhG0ZDj1o+U2XC7ZmfovD3s9la0NFeb9V/FCjybiY/wVid GGa6ASV7vumFaXSu24XUUbb+o3noy4NnbzoyQ8twcZFGqnX7/XadPMk1o ifUXt8L2PjiTEWhSyEG8iGUN/IQaKE8ki5XX8NhR3YfJpDd7mgIcbwS7U KGwJ+5Xoryy9lfRKjUlSt3dbrT7VgQOQ6aGPXglWcDDrlfPkcNfnZ7cKk Q==; X-CSE-ConnectionGUID: id3Y6l5VTFeDCCvN939Jbw== X-CSE-MsgGUID: 3kkLtd0CSdGNyyLrW5G2Bg== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="41291984" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="41291984" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2024 11:21:10 -0800 X-CSE-ConnectionGUID: X7LtG8ZhSOm9GUcPjmI2MQ== X-CSE-MsgGUID: Ch43AaPUSz63XfnLGxWmQg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,263,1725346800"; d="scan'208";a="88695388" Received: from unknown (HELO JF5300-B11A338T.jf.intel.com) ([10.242.51.115]) by fmviesa003.fm.intel.com with ESMTP; 06 Nov 2024 11:21:09 -0800 From: Kanchana P Sridhar To: linux-kernel@vger.kernel.org, linux-mm@kvack.org, hannes@cmpxchg.org, yosryahmed@google.com, nphamcs@gmail.com, chengming.zhou@linux.dev, usamaarif642@gmail.com, ryan.roberts@arm.com, ying.huang@intel.com, 21cnbao@gmail.com, akpm@linux-foundation.org, linux-crypto@vger.kernel.org, herbert@gondor.apana.org.au, davem@davemloft.net, clabbe@baylibre.com, ardb@kernel.org, ebiggers@google.com, surenb@google.com, kristen.c.accardi@intel.com, zanussi@kernel.org Cc: wajdi.k.feghali@intel.com, vinodh.gopal@intel.com, kanchana.p.sridhar@intel.com Subject: [PATCH v3 05/13] crypto: iaa - Disable iaa_verify_compress by default. Date: Wed, 6 Nov 2024 11:20:57 -0800 Message-Id: <20241106192105.6731-6-kanchana.p.sridhar@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20241106192105.6731-1-kanchana.p.sridhar@intel.com> References: <20241106192105.6731-1-kanchana.p.sridhar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch makes it easier for IAA hardware acceleration in the iaa_crypto driver to be loaded by default with "iaa_verify_compress" disabled, to facilitate performance comparisons with software compressors (which also do not run compress verification by default). Earlier, iaa_crypto compress verification used to be enabled by default. With this patch, if users want to enable compress verification, they can do so with these steps: 1) disable all the IAA device/wq bindings that happen at boot time 2) rmmod iaa_crypto 3) modprobe iaa_crypto 4) echo 1 > /sys/bus/dsa/drivers/crypto/verify_compress 5) re-run initialization of the IAA devices and wqs Signed-off-by: Kanchana P Sridhar --- drivers/crypto/intel/iaa/iaa_crypto_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/crypto/intel/iaa/iaa_crypto_main.c b/drivers/crypto/in= tel/iaa/iaa_crypto_main.c index 13f9d22811ff..c4b143dd1ddd 100644 --- a/drivers/crypto/intel/iaa/iaa_crypto_main.c +++ b/drivers/crypto/intel/iaa/iaa_crypto_main.c @@ -94,7 +94,7 @@ static bool iaa_crypto_enabled; static bool iaa_crypto_registered; =20 /* Verify results of IAA compress or not */ -static bool iaa_verify_compress =3D true; +static bool iaa_verify_compress =3D false; =20 static ssize_t verify_compress_show(struct device_driver *driver, char *bu= f) { --=20 2.27.0 From nobody Sun Nov 24 07:43:53 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 794FE20B215; Wed, 6 Nov 2024 19:21:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730920875; cv=none; b=Q6NcNkdiSrUoE6QLUbusaVfMLlBl/VbYqGru4e5Z/DBLldqGiOOrWiu5RTN8nZrA48IpbACmsjuzdYDhQOH9XvXuzmkzrijf2AYobXBp2Q4XtILAzTNdkd7MalCnvYMmx28bX2OT/b82hBskkBngwUii3VmYMIjp0HC5aBDBLtQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730920875; c=relaxed/simple; bh=dsGJj+DqE0i7pg9VVqHrElSTuA3RtibV8w9INDbEh+Q=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=rHbHShpWLzgG3L3TZM98TJrBZK1YmzDWDqrHncGuuPkxy81sHjiJPPBBvrUmeNY3jOku3VvzhB3/OxZIzsD+9rLRxNkq+Xa3RFHFjcoWRvab5okLMk4n3ZvKeFcCvtL4DHnbCmQZnCneF+KgYuZ8vjweBZqB1WP8CzOUHObXtTE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=XO+YyNNi; arc=none smtp.client-ip=198.175.65.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="XO+YyNNi" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730920873; x=1762456873; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dsGJj+DqE0i7pg9VVqHrElSTuA3RtibV8w9INDbEh+Q=; b=XO+YyNNiQ0RvNADCKEmBzDHpHNKrJ7UX3aKVUe180rYckDBeJuk2a4DK TF+0Ym+HHyZjdVXdS67zRmMMxG9EJsOq2Ms74m+ANVV3QhuLhNLED75Kj Z68hJAlJqxuqLyzqTOmVME2LUVJEh823pftPv2d7lXIFceLKTTCoAA6P9 lHjWasRlS+WQaavJxJ+CDmbLNHF+WWUxM1DrOarY3HsWJetcKu/9bhIzb aiOMav0LVm4Bmj44go6I02IsIsMidBB1D/79DFCzolb1in3L8H0JYfLit 4lBrWNU1V54FyLEH92degiKLPtrD15PWr1K8HAU3tz61BCzKcmKHqnszY A==; X-CSE-ConnectionGUID: tqeKeSb6S1mi/R/gFUrbjA== X-CSE-MsgGUID: KS5l0Q5hQauDjHsvgp2tAg== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="41291997" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="41291997" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2024 11:21:10 -0800 X-CSE-ConnectionGUID: OWkevIq+QMWqgKgle/FXXA== X-CSE-MsgGUID: mh/T3E6IR1CskRaqe4OZ8Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,263,1725346800"; d="scan'208";a="88695393" Received: from unknown (HELO JF5300-B11A338T.jf.intel.com) ([10.242.51.115]) by fmviesa003.fm.intel.com with ESMTP; 06 Nov 2024 11:21:10 -0800 From: Kanchana P Sridhar To: linux-kernel@vger.kernel.org, linux-mm@kvack.org, hannes@cmpxchg.org, yosryahmed@google.com, nphamcs@gmail.com, chengming.zhou@linux.dev, usamaarif642@gmail.com, ryan.roberts@arm.com, ying.huang@intel.com, 21cnbao@gmail.com, akpm@linux-foundation.org, linux-crypto@vger.kernel.org, herbert@gondor.apana.org.au, davem@davemloft.net, clabbe@baylibre.com, ardb@kernel.org, ebiggers@google.com, surenb@google.com, kristen.c.accardi@intel.com, zanussi@kernel.org Cc: wajdi.k.feghali@intel.com, vinodh.gopal@intel.com, kanchana.p.sridhar@intel.com Subject: [PATCH v3 06/13] crypto: iaa - Change cpu-to-iaa mappings to evenly balance cores to IAAs. Date: Wed, 6 Nov 2024 11:20:58 -0800 Message-Id: <20241106192105.6731-7-kanchana.p.sridhar@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20241106192105.6731-1-kanchana.p.sridhar@intel.com> References: <20241106192105.6731-1-kanchana.p.sridhar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This change distributes the cpus more evenly among the IAAs in each socket. Old algorithm to assign cpus to IAA: ------------------------------------ If "nr_cpus" =3D nr_logical_cpus (includes hyper-threading), the current algorithm determines "nr_cpus_per_node" =3D nr_cpus / nr_nodes. Hence, on a 2-socket Sapphire Rapids server where each socket has 56 cores and 4 IAA devices, nr_cpus_per_node =3D 112. Further, cpus_per_iaa =3D (nr_nodes * nr_cpus_per_node) / nr_iaa Hence, cpus_per_iaa =3D 224/8 =3D 28. The iaa_crypto driver then assigns 28 "logical" node cpus per IAA device on that node, that results in this cpu-to-iaa mapping: lscpu|grep NUMA NUMA node(s): 2 NUMA node0 CPU(s): 0-55,112-167 NUMA node1 CPU(s): 56-111,168-223 NUMA node 0: cpu 0-27 28-55 112-139 140-167 iaa iax1 iax3 iax5 iax7 NUMA node 1: cpu 56-83 84-111 168-195 196-223 iaa iax9 iax11 iax13 iax15 This appears non-optimal for a few reasons: 1) The 2 logical threads on a core will get assigned to different IAA devices. For e.g.: cpu 0: iax1 cpu 112: iax5 2) One of the logical threads on a core is assigned to an IAA that is not closest to that core. For e.g. cpu 112. 3) If numactl is used to start processes sequentially on the logical cores, some of the IAA devices on the socket could be over-subscribed, while some could be under-utilized. This patch introduces a scheme to more evenly balance the logical cores to IAA devices on a socket. New algorithm to assign cpus to IAA: ------------------------------------ We introduce a function "cpu_to_iaa()" that takes a logical cpu and returns the IAA device closest to it. If "nr_cpus" =3D nr_logical_cpus (includes hyper-threading), the new algorithm determines "nr_cpus_per_node" =3D topology_num_cores_per_package= (). Hence, on a 2-socket Sapphire Rapids server where each socket has 56 cores and 4 IAA devices, nr_cpus_per_node =3D 56. Further, cpus_per_iaa =3D (nr_nodes * nr_cpus_per_node) / nr_iaa Hence, cpus_per_iaa =3D 112/8 =3D 14. The iaa_crypto driver then assigns 14 "logical" node cpus per IAA device on that node, that results in this cpu-to-iaa mapping: NUMA node 0: cpu 0-13,112-125 14-27,126-139 28-41,140-153 42-55,154-167 iaa iax1 iax3 iax5 iax7 NUMA node 1: cpu 56-69,168-181 70-83,182-195 84-97,196-209 98-111,210-223 iaa iax9 iax11 iax13 iax15 This resolves the 3 issues with non-optimality of cpu-to-iaa mappings pointed out earlier with the existing approach. Originally-by: Tom Zanussi Signed-off-by: Kanchana P Sridhar --- drivers/crypto/intel/iaa/iaa_crypto_main.c | 84 ++++++++++++++-------- 1 file changed, 54 insertions(+), 30 deletions(-) diff --git a/drivers/crypto/intel/iaa/iaa_crypto_main.c b/drivers/crypto/in= tel/iaa/iaa_crypto_main.c index c4b143dd1ddd..a12a8f9caa84 100644 --- a/drivers/crypto/intel/iaa/iaa_crypto_main.c +++ b/drivers/crypto/intel/iaa/iaa_crypto_main.c @@ -55,6 +55,46 @@ static struct idxd_wq *wq_table_next_wq(int cpu) return entry->wqs[entry->cur_wq]; } =20 +/* + * Given a cpu, find the closest IAA instance. The idea is to try to + * choose the most appropriate IAA instance for a caller and spread + * available workqueues around to clients. + */ +static inline int cpu_to_iaa(int cpu) +{ + int node, n_cpus =3D 0, test_cpu, iaa =3D 0; + int nr_iaa_per_node; + const struct cpumask *node_cpus; + + if (!nr_nodes) + return 0; + + nr_iaa_per_node =3D nr_iaa / nr_nodes; + if (!nr_iaa_per_node) + return 0; + + for_each_online_node(node) { + node_cpus =3D cpumask_of_node(node); + if (!cpumask_test_cpu(cpu, node_cpus)) + continue; + + for_each_cpu(test_cpu, node_cpus) { + if ((n_cpus % nr_cpus_per_node) =3D=3D 0) + iaa =3D node * nr_iaa_per_node; + + if (test_cpu =3D=3D cpu) + return iaa; + + n_cpus++; + + if ((n_cpus % cpus_per_iaa) =3D=3D 0) + iaa++; + } + } + + return -1; +} + static void wq_table_add(int cpu, struct idxd_wq *wq) { struct wq_table_entry *entry =3D per_cpu_ptr(wq_table, cpu); @@ -895,8 +935,7 @@ static int wq_table_add_wqs(int iaa, int cpu) */ static void rebalance_wq_table(void) { - const struct cpumask *node_cpus; - int node, cpu, iaa =3D -1; + int cpu, iaa; =20 if (nr_iaa =3D=3D 0) return; @@ -906,37 +945,22 @@ static void rebalance_wq_table(void) =20 clear_wq_table(); =20 - if (nr_iaa =3D=3D 1) { - for (cpu =3D 0; cpu < nr_cpus; cpu++) { - if (WARN_ON(wq_table_add_wqs(0, cpu))) { - pr_debug("could not add any wqs for iaa 0 to cpu %d!\n", cpu); - return; - } - } - - return; - } - - for_each_node_with_cpus(node) { - node_cpus =3D cpumask_of_node(node); - - for (cpu =3D 0; cpu < cpumask_weight(node_cpus); cpu++) { - int node_cpu =3D cpumask_nth(cpu, node_cpus); - - if (WARN_ON(node_cpu >=3D nr_cpu_ids)) { - pr_debug("node_cpu %d doesn't exist!\n", node_cpu); - return; - } + for (cpu =3D 0; cpu < nr_cpus; cpu++) { + iaa =3D cpu_to_iaa(cpu); + pr_debug("rebalance: cpu=3D%d iaa=3D%d\n", cpu, iaa); =20 - if ((cpu % cpus_per_iaa) =3D=3D 0) - iaa++; + if (WARN_ON(iaa =3D=3D -1)) { + pr_debug("rebalance (cpu_to_iaa(%d)) failed!\n", cpu); + return; + } =20 - if (WARN_ON(wq_table_add_wqs(iaa, node_cpu))) { - pr_debug("could not add any wqs for iaa %d to cpu %d!\n", iaa, cpu); - return; - } + if (WARN_ON(wq_table_add_wqs(iaa, cpu))) { + pr_debug("could not add any wqs for iaa %d to cpu %d!\n", iaa, cpu); + return; } } + + pr_debug("Finished rebalance local wqs."); } =20 static inline int check_completion(struct device *dev, @@ -2332,7 +2356,7 @@ static int __init iaa_crypto_init_module(void) pr_err("IAA couldn't find any nodes with cpus\n"); return -ENODEV; } - nr_cpus_per_node =3D nr_cpus / nr_nodes; + nr_cpus_per_node =3D topology_num_cores_per_package(); =20 if (crypto_has_comp("deflate-generic", 0, 0)) deflate_generic_tfm =3D crypto_alloc_comp("deflate-generic", 0, 0); --=20 2.27.0 From nobody Sun Nov 24 07:43:53 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1001E20BB26; Wed, 6 Nov 2024 19:21:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; 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06 Nov 2024 11:21:11 -0800 X-CSE-ConnectionGUID: +Z5vOFvCTR6cWN9dNz77NQ== X-CSE-MsgGUID: FoxFzadKSE+f4ae5fyvaeQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,263,1725346800"; d="scan'208";a="88695396" Received: from unknown (HELO JF5300-B11A338T.jf.intel.com) ([10.242.51.115]) by fmviesa003.fm.intel.com with ESMTP; 06 Nov 2024 11:21:10 -0800 From: Kanchana P Sridhar To: linux-kernel@vger.kernel.org, linux-mm@kvack.org, hannes@cmpxchg.org, yosryahmed@google.com, nphamcs@gmail.com, chengming.zhou@linux.dev, usamaarif642@gmail.com, ryan.roberts@arm.com, ying.huang@intel.com, 21cnbao@gmail.com, akpm@linux-foundation.org, linux-crypto@vger.kernel.org, herbert@gondor.apana.org.au, davem@davemloft.net, clabbe@baylibre.com, ardb@kernel.org, ebiggers@google.com, surenb@google.com, kristen.c.accardi@intel.com, zanussi@kernel.org Cc: wajdi.k.feghali@intel.com, vinodh.gopal@intel.com, kanchana.p.sridhar@intel.com Subject: [PATCH v3 07/13] crypto: iaa - Distribute compress jobs to all IAA devices on a NUMA node. Date: Wed, 6 Nov 2024 11:20:59 -0800 Message-Id: <20241106192105.6731-8-kanchana.p.sridhar@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20241106192105.6731-1-kanchana.p.sridhar@intel.com> References: <20241106192105.6731-1-kanchana.p.sridhar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This change enables processes running on any logical core on a NUMA node to use all the IAA devices enabled on that NUMA node for compress jobs. In other words, compressions originating from any process in a node will be distributed in round-robin manner to the available IAA devices on the same socket. The main premise behind this change is to make sure that no compress engines on any IAA device are left un-utilized/under-utilized. In other words, the compress engines on all IAA devices are considered a global resource for that socket. This allows the use of all IAA devices present in a given NUMA node for (batched) compressions originating from zswap/zram, from all cores on this node. A new per-cpu "global_wq_table" implements this in the iaa_crypto driver. We can think of the global WQ per IAA as a WQ to which all cores on that socket can submit compress jobs. To avail of this feature, the user must configure 2 WQs per IAA in order to enable distribution of compress jobs to multiple IAA devices. Each IAA will have 2 WQs: wq.0 (local WQ): Used for decompress jobs from cores mapped by the cpu_to_iaa() "even balancing of logical cores to IAA devices" algorithm. wq.1 (global WQ): Used for compress jobs from *all* logical cores on that socket. The iaa_crypto driver will place all global WQs from all same-socket IAA devices in the global_wq_table per cpu on that socket. When the driver receives a compress job, it will lookup the "next" global WQ in the cpu's global_wq_table to submit the descriptor. The starting wq in the global_wq_table for each cpu is the global wq associated with the IAA nearest to it, so that we stagger the starting global wq for each process. This results in very uniform usage of all IAAs for compress jobs. Two new driver module parameters are added for this feature: g_wqs_per_iaa (default 1): /sys/bus/dsa/drivers/crypto/g_wqs_per_iaa This represents the number of global WQs that can be configured per IAA device. The default is 1, and is the recommended setting to enable the use of this feature once the user configures 2 WQs per IAA using higher level scripts as described in Documentation/driver-api/crypto/iaa/iaa-crypto.rst. g_consec_descs_per_gwq (default 1): /sys/bus/dsa/drivers/crypto/g_consec_descs_per_gwq This represents the number of consecutive compress jobs that will be submitted to the same global WQ (i.e. to the same IAA device) from a given core, before moving to the next global WQ. The default is 1, which is also the recommended setting to avail of this feature. The decompress jobs from any core will be sent to the "local" IAA, namely the one that the driver assigns with the cpu_to_iaa() mapping algorithm that evenly balances the assignment of logical cores to IAA devices on a NUMA node. On a 2-socket Sapphire Rapids server where each socket has 56 cores and 4 IAA devices, this is how the compress/decompress jobs will be mapped when the user configures 2 WQs per IAA device (which implies wq.1 will be added to the global WQ table for each logical core on that NUMA node): lscpu|grep NUMA NUMA node(s): 2 NUMA node0 CPU(s): 0-55,112-167 NUMA node1 CPU(s): 56-111,168-223 Compress jobs: -------------- NUMA node 0: All cpus (0-55,112-167) can send compress jobs to all IAA devices on the socket (iax1/iax3/iax5/iax7) in round-robin manner: iaa iax1 iax3 iax5 iax7 NUMA node 1: All cpus (56-111,168-223) can send compress jobs to all IAA devices on the socket (iax9/iax11/iax13/iax15) in round-robin manner: iaa iax9 iax11 iax13 iax15 Decompress jobs: ---------------- NUMA node 0: cpu 0-13,112-125 14-27,126-139 28-41,140-153 42-55,154-167 iaa iax1 iax3 iax5 iax7 NUMA node 1: cpu 56-69,168-181 70-83,182-195 84-97,196-209 98-111,210-223 iaa iax9 iax11 iax13 iax15 Signed-off-by: Kanchana P Sridhar --- drivers/crypto/intel/iaa/iaa_crypto_main.c | 305 ++++++++++++++++++++- 1 file changed, 290 insertions(+), 15 deletions(-) diff --git a/drivers/crypto/intel/iaa/iaa_crypto_main.c b/drivers/crypto/in= tel/iaa/iaa_crypto_main.c index a12a8f9caa84..ca0a71b8f31d 100644 --- a/drivers/crypto/intel/iaa/iaa_crypto_main.c +++ b/drivers/crypto/intel/iaa/iaa_crypto_main.c @@ -29,14 +29,23 @@ static unsigned int nr_iaa; static unsigned int nr_cpus; static unsigned int nr_nodes; static unsigned int nr_cpus_per_node; - /* Number of physical cpus sharing each iaa instance */ static unsigned int cpus_per_iaa; =20 static struct crypto_comp *deflate_generic_tfm; =20 /* Per-cpu lookup table for balanced wqs */ -static struct wq_table_entry __percpu *wq_table; +static struct wq_table_entry __percpu *wq_table =3D NULL; + +/* Per-cpu lookup table for global wqs shared by all cpus. */ +static struct wq_table_entry __percpu *global_wq_table =3D NULL; + +/* + * Per-cpu counter of consecutive descriptors allocated to + * the same wq in the global_wq_table, so that we know + * when to switch to the next wq in the global_wq_table. + */ +static int __percpu *num_consec_descs_per_wq =3D NULL; =20 static struct idxd_wq *wq_table_next_wq(int cpu) { @@ -104,26 +113,68 @@ static void wq_table_add(int cpu, struct idxd_wq *wq) =20 entry->wqs[entry->n_wqs++] =3D wq; =20 - pr_debug("%s: added iaa wq %d.%d to idx %d of cpu %d\n", __func__, - entry->wqs[entry->n_wqs - 1]->idxd->id, - entry->wqs[entry->n_wqs - 1]->id, entry->n_wqs - 1, cpu); + pr_debug("%s: added iaa local wq %d.%d to idx %d of cpu %d\n", __func__, + entry->wqs[entry->n_wqs - 1]->idxd->id, + entry->wqs[entry->n_wqs - 1]->id, entry->n_wqs - 1, cpu); +} + +static void global_wq_table_add(int cpu, struct idxd_wq *wq) +{ + struct wq_table_entry *entry =3D per_cpu_ptr(global_wq_table, cpu); + + if (WARN_ON(entry->n_wqs =3D=3D entry->max_wqs)) + return; + + entry->wqs[entry->n_wqs++] =3D wq; + + pr_debug("%s: added iaa global wq %d.%d to idx %d of cpu %d\n", __func__, + entry->wqs[entry->n_wqs - 1]->idxd->id, + entry->wqs[entry->n_wqs - 1]->id, entry->n_wqs - 1, cpu); +} + +static void global_wq_table_set_start_wq(int cpu) +{ + struct wq_table_entry *entry =3D per_cpu_ptr(global_wq_table, cpu); + int start_wq =3D (entry->n_wqs / nr_iaa) * cpu_to_iaa(cpu); + + if ((start_wq >=3D 0) && (start_wq < entry->n_wqs)) + entry->cur_wq =3D start_wq; } =20 static void wq_table_free_entry(int cpu) { struct wq_table_entry *entry =3D per_cpu_ptr(wq_table, cpu); =20 - kfree(entry->wqs); - memset(entry, 0, sizeof(*entry)); + if (entry) { + kfree(entry->wqs); + memset(entry, 0, sizeof(*entry)); + } + + entry =3D per_cpu_ptr(global_wq_table, cpu); + + if (entry) { + kfree(entry->wqs); + memset(entry, 0, sizeof(*entry)); + } } =20 static void wq_table_clear_entry(int cpu) { struct wq_table_entry *entry =3D per_cpu_ptr(wq_table, cpu); =20 - entry->n_wqs =3D 0; - entry->cur_wq =3D 0; - memset(entry->wqs, 0, entry->max_wqs * sizeof(struct idxd_wq *)); + if (entry) { + entry->n_wqs =3D 0; + entry->cur_wq =3D 0; + memset(entry->wqs, 0, entry->max_wqs * sizeof(struct idxd_wq *)); + } + + entry =3D per_cpu_ptr(global_wq_table, cpu); + + if (entry) { + entry->n_wqs =3D 0; + entry->cur_wq =3D 0; + memset(entry->wqs, 0, entry->max_wqs * sizeof(struct idxd_wq *)); + } } =20 LIST_HEAD(iaa_devices); @@ -163,6 +214,70 @@ static ssize_t verify_compress_store(struct device_dri= ver *driver, } static DRIVER_ATTR_RW(verify_compress); =20 +/* Number of global wqs per iaa*/ +static int g_wqs_per_iaa =3D 1; + +static ssize_t g_wqs_per_iaa_show(struct device_driver *driver, char *buf) +{ + return sprintf(buf, "%d\n", g_wqs_per_iaa); +} + +static ssize_t g_wqs_per_iaa_store(struct device_driver *driver, + const char *buf, size_t count) +{ + int ret =3D -EBUSY; + + mutex_lock(&iaa_devices_lock); + + if (iaa_crypto_enabled) + goto out; + + ret =3D kstrtoint(buf, 10, &g_wqs_per_iaa); + if (ret) + goto out; + + ret =3D count; +out: + mutex_unlock(&iaa_devices_lock); + + return ret; +} +static DRIVER_ATTR_RW(g_wqs_per_iaa); + +/* + * Number of consecutive descriptors to allocate from a + * given global wq before switching to the next wq in + * the global_wq_table. + */ +static int g_consec_descs_per_gwq =3D 1; + +static ssize_t g_consec_descs_per_gwq_show(struct device_driver *driver, c= har *buf) +{ + return sprintf(buf, "%d\n", g_consec_descs_per_gwq); +} + +static ssize_t g_consec_descs_per_gwq_store(struct device_driver *driver, + const char *buf, size_t count) +{ + int ret =3D -EBUSY; + + mutex_lock(&iaa_devices_lock); + + if (iaa_crypto_enabled) + goto out; + + ret =3D kstrtoint(buf, 10, &g_consec_descs_per_gwq); + if (ret) + goto out; + + ret =3D count; +out: + mutex_unlock(&iaa_devices_lock); + + return ret; +} +static DRIVER_ATTR_RW(g_consec_descs_per_gwq); + /* * The iaa crypto driver supports three 'sync' methods determining how * compressions and decompressions are performed: @@ -751,7 +866,20 @@ static void free_wq_table(void) for (cpu =3D 0; cpu < nr_cpus; cpu++) wq_table_free_entry(cpu); =20 - free_percpu(wq_table); + if (wq_table) { + free_percpu(wq_table); + wq_table =3D NULL; + } + + if (global_wq_table) { + free_percpu(global_wq_table); + global_wq_table =3D NULL; + } + + if (num_consec_descs_per_wq) { + free_percpu(num_consec_descs_per_wq); + num_consec_descs_per_wq =3D NULL; + } =20 pr_debug("freed wq table\n"); } @@ -774,6 +902,38 @@ static int alloc_wq_table(int max_wqs) } =20 entry->max_wqs =3D max_wqs; + entry->n_wqs =3D 0; + entry->cur_wq =3D 0; + } + + global_wq_table =3D alloc_percpu(struct wq_table_entry); + if (!global_wq_table) { + free_wq_table(); + return -ENOMEM; + } + + for (cpu =3D 0; cpu < nr_cpus; cpu++) { + entry =3D per_cpu_ptr(global_wq_table, cpu); + entry->wqs =3D kzalloc(GFP_KERNEL, max_wqs * sizeof(struct wq *)); + if (!entry->wqs) { + free_wq_table(); + return -ENOMEM; + } + + entry->max_wqs =3D max_wqs; + entry->n_wqs =3D 0; + entry->cur_wq =3D 0; + } + + num_consec_descs_per_wq =3D alloc_percpu(int); + if (!num_consec_descs_per_wq) { + free_wq_table(); + return -ENOMEM; + } + + for (cpu =3D 0; cpu < nr_cpus; cpu++) { + int *num_consec_descs =3D per_cpu_ptr(num_consec_descs_per_wq, cpu); + *num_consec_descs =3D 0; } =20 pr_debug("initialized wq table\n"); @@ -912,9 +1072,14 @@ static int wq_table_add_wqs(int iaa, int cpu) } =20 list_for_each_entry(iaa_wq, &found_device->wqs, list) { - wq_table_add(cpu, iaa_wq->wq); + + if (((found_device->n_wq - g_wqs_per_iaa) < 1) || + (n_wqs_added < (found_device->n_wq - g_wqs_per_iaa))) { + wq_table_add(cpu, iaa_wq->wq); + } + pr_debug("rebalance: added wq for cpu=3D%d: iaa wq %d.%d\n", - cpu, iaa_wq->wq->idxd->id, iaa_wq->wq->id); + cpu, iaa_wq->wq->idxd->id, iaa_wq->wq->id); n_wqs_added++; } =20 @@ -927,6 +1092,63 @@ static int wq_table_add_wqs(int iaa, int cpu) return ret; } =20 +static int global_wq_table_add_wqs(void) +{ + struct iaa_device *iaa_device; + int ret =3D 0, n_wqs_added; + struct idxd_device *idxd; + struct iaa_wq *iaa_wq; + struct pci_dev *pdev; + struct device *dev; + int cpu, node, node_of_cpu =3D -1; + + for (cpu =3D 0; cpu < nr_cpus; cpu++) { + +#ifdef CONFIG_NUMA + node_of_cpu =3D -1; + for_each_online_node(node) { + const struct cpumask *node_cpus; + node_cpus =3D cpumask_of_node(node); + if (!cpumask_test_cpu(cpu, node_cpus)) + continue; + node_of_cpu =3D node; + break; + } +#endif + list_for_each_entry(iaa_device, &iaa_devices, list) { + idxd =3D iaa_device->idxd; + pdev =3D idxd->pdev; + dev =3D &pdev->dev; + +#ifdef CONFIG_NUMA + if (dev && (node_of_cpu !=3D dev->numa_node)) + continue; +#endif + + if (iaa_device->n_wq <=3D g_wqs_per_iaa) + continue; + + n_wqs_added =3D 0; + + list_for_each_entry(iaa_wq, &iaa_device->wqs, list) { + + if (n_wqs_added < (iaa_device->n_wq - g_wqs_per_iaa)) { + n_wqs_added++; + } + else { + global_wq_table_add(cpu, iaa_wq->wq); + pr_debug("rebalance: added global wq for cpu=3D%d: iaa wq %d.%d\n", + cpu, iaa_wq->wq->idxd->id, iaa_wq->wq->id); + } + } + } + + global_wq_table_set_start_wq(cpu); + } + + return ret; +} + /* * Rebalance the wq table so that given a cpu, it's easy to find the * closest IAA instance. The idea is to try to choose the most @@ -961,6 +1183,7 @@ static void rebalance_wq_table(void) } =20 pr_debug("Finished rebalance local wqs."); + global_wq_table_add_wqs(); } =20 static inline int check_completion(struct device *dev, @@ -1509,6 +1732,27 @@ static int iaa_decompress(struct crypto_tfm *tfm, st= ruct acomp_req *req, goto out; } =20 +/* + * Caller should make sure to call only if the + * per_cpu_ptr "global_wq_table" is non-NULL + * and has at least one wq configured. + */ +static struct idxd_wq *global_wq_table_next_wq(int cpu) +{ + struct wq_table_entry *entry =3D per_cpu_ptr(global_wq_table, cpu); + int *num_consec_descs =3D per_cpu_ptr(num_consec_descs_per_wq, cpu); + + if ((*num_consec_descs) =3D=3D g_consec_descs_per_gwq) { + if (++entry->cur_wq >=3D entry->n_wqs) + entry->cur_wq =3D 0; + *num_consec_descs =3D 0; + } + + ++(*num_consec_descs); + + return entry->wqs[entry->cur_wq]; +} + static int iaa_comp_acompress(struct acomp_req *req) { struct iaa_compression_ctx *compression_ctx; @@ -1521,6 +1765,7 @@ static int iaa_comp_acompress(struct acomp_req *req) struct idxd_wq *wq; struct device *dev; int order =3D -1; + struct wq_table_entry *entry; =20 compression_ctx =3D crypto_tfm_ctx(tfm); =20 @@ -1539,8 +1784,15 @@ static int iaa_comp_acompress(struct acomp_req *req) disable_async =3D true; =20 cpu =3D get_cpu(); - wq =3D wq_table_next_wq(cpu); + entry =3D per_cpu_ptr(global_wq_table, cpu); + + if (!entry || entry->n_wqs =3D=3D 0) { + wq =3D wq_table_next_wq(cpu); + } else { + wq =3D global_wq_table_next_wq(cpu); + } put_cpu(); + if (!wq) { pr_debug("no wq configured for cpu=3D%d\n", cpu); return -ENODEV; @@ -2393,13 +2645,32 @@ static int __init iaa_crypto_init_module(void) goto err_sync_attr_create; } =20 + ret =3D driver_create_file(&iaa_crypto_driver.drv, + &driver_attr_g_wqs_per_iaa); + if (ret) { + pr_debug("IAA g_wqs_per_iaa attr creation failed\n"); + goto err_g_wqs_per_iaa_attr_create; + } + + ret =3D driver_create_file(&iaa_crypto_driver.drv, + &driver_attr_g_consec_descs_per_gwq); + if (ret) { + pr_debug("IAA g_consec_descs_per_gwq attr creation failed\n"); + goto err_g_consec_descs_per_gwq_attr_create; + } + if (iaa_crypto_debugfs_init()) pr_warn("debugfs init failed, stats not available\n"); =20 pr_debug("initialized\n"); out: return ret; - +err_g_consec_descs_per_gwq_attr_create: + driver_remove_file(&iaa_crypto_driver.drv, + &driver_attr_g_wqs_per_iaa); +err_g_wqs_per_iaa_attr_create: + driver_remove_file(&iaa_crypto_driver.drv, + &driver_attr_sync_mode); err_sync_attr_create: driver_remove_file(&iaa_crypto_driver.drv, &driver_attr_verify_compress); @@ -2423,6 +2694,10 @@ static void __exit iaa_crypto_cleanup_module(void) &driver_attr_sync_mode); driver_remove_file(&iaa_crypto_driver.drv, &driver_attr_verify_compress); + driver_remove_file(&iaa_crypto_driver.drv, + &driver_attr_g_wqs_per_iaa); + driver_remove_file(&iaa_crypto_driver.drv, + &driver_attr_g_consec_descs_per_gwq); idxd_driver_unregister(&iaa_crypto_driver); iaa_aecs_cleanup_fixed(); crypto_free_comp(deflate_generic_tfm); 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X-CSE-ConnectionGUID: GUVQ78v+RU6eXnqEPpUpgQ== X-CSE-MsgGUID: bpRJtHR4TKy/3DrXrjb0yA== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="41292022" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="41292022" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2024 11:21:12 -0800 X-CSE-ConnectionGUID: JuZp7wgeTZupSYi8bw+nGA== X-CSE-MsgGUID: /kRNAQktRwSLiBLyCdU2qg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,263,1725346800"; d="scan'208";a="88695402" Received: from unknown (HELO JF5300-B11A338T.jf.intel.com) ([10.242.51.115]) by fmviesa003.fm.intel.com with ESMTP; 06 Nov 2024 11:21:11 -0800 From: Kanchana P Sridhar To: linux-kernel@vger.kernel.org, linux-mm@kvack.org, hannes@cmpxchg.org, yosryahmed@google.com, nphamcs@gmail.com, chengming.zhou@linux.dev, usamaarif642@gmail.com, ryan.roberts@arm.com, ying.huang@intel.com, 21cnbao@gmail.com, akpm@linux-foundation.org, linux-crypto@vger.kernel.org, herbert@gondor.apana.org.au, davem@davemloft.net, clabbe@baylibre.com, ardb@kernel.org, ebiggers@google.com, surenb@google.com, kristen.c.accardi@intel.com, zanussi@kernel.org Cc: wajdi.k.feghali@intel.com, vinodh.gopal@intel.com, kanchana.p.sridhar@intel.com Subject: [PATCH v3 08/13] mm: zswap: acomp_ctx mutex lock/unlock optimizations. Date: Wed, 6 Nov 2024 11:21:00 -0800 Message-Id: <20241106192105.6731-9-kanchana.p.sridhar@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20241106192105.6731-1-kanchana.p.sridhar@intel.com> References: <20241106192105.6731-1-kanchana.p.sridhar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch implements two changes with respect to the acomp_ctx mutex lock: 1) The mutex lock is not acquired/released in zswap_compress(). Instead, zswap_store() acquires the mutex lock once before compressing each page in a large folio, and releases the lock once all pages in the folio have been compressed. This should reduce some compute cycles in case of large folio stores. 2) In zswap_decompress(), the mutex lock is released after the conditional zpool_unmap_handle() based on "src !=3D acomp_ctx->buffer" rather than before. This ensures that the value of "src" obtained earlier does not change. If the mutex lock is released before the comparison of "src" it is possible that another call to reclaim by the same process could obtain the mutex lock and over-write the value of "src". Signed-off-by: Kanchana P Sridhar --- mm/zswap.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/mm/zswap.c b/mm/zswap.c index f6316b66fb23..3e899fa61445 100644 --- a/mm/zswap.c +++ b/mm/zswap.c @@ -880,6 +880,9 @@ static int zswap_cpu_comp_dead(unsigned int cpu, struct= hlist_node *node) return 0; } =20 +/* + * The acomp_ctx->mutex must be locked/unlocked in the calling procedure. + */ static bool zswap_compress(struct page *page, struct zswap_entry *entry, struct zswap_pool *pool) { @@ -895,8 +898,6 @@ static bool zswap_compress(struct page *page, struct zs= wap_entry *entry, =20 acomp_ctx =3D raw_cpu_ptr(pool->acomp_ctx); =20 - mutex_lock(&acomp_ctx->mutex); - dst =3D acomp_ctx->buffer; sg_init_table(&input, 1); sg_set_page(&input, page, PAGE_SIZE, 0); @@ -949,7 +950,6 @@ static bool zswap_compress(struct page *page, struct zs= wap_entry *entry, else if (alloc_ret) zswap_reject_alloc_fail++; =20 - mutex_unlock(&acomp_ctx->mutex); return comp_ret =3D=3D 0 && alloc_ret =3D=3D 0; } =20 @@ -986,10 +986,16 @@ static void zswap_decompress(struct zswap_entry *entr= y, struct folio *folio) acomp_request_set_params(acomp_ctx->req, &input, &output, entry->length, = PAGE_SIZE); BUG_ON(crypto_wait_req(crypto_acomp_decompress(acomp_ctx->req), &acomp_ct= x->wait)); BUG_ON(acomp_ctx->req->dlen !=3D PAGE_SIZE); - mutex_unlock(&acomp_ctx->mutex); =20 if (src !=3D acomp_ctx->buffer) zpool_unmap_handle(zpool, entry->handle); + + /* + * It is safer to unlock the mutex after the check for + * "src !=3D acomp_ctx->buffer" so that the value of "src" + * does not change. + */ + mutex_unlock(&acomp_ctx->mutex); } =20 /********************************* @@ -1487,6 +1493,7 @@ bool zswap_store(struct folio *folio) { long nr_pages =3D folio_nr_pages(folio); swp_entry_t swp =3D folio->swap; + struct crypto_acomp_ctx *acomp_ctx; struct obj_cgroup *objcg =3D NULL; struct mem_cgroup *memcg =3D NULL; struct zswap_pool *pool; @@ -1526,6 +1533,9 @@ bool zswap_store(struct folio *folio) mem_cgroup_put(memcg); } =20 + acomp_ctx =3D raw_cpu_ptr(pool->acomp_ctx); + mutex_lock(&acomp_ctx->mutex); + for (index =3D 0; index < nr_pages; ++index) { struct page *page =3D folio_page(folio, index); ssize_t bytes; @@ -1547,6 +1557,7 @@ bool zswap_store(struct folio *folio) ret =3D true; =20 put_pool: + mutex_unlock(&acomp_ctx->mutex); zswap_pool_put(pool); put_objcg: obj_cgroup_put(objcg); --=20 2.27.0 From nobody Sun Nov 24 07:43:53 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55D8A20C03E; Wed, 6 Nov 2024 19:21:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730920877; cv=none; b=RxchoS6FNUBH86PqRYM6tH54OnwoQKF8MRVjhPsxr45Ybe2styTq99jEPO8eToAAlG9/SsygY5yGAxwsqvXAzcSc2OgoBZyfIsDyCGdexlOWFC1c3Iv0gkHbDtjVcftDRMi8iVY6RHJuybi1RQW2Ai3BHOK0x48HX+ZKPgnJMdc= ARC-Message-Signature: i=1; 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d="scan'208";a="88695405" Received: from unknown (HELO JF5300-B11A338T.jf.intel.com) ([10.242.51.115]) by fmviesa003.fm.intel.com with ESMTP; 06 Nov 2024 11:21:11 -0800 From: Kanchana P Sridhar To: linux-kernel@vger.kernel.org, linux-mm@kvack.org, hannes@cmpxchg.org, yosryahmed@google.com, nphamcs@gmail.com, chengming.zhou@linux.dev, usamaarif642@gmail.com, ryan.roberts@arm.com, ying.huang@intel.com, 21cnbao@gmail.com, akpm@linux-foundation.org, linux-crypto@vger.kernel.org, herbert@gondor.apana.org.au, davem@davemloft.net, clabbe@baylibre.com, ardb@kernel.org, ebiggers@google.com, surenb@google.com, kristen.c.accardi@intel.com, zanussi@kernel.org Cc: wajdi.k.feghali@intel.com, vinodh.gopal@intel.com, kanchana.p.sridhar@intel.com Subject: [PATCH v3 09/13] mm: zswap: Modify struct crypto_acomp_ctx to be configurable in nr of acomp_reqs. Date: Wed, 6 Nov 2024 11:21:01 -0800 Message-Id: <20241106192105.6731-10-kanchana.p.sridhar@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20241106192105.6731-1-kanchana.p.sridhar@intel.com> References: <20241106192105.6731-1-kanchana.p.sridhar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Modified the definition of "struct crypto_acomp_ctx" to represent a configurable number of acomp_reqs and the required number of buffers. Accordingly, refactored the code that allocates/deallocates the acomp_ctx resources, so that it can be called to create a regular acomp_ctx with exactly one acomp_req/buffer, for use in the the existing non-batching zswap_store(), as well as to create a separate "batching acomp_ctx" with multiple acomp_reqs/buffers for IAA compress batching. Signed-off-by: Kanchana P Sridhar --- mm/zswap.c | 149 ++++++++++++++++++++++++++++++++++++++--------------- 1 file changed, 107 insertions(+), 42 deletions(-) diff --git a/mm/zswap.c b/mm/zswap.c index 3e899fa61445..02e031122fdf 100644 --- a/mm/zswap.c +++ b/mm/zswap.c @@ -143,9 +143,10 @@ bool zswap_never_enabled(void) =20 struct crypto_acomp_ctx { struct crypto_acomp *acomp; - struct acomp_req *req; + struct acomp_req **reqs; + u8 **buffers; + unsigned int nr_reqs; struct crypto_wait wait; - u8 *buffer; struct mutex mutex; bool is_sleepable; }; @@ -241,6 +242,11 @@ static inline struct xarray *swap_zswap_tree(swp_entry= _t swp) pr_debug("%s pool %s/%s\n", msg, (p)->tfm_name, \ zpool_get_type((p)->zpool)) =20 +static int zswap_create_acomp_ctx(unsigned int cpu, + struct crypto_acomp_ctx *acomp_ctx, + char *tfm_name, + unsigned int nr_reqs); + /********************************* * pool functions **********************************/ @@ -813,69 +819,128 @@ static void zswap_entry_free(struct zswap_entry *ent= ry) /********************************* * compressed storage functions **********************************/ -static int zswap_cpu_comp_prepare(unsigned int cpu, struct hlist_node *nod= e) +static int zswap_create_acomp_ctx(unsigned int cpu, + struct crypto_acomp_ctx *acomp_ctx, + char *tfm_name, + unsigned int nr_reqs) { - struct zswap_pool *pool =3D hlist_entry(node, struct zswap_pool, node); - struct crypto_acomp_ctx *acomp_ctx =3D per_cpu_ptr(pool->acomp_ctx, cpu); struct crypto_acomp *acomp; - struct acomp_req *req; - int ret; + int ret =3D -ENOMEM; + int i, j; =20 + acomp_ctx->nr_reqs =3D 0; mutex_init(&acomp_ctx->mutex); =20 - acomp_ctx->buffer =3D kmalloc_node(PAGE_SIZE * 2, GFP_KERNEL, cpu_to_node= (cpu)); - if (!acomp_ctx->buffer) - return -ENOMEM; - - acomp =3D crypto_alloc_acomp_node(pool->tfm_name, 0, 0, cpu_to_node(cpu)); + acomp =3D crypto_alloc_acomp_node(tfm_name, 0, 0, cpu_to_node(cpu)); if (IS_ERR(acomp)) { pr_err("could not alloc crypto acomp %s : %ld\n", - pool->tfm_name, PTR_ERR(acomp)); - ret =3D PTR_ERR(acomp); - goto acomp_fail; + tfm_name, PTR_ERR(acomp)); + return PTR_ERR(acomp); } + acomp_ctx->acomp =3D acomp; acomp_ctx->is_sleepable =3D acomp_is_async(acomp); =20 - req =3D acomp_request_alloc(acomp_ctx->acomp); - if (!req) { - pr_err("could not alloc crypto acomp_request %s\n", - pool->tfm_name); - ret =3D -ENOMEM; + acomp_ctx->buffers =3D kmalloc_node(nr_reqs * sizeof(u8 *), + GFP_KERNEL, cpu_to_node(cpu)); + if (!acomp_ctx->buffers) + goto buf_fail; + + for (i =3D 0; i < nr_reqs; ++i) { + acomp_ctx->buffers[i] =3D kmalloc_node(PAGE_SIZE * 2, + GFP_KERNEL, cpu_to_node(cpu)); + if (!acomp_ctx->buffers[i]) { + for (j =3D 0; j < i; ++j) + kfree(acomp_ctx->buffers[j]); + kfree(acomp_ctx->buffers); + ret =3D -ENOMEM; + goto buf_fail; + } + } + + acomp_ctx->reqs =3D kmalloc_node(nr_reqs * sizeof(struct acomp_req *), + GFP_KERNEL, cpu_to_node(cpu)); + if (!acomp_ctx->reqs) goto req_fail; + + for (i =3D 0; i < nr_reqs; ++i) { + acomp_ctx->reqs[i] =3D acomp_request_alloc(acomp_ctx->acomp); + if (!acomp_ctx->reqs[i]) { + pr_err("could not alloc crypto acomp_request reqs[%d] %s\n", + i, tfm_name); + for (j =3D 0; j < i; ++j) + acomp_request_free(acomp_ctx->reqs[j]); + kfree(acomp_ctx->reqs); + ret =3D -ENOMEM; + goto req_fail; + } } - acomp_ctx->req =3D req; =20 + /* + * The crypto_wait is used only in fully synchronous, i.e., with scomp + * or non-poll mode of acomp, hence there is only one "wait" per + * acomp_ctx, with callback set to reqs[0], under the assumption that + * there is at least 1 request per acomp_ctx. + */ crypto_init_wait(&acomp_ctx->wait); /* * if the backend of acomp is async zip, crypto_req_done() will wakeup * crypto_wait_req(); if the backend of acomp is scomp, the callback * won't be called, crypto_wait_req() will return without blocking. */ - acomp_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG, + acomp_request_set_callback(acomp_ctx->reqs[0], CRYPTO_TFM_REQ_MAY_BACKLOG, crypto_req_done, &acomp_ctx->wait); =20 + acomp_ctx->nr_reqs =3D nr_reqs; return 0; =20 req_fail: + for (i =3D 0; i < nr_reqs; ++i) + kfree(acomp_ctx->buffers[i]); + kfree(acomp_ctx->buffers); +buf_fail: crypto_free_acomp(acomp_ctx->acomp); -acomp_fail: - kfree(acomp_ctx->buffer); return ret; } =20 -static int zswap_cpu_comp_dead(unsigned int cpu, struct hlist_node *node) +static void zswap_delete_acomp_ctx(struct crypto_acomp_ctx *acomp_ctx) { - struct zswap_pool *pool =3D hlist_entry(node, struct zswap_pool, node); - struct crypto_acomp_ctx *acomp_ctx =3D per_cpu_ptr(pool->acomp_ctx, cpu); - if (!IS_ERR_OR_NULL(acomp_ctx)) { - if (!IS_ERR_OR_NULL(acomp_ctx->req)) - acomp_request_free(acomp_ctx->req); + int i; + + for (i =3D 0; i < acomp_ctx->nr_reqs; ++i) + if (!IS_ERR_OR_NULL(acomp_ctx->reqs[i])) + acomp_request_free(acomp_ctx->reqs[i]); + kfree(acomp_ctx->reqs); + + for (i =3D 0; i < acomp_ctx->nr_reqs; ++i) + kfree(acomp_ctx->buffers[i]); + kfree(acomp_ctx->buffers); + if (!IS_ERR_OR_NULL(acomp_ctx->acomp)) crypto_free_acomp(acomp_ctx->acomp); - kfree(acomp_ctx->buffer); + + acomp_ctx->nr_reqs =3D 0; + acomp_ctx =3D NULL; } +} + +static int zswap_cpu_comp_prepare(unsigned int cpu, struct hlist_node *nod= e) +{ + struct zswap_pool *pool =3D hlist_entry(node, struct zswap_pool, node); + struct crypto_acomp_ctx *acomp_ctx; + + acomp_ctx =3D per_cpu_ptr(pool->acomp_ctx, cpu); + return zswap_create_acomp_ctx(cpu, acomp_ctx, pool->tfm_name, 1); +} + +static int zswap_cpu_comp_dead(unsigned int cpu, struct hlist_node *node) +{ + struct zswap_pool *pool =3D hlist_entry(node, struct zswap_pool, node); + struct crypto_acomp_ctx *acomp_ctx; + + acomp_ctx =3D per_cpu_ptr(pool->acomp_ctx, cpu); + zswap_delete_acomp_ctx(acomp_ctx); =20 return 0; } @@ -898,7 +963,7 @@ static bool zswap_compress(struct page *page, struct zs= wap_entry *entry, =20 acomp_ctx =3D raw_cpu_ptr(pool->acomp_ctx); =20 - dst =3D acomp_ctx->buffer; + dst =3D acomp_ctx->buffers[0]; sg_init_table(&input, 1); sg_set_page(&input, page, PAGE_SIZE, 0); =20 @@ -908,7 +973,7 @@ static bool zswap_compress(struct page *page, struct zs= wap_entry *entry, * giving the dst buffer with enough length to avoid buffer overflow. */ sg_init_one(&output, dst, PAGE_SIZE * 2); - acomp_request_set_params(acomp_ctx->req, &input, &output, PAGE_SIZE, dlen= ); + acomp_request_set_params(acomp_ctx->reqs[0], &input, &output, PAGE_SIZE, = dlen); =20 /* * it maybe looks a little bit silly that we send an asynchronous request, @@ -922,8 +987,8 @@ static bool zswap_compress(struct page *page, struct zs= wap_entry *entry, * but in different threads running on different cpu, we have different * acomp instance, so multiple threads can do (de)compression in parallel. */ - comp_ret =3D crypto_wait_req(crypto_acomp_compress(acomp_ctx->req), &acom= p_ctx->wait); - dlen =3D acomp_ctx->req->dlen; + comp_ret =3D crypto_wait_req(crypto_acomp_compress(acomp_ctx->reqs[0]), &= acomp_ctx->wait); + dlen =3D acomp_ctx->reqs[0]->dlen; if (comp_ret) goto unlock; =20 @@ -975,24 +1040,24 @@ static void zswap_decompress(struct zswap_entry *ent= ry, struct folio *folio) */ if ((acomp_ctx->is_sleepable && !zpool_can_sleep_mapped(zpool)) || !virt_addr_valid(src)) { - memcpy(acomp_ctx->buffer, src, entry->length); - src =3D acomp_ctx->buffer; + memcpy(acomp_ctx->buffers[0], src, entry->length); + src =3D acomp_ctx->buffers[0]; zpool_unmap_handle(zpool, entry->handle); } =20 sg_init_one(&input, src, entry->length); sg_init_table(&output, 1); sg_set_folio(&output, folio, PAGE_SIZE, 0); - acomp_request_set_params(acomp_ctx->req, &input, &output, entry->length, = PAGE_SIZE); - BUG_ON(crypto_wait_req(crypto_acomp_decompress(acomp_ctx->req), &acomp_ct= x->wait)); - BUG_ON(acomp_ctx->req->dlen !=3D PAGE_SIZE); + acomp_request_set_params(acomp_ctx->reqs[0], &input, &output, entry->leng= th, PAGE_SIZE); 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06 Nov 2024 11:21:13 -0800 X-CSE-ConnectionGUID: 6oXbOKZDRWiqdJfoYia+Yg== X-CSE-MsgGUID: 7yNp1XuCTqGZv0eIhDj5ZQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,263,1725346800"; d="scan'208";a="88695410" Received: from unknown (HELO JF5300-B11A338T.jf.intel.com) ([10.242.51.115]) by fmviesa003.fm.intel.com with ESMTP; 06 Nov 2024 11:21:12 -0800 From: Kanchana P Sridhar To: linux-kernel@vger.kernel.org, linux-mm@kvack.org, hannes@cmpxchg.org, yosryahmed@google.com, nphamcs@gmail.com, chengming.zhou@linux.dev, usamaarif642@gmail.com, ryan.roberts@arm.com, ying.huang@intel.com, 21cnbao@gmail.com, akpm@linux-foundation.org, linux-crypto@vger.kernel.org, herbert@gondor.apana.org.au, davem@davemloft.net, clabbe@baylibre.com, ardb@kernel.org, ebiggers@google.com, surenb@google.com, kristen.c.accardi@intel.com, zanussi@kernel.org Cc: wajdi.k.feghali@intel.com, vinodh.gopal@intel.com, kanchana.p.sridhar@intel.com Subject: [PATCH v3 10/13] mm: zswap: Add a per-cpu "acomp_batch_ctx" to struct zswap_pool. Date: Wed, 6 Nov 2024 11:21:02 -0800 Message-Id: <20241106192105.6731-11-kanchana.p.sridhar@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20241106192105.6731-1-kanchana.p.sridhar@intel.com> References: <20241106192105.6731-1-kanchana.p.sridhar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch adds a separate per-cpu batching acomp context "acomp_batch_ctx" to the zswap_pool. The per-cpu acomp_batch_ctx pointer is allocated at pool creation time, but no per-cpu resources are allocated for it. The idea is to not incur the memory footprint cost of multiple acomp_reqs and buffers in the existing "acomp_ctx" for cases where compress batching is not possible; for instance, with software compressor algorithms, on systems without IAA, on systems with IAA that want to run the existing non-batching implementation of zswap_store() of large folios. By creating a separate acomp_batch_ctx, we have the ability to allocate additional memory per-cpu only if the zswap compressor supports batching, and if the user wants to enable the use of compress batching in zswap_store() to improve swapout performance of large folios. Suggested-by: Yosry Ahmed Signed-off-by: Kanchana P Sridhar --- mm/zswap.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/mm/zswap.c b/mm/zswap.c index 02e031122fdf..80a928cf0f7e 100644 --- a/mm/zswap.c +++ b/mm/zswap.c @@ -160,6 +160,7 @@ struct crypto_acomp_ctx { struct zswap_pool { struct zpool *zpool; struct crypto_acomp_ctx __percpu *acomp_ctx; + struct crypto_acomp_ctx __percpu *acomp_batch_ctx; struct percpu_ref ref; struct list_head list; struct work_struct release_work; @@ -287,10 +288,14 @@ static struct zswap_pool *zswap_pool_create(char *typ= e, char *compressor) =20 pool->acomp_ctx =3D alloc_percpu(*pool->acomp_ctx); if (!pool->acomp_ctx) { - pr_err("percpu alloc failed\n"); + pr_err("percpu acomp_ctx alloc failed\n"); goto error; } =20 + pool->acomp_batch_ctx =3D alloc_percpu(*pool->acomp_batch_ctx); + if (!pool->acomp_batch_ctx) + pr_err("percpu acomp_batch_ctx alloc failed\n"); + ret =3D cpuhp_state_add_instance(CPUHP_MM_ZSWP_POOL_PREPARE, &pool->node); if (ret) @@ -312,6 +317,8 @@ static struct zswap_pool *zswap_pool_create(char *type,= char *compressor) ref_fail: cpuhp_state_remove_instance(CPUHP_MM_ZSWP_POOL_PREPARE, &pool->node); error: + if (pool->acomp_batch_ctx) + free_percpu(pool->acomp_batch_ctx); if (pool->acomp_ctx) free_percpu(pool->acomp_ctx); if (pool->zpool) @@ -368,6 +375,8 @@ static void zswap_pool_destroy(struct zswap_pool *pool) =20 cpuhp_state_remove_instance(CPUHP_MM_ZSWP_POOL_PREPARE, &pool->node); free_percpu(pool->acomp_ctx); + if (pool->acomp_batch_ctx) + free_percpu(pool->acomp_batch_ctx); =20 zpool_destroy_pool(pool->zpool); kfree(pool); @@ -930,6 +939,11 @@ static int zswap_cpu_comp_prepare(unsigned int cpu, st= ruct hlist_node *node) struct zswap_pool *pool =3D hlist_entry(node, struct zswap_pool, node); struct crypto_acomp_ctx *acomp_ctx; =20 + if (pool->acomp_batch_ctx) { + acomp_ctx =3D per_cpu_ptr(pool->acomp_batch_ctx, cpu); + acomp_ctx->nr_reqs =3D 0; + } + acomp_ctx =3D per_cpu_ptr(pool->acomp_ctx, cpu); return zswap_create_acomp_ctx(cpu, acomp_ctx, pool->tfm_name, 1); } @@ -939,6 +953,12 @@ static int zswap_cpu_comp_dead(unsigned int cpu, struc= t hlist_node *node) struct zswap_pool *pool =3D hlist_entry(node, struct zswap_pool, node); struct crypto_acomp_ctx *acomp_ctx; =20 + if (pool->acomp_batch_ctx) { + acomp_ctx =3D per_cpu_ptr(pool->acomp_batch_ctx, cpu); + if (!IS_ERR_OR_NULL(acomp_ctx) && (acomp_ctx->nr_reqs > 0)) + zswap_delete_acomp_ctx(acomp_ctx); + } + acomp_ctx =3D per_cpu_ptr(pool->acomp_ctx, cpu); zswap_delete_acomp_ctx(acomp_ctx); =20 --=20 2.27.0 From nobody Sun Nov 24 07:43:53 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D194220C316; Wed, 6 Nov 2024 19:21:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; 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06 Nov 2024 11:21:14 -0800 X-CSE-ConnectionGUID: ClMLUI8HQiKSghkT7rDUWg== X-CSE-MsgGUID: EuVmJ52UQjmumLK5h0SBhQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,263,1725346800"; d="scan'208";a="88695416" Received: from unknown (HELO JF5300-B11A338T.jf.intel.com) ([10.242.51.115]) by fmviesa003.fm.intel.com with ESMTP; 06 Nov 2024 11:21:13 -0800 From: Kanchana P Sridhar To: linux-kernel@vger.kernel.org, linux-mm@kvack.org, hannes@cmpxchg.org, yosryahmed@google.com, nphamcs@gmail.com, chengming.zhou@linux.dev, usamaarif642@gmail.com, ryan.roberts@arm.com, ying.huang@intel.com, 21cnbao@gmail.com, akpm@linux-foundation.org, linux-crypto@vger.kernel.org, herbert@gondor.apana.org.au, davem@davemloft.net, clabbe@baylibre.com, ardb@kernel.org, ebiggers@google.com, surenb@google.com, kristen.c.accardi@intel.com, zanussi@kernel.org Cc: wajdi.k.feghali@intel.com, vinodh.gopal@intel.com, kanchana.p.sridhar@intel.com Subject: [PATCH v3 11/13] mm: zswap: Allocate acomp_batch_ctx resources for a given zswap_pool. Date: Wed, 6 Nov 2024 11:21:03 -0800 Message-Id: <20241106192105.6731-12-kanchana.p.sridhar@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20241106192105.6731-1-kanchana.p.sridhar@intel.com> References: <20241106192105.6731-1-kanchana.p.sridhar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If the zswap_pool is associated with an acomp_alg/crypto_acomp that has registered batch_compress() and batch_decompress() API, we can allocate the necessary batching resources for the pool's acomp_batch_ctx. This patch makes the above determination on incurring the per-cpu memory footprint cost for batching, and if so, goes ahead and allocates SWAP_CRYPTO_BATCH_SIZE (i.e. 8) acomp_reqs/buffers for the pool->acomp_batch_ctx on that specific cpu. It also "remembers" the pool's batching readiness as a result of the above, through a new enum batch_comp_status can_batch_comp; member added to struct zswap_pool, for fast retrieval during zswap_store(). This allows us a way to only incur the memory footprint cost of the pool->acomp_batch_ctx resources for a given cpu on which zswap_store() needs to process a large folio. Suggested-by: Yosry Ahmed Suggested-by: Ying Huang Signed-off-by: Kanchana P Sridhar --- include/linux/zswap.h | 7 ++++++ mm/zswap.c | 52 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) diff --git a/include/linux/zswap.h b/include/linux/zswap.h index d961ead91bf1..9ad27ab3d222 100644 --- a/include/linux/zswap.h +++ b/include/linux/zswap.h @@ -7,6 +7,13 @@ =20 struct lruvec; =20 +/* + * For IAA compression batching: + * Maximum number of IAA acomp compress requests that will be processed + * in a batch: in parallel, if iaa_crypto async/no irq mode is enabled + * (the default); else sequentially, if iaa_crypto sync mode is in effect. + */ +#define SWAP_CRYPTO_BATCH_SIZE 8UL extern atomic_long_t zswap_stored_pages; =20 #ifdef CONFIG_ZSWAP diff --git a/mm/zswap.c b/mm/zswap.c index 80a928cf0f7e..2af736e38213 100644 --- a/mm/zswap.c +++ b/mm/zswap.c @@ -151,6 +151,12 @@ struct crypto_acomp_ctx { bool is_sleepable; }; =20 +enum batch_comp_status { + UNINIT_BATCH_COMP =3D -1, + CANNOT_BATCH_COMP =3D 0, + BATCH_COMP_ENABLED =3D 1, +}; + /* * The lock ordering is zswap_tree.lock -> zswap_pool.lru_lock. * The only case where lru_lock is not acquired while holding tree.lock is @@ -159,6 +165,7 @@ struct crypto_acomp_ctx { */ struct zswap_pool { struct zpool *zpool; + enum batch_comp_status can_batch_comp; struct crypto_acomp_ctx __percpu *acomp_ctx; struct crypto_acomp_ctx __percpu *acomp_batch_ctx; struct percpu_ref ref; @@ -310,6 +317,7 @@ static struct zswap_pool *zswap_pool_create(char *type,= char *compressor) goto ref_fail; INIT_LIST_HEAD(&pool->list); =20 + pool->can_batch_comp =3D UNINIT_BATCH_COMP; zswap_pool_debug("created", pool); =20 return pool; @@ -695,6 +703,39 @@ static int zswap_enabled_param_set(const char *val, return ret; } =20 +/* Called only if sysctl vm.compress-batching is set to "1". */ +static __always_inline bool zswap_pool_can_batch(struct zswap_pool *pool) +{ + struct crypto_acomp_ctx *acomp_ctx; + + if ((pool->can_batch_comp =3D=3D BATCH_COMP_ENABLED) && + !IS_ERR_OR_NULL((acomp_ctx =3D raw_cpu_ptr(pool->acomp_batch_ctx))) && + (acomp_ctx->nr_reqs =3D=3D SWAP_CRYPTO_BATCH_SIZE)) + return true; + + if (pool->can_batch_comp =3D=3D CANNOT_BATCH_COMP) + return false; + + if ((pool->can_batch_comp =3D=3D UNINIT_BATCH_COMP) && pool->acomp_batch_= ctx) { + acomp_ctx =3D raw_cpu_ptr(pool->acomp_batch_ctx); + + if (!IS_ERR_OR_NULL(acomp_ctx)) { + if ((acomp_ctx->nr_reqs =3D=3D SWAP_CRYPTO_BATCH_SIZE) || + (!acomp_ctx->nr_reqs && + !zswap_create_acomp_ctx(raw_smp_processor_id(), + acomp_ctx, + pool->tfm_name, + SWAP_CRYPTO_BATCH_SIZE))) { + pool->can_batch_comp =3D BATCH_COMP_ENABLED; + return true; + } + } + } + + pool->can_batch_comp =3D CANNOT_BATCH_COMP; + return false; +} + /********************************* * lru functions **********************************/ @@ -850,6 +891,17 @@ static int zswap_create_acomp_ctx(unsigned int cpu, acomp_ctx->acomp =3D acomp; acomp_ctx->is_sleepable =3D acomp_is_async(acomp); =20 + /* + * Cannot create a batching ctx without the crypto acomp alg supporting + * batch_compress and batch_decompress API. + */ + if ((nr_reqs > 1) && (!acomp->batch_compress || !acomp->batch_decompress)= ) { + WARN_ONCE(1, "Cannot alloc acomp_ctx with %d reqs since crypto acomp %s\= nhas not registered batch_compress() and/or batch_decompress()\n", + nr_reqs, tfm_name); + ret =3D -ENODEV; + goto buf_fail; + } + acomp_ctx->buffers =3D kmalloc_node(nr_reqs * sizeof(u8 *), GFP_KERNEL, cpu_to_node(cpu)); if (!acomp_ctx->buffers) --=20 2.27.0 From nobody Sun Nov 24 07:43:53 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BCFF320C47A; Wed, 6 Nov 2024 19:21:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730920879; cv=none; b=Qleg8629UPTx28DB3M9CrmoYXHwEgO9/n69ec3w04jJxGl0qB3zabi3+tTGuT5EWO3arsnkMnaxk/53BbrhZgfN9FPmhljmpavhKcwoDMvnAViLiM9RQLkXiyd9Fz2Bo69OR6PcrTYr5dyfufjwoWMEFtDV+EVhwUYel09fZSOo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730920879; c=relaxed/simple; bh=RvYO56c7H8o1E9i8DrptIuQN+cu6z6PTo04ljSRvTjY=; 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06 Nov 2024 11:21:13 -0800 From: Kanchana P Sridhar To: linux-kernel@vger.kernel.org, linux-mm@kvack.org, hannes@cmpxchg.org, yosryahmed@google.com, nphamcs@gmail.com, chengming.zhou@linux.dev, usamaarif642@gmail.com, ryan.roberts@arm.com, ying.huang@intel.com, 21cnbao@gmail.com, akpm@linux-foundation.org, linux-crypto@vger.kernel.org, herbert@gondor.apana.org.au, davem@davemloft.net, clabbe@baylibre.com, ardb@kernel.org, ebiggers@google.com, surenb@google.com, kristen.c.accardi@intel.com, zanussi@kernel.org Cc: wajdi.k.feghali@intel.com, vinodh.gopal@intel.com, kanchana.p.sridhar@intel.com Subject: [PATCH v3 12/13] mm: Add sysctl vm.compress-batching switch for compress batching during swapout. Date: Wed, 6 Nov 2024 11:21:04 -0800 Message-Id: <20241106192105.6731-13-kanchana.p.sridhar@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20241106192105.6731-1-kanchana.p.sridhar@intel.com> References: <20241106192105.6731-1-kanchana.p.sridhar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The sysctl vm.compress-batching parameter is 0 by default. If the platform has Intel IAA, the user can run experiments with IAA compress batching of large folios in zswap_store() as follows: sysctl vm.compress-batching=3D1 echo deflate-iaa > /sys/module/zswap/parameters/compressor This is expected to significantly improve zswap_store() latency of swapping out large folios due to parallel compression of 8 pages in the large folio at a time, in hardware. Setting vm.compress-batching to "1" takes effect only if the zswap compression algorithm's crypto_acomp registers implementations for the batch_compress() and batch_decompress() API. In other words, compress batching works only with the iaa_crypto driver, that does register these new batching API. It is a no-op for compressors that do not register the batching API. The sysctl vm.compress-batching acts as a switch because it takes effect upon future zswap_store() calls on any given core. If the switch is "1", large folios will use parallel batched compression of the folio's pages. If the switch is "0", zswap_store() will use sequential compression for storing every page in a large folio. Signed-off-by: Kanchana P Sridhar --- include/linux/mm.h | 2 ++ kernel/sysctl.c | 9 +++++++++ mm/swap.c | 6 ++++++ 3 files changed, 17 insertions(+) diff --git a/include/linux/mm.h b/include/linux/mm.h index fecd47239fa9..f61915aa2f37 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -82,8 +82,10 @@ extern const int page_cluster_max; =20 #ifdef CONFIG_SYSCTL extern int sysctl_legacy_va_layout; +extern unsigned int compress_batching; #else #define sysctl_legacy_va_layout 0 +#define compress_batching 0 #endif =20 #ifdef CONFIG_HAVE_ARCH_MMAP_RND_BITS diff --git a/kernel/sysctl.c b/kernel/sysctl.c index 79e6cb1d5c48..e298857595b4 100644 --- a/kernel/sysctl.c +++ b/kernel/sysctl.c @@ -2064,6 +2064,15 @@ static struct ctl_table vm_table[] =3D { .extra1 =3D SYSCTL_ZERO, .extra2 =3D (void *)&page_cluster_max, }, + { + .procname =3D "compress-batching", + .data =3D &compress_batching, + .maxlen =3D sizeof(unsigned int), + .mode =3D 0644, + .proc_handler =3D proc_douintvec_minmax, + .extra1 =3D SYSCTL_ZERO, + .extra2 =3D SYSCTL_ONE, + }, { .procname =3D "dirtytime_expire_seconds", .data =3D &dirtytime_expire_interval, diff --git a/mm/swap.c b/mm/swap.c index 638a3f001676..bc4c9079769e 100644 --- a/mm/swap.c +++ b/mm/swap.c @@ -47,6 +47,9 @@ int page_cluster; const int page_cluster_max =3D 31; =20 +/* Enable/disable compress batching during swapout. */ +unsigned int compress_batching; + struct cpu_fbatches { /* * The following folio batches are grouped together because they are prot= ected @@ -1074,4 +1077,7 @@ void __init swap_setup(void) * Right now other parts of the system means that we * _really_ don't want to cluster much more */ + + /* Disable compress batching during swapout by default. */ + compress_batching =3D 0; } --=20 2.27.0 From nobody Sun Nov 24 07:43:53 2024 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB44B20C484; Wed, 6 Nov 2024 19:21:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730920880; cv=none; b=CA2aYbmakXcguuAxUot9RvXik8AzkyOfOoOa1yB43WFfVxWPRtMtrgHx0M8bp1msAyv/MSwYd8r+rzIgFlDPiELAhBVg/DbPVjzWMiRqwl7JuoGIgh8Kvlm/jzrUCM4NR2vvZw9t+K8N3uMT0WARSYoKu4DMeYof//B+yDnv/Pw= ARC-Message-Signature: i=1; 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d="scan'208";a="88695434" Received: from unknown (HELO JF5300-B11A338T.jf.intel.com) ([10.242.51.115]) by fmviesa003.fm.intel.com with ESMTP; 06 Nov 2024 11:21:14 -0800 From: Kanchana P Sridhar To: linux-kernel@vger.kernel.org, linux-mm@kvack.org, hannes@cmpxchg.org, yosryahmed@google.com, nphamcs@gmail.com, chengming.zhou@linux.dev, usamaarif642@gmail.com, ryan.roberts@arm.com, ying.huang@intel.com, 21cnbao@gmail.com, akpm@linux-foundation.org, linux-crypto@vger.kernel.org, herbert@gondor.apana.org.au, davem@davemloft.net, clabbe@baylibre.com, ardb@kernel.org, ebiggers@google.com, surenb@google.com, kristen.c.accardi@intel.com, zanussi@kernel.org Cc: wajdi.k.feghali@intel.com, vinodh.gopal@intel.com, kanchana.p.sridhar@intel.com Subject: [PATCH v3 13/13] mm: zswap: Compress batching with Intel IAA in zswap_store() of large folios. Date: Wed, 6 Nov 2024 11:21:05 -0800 Message-Id: <20241106192105.6731-14-kanchana.p.sridhar@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20241106192105.6731-1-kanchana.p.sridhar@intel.com> References: <20241106192105.6731-1-kanchana.p.sridhar@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If the system has Intel IAA, and if sysctl vm.compress-batching is set to "1", zswap_store() will call crypto_acomp_batch_compress() to compress up to SWAP_CRYPTO_BATCH_SIZE (i.e. 8) pages in large folios in parallel using the multiple compress engines available in IAA hardware. On platforms with multiple IAA devices per socket, compress jobs from all cores in a socket will be distributed among all IAA devices on the socket by the iaa_crypto driver. With deflate-iaa configured as the zswap compressor, and sysctl vm.compress-batching is enabled, the first time zswap_store() has to swapout a large folio on any given cpu, it will allocate the pool->acomp_batch_ctx resources on that cpu, and set pool->can_batch_comp to BATCH_COMP_ENABLED. It will then proceed to call the main __zswap_store_batch_core() compress batching function. Subsequent calls to zswap_store() on the same cpu will go ahead and use the acomp_batch_ctx by checking the pool->can_batch_comp status. Hence, we allocate the per-cpu pool->acomp_batch_ctx resources only on an as-needed basis, to reduce memory footprint cost. The cost is not incurred on cores that never get to swapout a large folio. This patch introduces the main __zswap_store_batch_core() function for compress batching. This interface represents the extensible compress batching architecture that can potentially be called with a batch of any-order folios from shrink_folio_list(). In other words, although zswap_store() calls __zswap_store_batch_core() with exactly one large folio in this patch, we can reuse this interface to reclaim a batch of folios, to significantly improve the reclaim path efficiency due to IAA's parallel compression capability. The newly added functions that implement batched stores follow the general structure of zswap_store() of a large folio. Some amount of restructuring and optimization is done to minimize failure points for a batch, fail early and maximize the zswap store pipeline occupancy with SWAP_CRYPTO_BATCH_SIZE pages, potentially from multiple folios. This is intended to maximize reclaim throughput with the IAA hardware parallel compressions. Signed-off-by: Kanchana P Sridhar --- include/linux/zswap.h | 84 ++++++ mm/zswap.c | 625 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 709 insertions(+) diff --git a/include/linux/zswap.h b/include/linux/zswap.h index 9ad27ab3d222..6d3ef4780c69 100644 --- a/include/linux/zswap.h +++ b/include/linux/zswap.h @@ -31,6 +31,88 @@ struct zswap_lruvec_state { atomic_long_t nr_disk_swapins; }; =20 +/* + * struct zswap_store_sub_batch_page: + * + * This represents one "zswap batching element", namely, the + * attributes associated with a page in a large folio that will + * be compressed and stored in zswap. The term "batch" is reserved + * for a conceptual "batch" of folios that can be sent to + * zswap_store() by reclaim. The term "sub-batch" is used to describe + * a collection of "zswap batching elements", i.e., an array of + * "struct zswap_store_sub_batch_page *". + * + * The zswap compress sub-batch size is specified by + * SWAP_CRYPTO_BATCH_SIZE, currently set as 8UL if the + * platform has Intel IAA. This means zswap can store a large folio + * by creating sub-batches of up to 8 pages and compressing this + * batch using IAA to parallelize the 8 compress jobs in hardware. + * For e.g., a 64KB folio can be compressed as 2 sub-batches of + * 8 pages each. This can significantly improve the zswap_store() + * performance for large folios. + * + * Although the page itself is represented directly, the structure + * adds a "u8 batch_idx" to represent an index for the folio in a + * conceptual "batch of folios" that can be passed to zswap_store(). + * Conceptually, this allows for up to 256 folios that can be passed + * to zswap_store(). If this conceptual number of folios sent to + * zswap_store() exceeds 256, the "batch_idx" needs to become u16. + */ +struct zswap_store_sub_batch_page { + u8 batch_idx; + swp_entry_t swpentry; + struct obj_cgroup *objcg; + struct zswap_entry *entry; + int error; /* folio error status. */ +}; + +/* + * struct zswap_store_pipeline_state: + * + * This stores state during IAA compress batching of (conceptually, a batc= h of) + * folios. The term pipelining in this context, refers to breaking down + * the batch of folios being reclaimed into sub-batches of + * SWAP_CRYPTO_BATCH_SIZE pages, batch compressing and storing the + * sub-batch. This concept could be further evolved to use overlap of CPU + * computes with IAA computes. For instance, we could stage the post-compr= ess + * computes for sub-batch "N-1" to happen in parallel with IAA batch + * compression of sub-batch "N". + * + * We begin by developing the concept of compress batching. Pipelining with + * overlap can be future work. + * + * @errors: The errors status for the batch of reclaim folios passed in fr= om + * a higher mm layer such as swap_writepage(). + * @pool: A valid zswap_pool. + * @acomp_ctx: The per-cpu pointer to the crypto_acomp_ctx for the @pool. + * @sub_batch: This is an array that represents the sub-batch of up to + * SWAP_CRYPTO_BATCH_SIZE pages that are being stored + * in zswap. + * @comp_dsts: The destination buffers for crypto_acomp_compress() for each + * page being compressed. + * @comp_dlens: The destination buffers' lengths from crypto_acomp_compres= s() + * obtained after crypto_acomp_poll() returns completion stat= us, + * for each page being compressed. + * @comp_errors: Compression errors for each page being compressed. + * @nr_comp_pages: Total number of pages in @sub_batch. + * + * Note: + * The max sub-batch size is SWAP_CRYPTO_BATCH_SIZE, currently 8UL. + * Hence, if SWAP_CRYPTO_BATCH_SIZE exceeds 256, some of the + * u8 members (except @comp_dsts) need to become u16. + */ +struct zswap_store_pipeline_state { + int *errors; + struct zswap_pool *pool; + struct crypto_acomp_ctx *acomp_ctx; + struct zswap_store_sub_batch_page *sub_batch; + struct page **comp_pages; + u8 **comp_dsts; + unsigned int *comp_dlens; + int *comp_errors; + u8 nr_comp_pages; +}; + unsigned long zswap_total_pages(void); bool zswap_store(struct folio *folio); bool zswap_load(struct folio *folio); @@ -45,6 +127,8 @@ bool zswap_never_enabled(void); #else =20 struct zswap_lruvec_state {}; +struct zswap_store_sub_batch_page {}; +struct zswap_store_pipeline_state {}; =20 static inline bool zswap_store(struct folio *folio) { diff --git a/mm/zswap.c b/mm/zswap.c index 2af736e38213..538aac3fb552 100644 --- a/mm/zswap.c +++ b/mm/zswap.c @@ -255,6 +255,12 @@ static int zswap_create_acomp_ctx(unsigned int cpu, char *tfm_name, unsigned int nr_reqs); =20 +static bool __zswap_store_batch_core( + int node_id, + struct folio **folios, + int *errors, + unsigned int nr_folios); + /********************************* * pool functions **********************************/ @@ -1626,6 +1632,12 @@ static ssize_t zswap_store_page(struct page *page, return -EINVAL; } =20 +/* + * Modified to use the IAA compress batching framework implemented in + * __zswap_store_batch_core() if sysctl vm.compress-batching is 1. + * The batching code is intended to significantly improve folio store + * performance over the sequential code. + */ bool zswap_store(struct folio *folio) { long nr_pages =3D folio_nr_pages(folio); @@ -1638,6 +1650,38 @@ bool zswap_store(struct folio *folio) bool ret =3D false; long index; =20 + /* + * Improve large folio zswap_store() latency with IAA compress batching, + * if this is enabled by setting sysctl vm.compress-batching to "1". + * If enabled, the large folio's pages are compressed in parallel in + * batches of SWAP_CRYPTO_BATCH_SIZE pages. If disabled, every page in + * the large folio is compressed sequentially. + */ + if (folio_test_large(folio) && READ_ONCE(compress_batching)) { + pool =3D zswap_pool_current_get(); + if (!pool) { + pr_err("Cannot setup acomp_batch_ctx for compress batching: no current = pool found\n"); + goto sequential_store; + } + + if (zswap_pool_can_batch(pool)) { + int error =3D -1; + bool store_batch =3D __zswap_store_batch_core( + folio_nid(folio), + &folio, &error, 1); + + if (store_batch) { + zswap_pool_put(pool); + if (!error) + ret =3D true; + return ret; + } + } + zswap_pool_put(pool); + } + +sequential_store: + VM_WARN_ON_ONCE(!folio_test_locked(folio)); VM_WARN_ON_ONCE(!folio_test_swapcache(folio)); =20 @@ -1724,6 +1768,587 @@ bool zswap_store(struct folio *folio) return ret; } =20 +/* + * Note: If SWAP_CRYPTO_BATCH_SIZE exceeds 256, change the + * u8 stack variables in the next several functions, to u16. + */ + +/* + * Propagate the "sbp" error condition to other batch elements belonging to + * the same folio as "sbp". + */ +static __always_inline void zswap_store_propagate_errors( + struct zswap_store_pipeline_state *zst, + u8 error_batch_idx) +{ + u8 i; + + if (zst->errors[error_batch_idx]) + return; + + for (i =3D 0; i < zst->nr_comp_pages; ++i) { + struct zswap_store_sub_batch_page *sbp =3D &zst->sub_batch[i]; + + if (sbp->batch_idx =3D=3D error_batch_idx) { + if (!sbp->error) { + if (sbp->entry) { + if (!IS_ERR_VALUE(sbp->entry->handle)) + zpool_free(zst->pool->zpool, sbp->entry->handle); + + zswap_entry_cache_free(sbp->entry); + sbp->entry =3D NULL; + } + sbp->error =3D -EINVAL; + } + } + } + + /* + * Set zswap status for the folio to "error" + * for use in swap_writepage. + */ + zst->errors[error_batch_idx] =3D -EINVAL; +} + +static __always_inline void zswap_process_comp_errors( + struct zswap_store_pipeline_state *zst) +{ + u8 i; + + for (i =3D 0; i < zst->nr_comp_pages; ++i) { + struct zswap_store_sub_batch_page *sbp =3D &zst->sub_batch[i]; + + if (zst->comp_errors[i]) { + if (zst->comp_errors[i] =3D=3D -ENOSPC) + zswap_reject_compress_poor++; + else + zswap_reject_compress_fail++; + + if (!sbp->error) + zswap_store_propagate_errors(zst, + sbp->batch_idx); + } + } +} + +static void zswap_compress_batch(struct zswap_store_pipeline_state *zst) +{ + /* + * Compress up to SWAP_CRYPTO_BATCH_SIZE pages. + * It is important to note that the zswap pool's per-cpu "acomp_batch_ctx" + * resources are allocated only if the crypto_acomp has registered both, + * crypto_acomp_batch_compress() and crypto_acomp_batch_decompress() API. + * The iaa_crypto driver registers implementations for both these API. + * Hence, if IAA is the zswap compressor and sysctl vm.compress-batching + * is set to "1", the call to crypto_acomp_batch_compress() will + * compresses the pages in parallel, leading to significant performance + * improvements as compared to software compressors. + */ + crypto_acomp_batch_compress( + zst->acomp_ctx->reqs, + &zst->acomp_ctx->wait, + zst->comp_pages, + zst->comp_dsts, + zst->comp_dlens, + zst->comp_errors, + zst->nr_comp_pages); + + /* + * Scan the sub-batch for any compression errors, + * and invalidate pages with errors, along with other + * pages belonging to the same folio as the error pages. + */ + zswap_process_comp_errors(zst); +} + +static void zswap_zpool_store_sub_batch( + struct zswap_store_pipeline_state *zst) +{ + u8 i; + + for (i =3D 0; i < zst->nr_comp_pages; ++i) { + struct zswap_store_sub_batch_page *sbp =3D &zst->sub_batch[i]; + struct zpool *zpool; + unsigned long handle; + char *buf; + gfp_t gfp; + int err; + + /* Skip pages that had compress errors. */ + if (sbp->error) + continue; + + zpool =3D zst->pool->zpool; + gfp =3D __GFP_NORETRY | __GFP_NOWARN | __GFP_KSWAPD_RECLAIM; + if (zpool_malloc_support_movable(zpool)) + gfp |=3D __GFP_HIGHMEM | __GFP_MOVABLE; + err =3D zpool_malloc(zpool, zst->comp_dlens[i], gfp, &handle); + + if (err) { + if (err =3D=3D -ENOSPC) + zswap_reject_compress_poor++; + else + zswap_reject_alloc_fail++; + + /* + * An error should be propagated to other pages of the + * same folio in the sub-batch, and zpool resources for + * those pages (in sub-batch order prior to this zpool + * error) should be de-allocated. + */ + zswap_store_propagate_errors(zst, sbp->batch_idx); + continue; + } + + buf =3D zpool_map_handle(zpool, handle, ZPOOL_MM_WO); + memcpy(buf, zst->comp_dsts[i], zst->comp_dlens[i]); + zpool_unmap_handle(zpool, handle); + + sbp->entry->handle =3D handle; + sbp->entry->length =3D zst->comp_dlens[i]; + } +} + +/* + * Returns true if the entry was successfully + * stored in the xarray, and false otherwise. + */ +static bool zswap_store_entry(swp_entry_t page_swpentry, + struct zswap_entry *entry) +{ + struct zswap_entry *old =3D xa_store(swap_zswap_tree(page_swpentry), + swp_offset(page_swpentry), + entry, GFP_KERNEL); + if (xa_is_err(old)) { + int err =3D xa_err(old); + + WARN_ONCE(err !=3D -ENOMEM, "unexpected xarray error: %d\n", err); + zswap_reject_alloc_fail++; + return false; + } + + /* + * We may have had an existing entry that became stale when + * the folio was redirtied and now the new version is being + * swapped out. Get rid of the old. + */ + if (old) + zswap_entry_free(old); + + return true; +} + +static void zswap_batch_compress_post_proc( + struct zswap_store_pipeline_state *zst) +{ + int nr_objcg_pages =3D 0, nr_pages =3D 0; + struct obj_cgroup *objcg =3D NULL; + size_t compressed_bytes =3D 0; + u8 i; + + zswap_zpool_store_sub_batch(zst); + + for (i =3D 0; i < zst->nr_comp_pages; ++i) { + struct zswap_store_sub_batch_page *sbp =3D &zst->sub_batch[i]; + + if (sbp->error) + continue; + + if (!zswap_store_entry(sbp->swpentry, sbp->entry)) { + zswap_store_propagate_errors(zst, sbp->batch_idx); + continue; + } + + /* + * The entry is successfully compressed and stored in the tree, + * there is no further possibility of failure. Grab refs to the + * pool and objcg. These refs will be dropped by + * zswap_entry_free() when the entry is removed from the tree. + */ + zswap_pool_get(zst->pool); + if (sbp->objcg) + obj_cgroup_get(sbp->objcg); + + /* + * We finish initializing the entry while it's already in xarray. + * This is safe because: + * + * 1. Concurrent stores and invalidations are excluded by folio + * lock. + * + * 2. Writeback is excluded by the entry not being on the LRU yet. + * The publishing order matters to prevent writeback from seeing + * an incoherent entry. + */ + sbp->entry->pool =3D zst->pool; + sbp->entry->swpentry =3D sbp->swpentry; + sbp->entry->objcg =3D sbp->objcg; + sbp->entry->referenced =3D true; + if (sbp->entry->length) { + INIT_LIST_HEAD(&sbp->entry->lru); + zswap_lru_add(&zswap_list_lru, sbp->entry); + } + + if (!objcg && sbp->objcg) { + objcg =3D sbp->objcg; + } else if (objcg && sbp->objcg && (objcg !=3D sbp->objcg)) { + obj_cgroup_charge_zswap(objcg, compressed_bytes); + count_objcg_events(objcg, ZSWPOUT, nr_objcg_pages); + compressed_bytes =3D 0; + nr_objcg_pages =3D 0; + objcg =3D sbp->objcg; + } + + if (sbp->objcg) { + compressed_bytes +=3D sbp->entry->length; + ++nr_objcg_pages; + } + + ++nr_pages; + } /* for sub-batch pages. */ + + if (objcg) { + obj_cgroup_charge_zswap(objcg, compressed_bytes); + count_objcg_events(objcg, ZSWPOUT, nr_objcg_pages); + } + + atomic_long_add(nr_pages, &zswap_stored_pages); + count_vm_events(ZSWPOUT, nr_pages); +} + +static void zswap_store_sub_batch(struct zswap_store_pipeline_state *zst) +{ + u8 i; + + for (i =3D 0; i < zst->nr_comp_pages; ++i) { + zst->comp_dsts[i] =3D zst->acomp_ctx->buffers[i]; + zst->comp_dlens[i] =3D PAGE_SIZE; + } /* for sub-batch pages. */ + + /* + * Batch compress sub-batch "N". If IAA is the compressor, the + * hardware will compress multiple pages in parallel. + */ + zswap_compress_batch(zst); + + zswap_batch_compress_post_proc(zst); +} + +static void zswap_add_folio_pages_to_sb( + struct zswap_store_pipeline_state *zst, + struct folio* folio, + u8 batch_idx, + struct obj_cgroup *objcg, + struct zswap_entry *entries[], + long start_idx, + u8 add_nr_pages) +{ + long index; + + for (index =3D start_idx; index < (start_idx + add_nr_pages); ++index) { + u8 i =3D zst->nr_comp_pages; + struct zswap_store_sub_batch_page *sbp =3D &zst->sub_batch[i]; + struct page *page =3D folio_page(folio, index); + zst->comp_pages[i] =3D page; + sbp->swpentry =3D page_swap_entry(page); + sbp->batch_idx =3D batch_idx; + sbp->objcg =3D objcg; + sbp->entry =3D entries[index - start_idx]; + sbp->error =3D 0; + ++zst->nr_comp_pages; + } +} + +static __always_inline void zswap_store_reset_sub_batch( + struct zswap_store_pipeline_state *zst) +{ + zst->nr_comp_pages =3D 0; +} + +/* Allocate entries for the next sub-batch. */ +static int zswap_alloc_entries(u8 nr_entries, + struct zswap_entry *entries[], + int node_id) +{ + u8 i; + + for (i =3D 0; i < nr_entries; ++i) { + entries[i] =3D zswap_entry_cache_alloc(GFP_KERNEL, node_id); + if (!entries[i]) { + u8 j; + + zswap_reject_kmemcache_fail++; + for (j =3D 0; j < i; ++j) + zswap_entry_cache_free(entries[j]); + return -EINVAL; + } + + entries[i]->handle =3D (unsigned long)ERR_PTR(-EINVAL); + } + + return 0; +} + +/* + * If the zswap store fails or zswap is disabled, we must invalidate + * the possibly stale entries which were previously stored at the + * offsets corresponding to each page of the folio. Otherwise, + * writeback could overwrite the new data in the swapfile. + */ +static void zswap_delete_stored_entries(struct folio *folio) +{ + swp_entry_t swp =3D folio->swap; + unsigned type =3D swp_type(swp); + pgoff_t offset =3D swp_offset(swp); + struct zswap_entry *entry; + struct xarray *tree; + long index; + + for (index =3D 0; index < folio_nr_pages(folio); ++index) { + tree =3D swap_zswap_tree(swp_entry(type, offset + index)); + entry =3D xa_erase(tree, offset + index); + if (entry) + zswap_entry_free(entry); + } +} + +static void zswap_store_process_folio_errors( + struct folio **folios, + int *errors, + unsigned int nr_folios) +{ + u8 batch_idx; + + for (batch_idx =3D 0; batch_idx < nr_folios; ++batch_idx) + if (errors[batch_idx]) + zswap_delete_stored_entries(folios[batch_idx]); +} + +/* + * Store a (batch of) any-order large folio(s) in zswap. Each folio will be + * broken into sub-batches of SWAP_CRYPTO_BATCH_SIZE pages, the + * sub-batch will be compressed by IAA in parallel, and stored in zpool/xa= rray. + * + * This the main procedure for batching of folios, and batching within + * large folios. + * + * This procedure should only be called if zswap supports batching of stor= es. + * Otherwise, the sequential implementation for storing folios as in the + * current zswap_store() should be used. + * + * The signature of this procedure is meant to allow the calling function, + * (for instance, swap_writepage()) to pass an array @folios + * (the "reclaim batch") of @nr_folios folios to be stored in zswap. + * All folios in the batch must have the same swap type and folio_nid @nod= e_id + * (simplifying assumptions only to manage code complexity). + * + * @errors and @folios have @nr_folios number of entries, with one-one + * correspondence (@errors[i] represents the error status of @folios[i], + * for i in @nr_folios). + * The calling function (for instance, swap_writepage()) should initialize + * @errors[i] to a non-0 value. + * If zswap successfully stores @folios[i], it will set @errors[i] to 0. + * If there is an error in zswap, it will set @errors[i] to -EINVAL. + */ +static bool __zswap_store_batch_core( + int node_id, + struct folio **folios, + int *errors, + unsigned int nr_folios) +{ + struct zswap_store_sub_batch_page sub_batch[SWAP_CRYPTO_BATCH_SIZE]; + struct page *comp_pages[SWAP_CRYPTO_BATCH_SIZE]; + u8 *comp_dsts[SWAP_CRYPTO_BATCH_SIZE] =3D { NULL }; + unsigned int comp_dlens[SWAP_CRYPTO_BATCH_SIZE]; + int comp_errors[SWAP_CRYPTO_BATCH_SIZE]; + struct crypto_acomp_ctx *acomp_ctx, *acomp_batch_ctx; + struct zswap_pool *pool; + /* + * For now, lets say a max of 256 large folios can be reclaimed + * at a time, as a batch. If this exceeds 256, change this to u16. + */ + u8 batch_idx; + + /* Initialize the compress batching pipeline state. */ + struct zswap_store_pipeline_state zst =3D { + .errors =3D errors, + .pool =3D NULL, + .acomp_ctx =3D NULL, + .sub_batch =3D sub_batch, + .comp_pages =3D comp_pages, + .comp_dsts =3D comp_dsts, + .comp_dlens =3D comp_dlens, + .comp_errors =3D comp_errors, + .nr_comp_pages =3D 0, + }; + + pool =3D zswap_pool_current_get(); + if (!pool) { + if (zswap_check_limits()) + queue_work(shrink_wq, &zswap_shrink_work); + goto check_old; + } + + /* + * Caller should make sure that __zswap_store_batch_core() is + * invoked only if sysctl vm.compress-batching is set to "1". + * + * Verify if we are still on the same cpu for which batching + * resources in acomp_batch_ctx were allocated in zswap_store(). + * If not, return to zswap_store() for sequential store of the folio. + */ + acomp_ctx =3D raw_cpu_ptr(pool->acomp_ctx); + mutex_lock(&acomp_ctx->mutex); + + acomp_batch_ctx =3D raw_cpu_ptr(pool->acomp_batch_ctx); + if (!acomp_batch_ctx || !acomp_batch_ctx->nr_reqs) { + mutex_unlock(&acomp_ctx->mutex); + zswap_pool_put(pool); + return false; + } + + mutex_lock(&acomp_batch_ctx->mutex); + mutex_unlock(&acomp_ctx->mutex); + + zst.pool =3D pool; + zst.acomp_ctx =3D acomp_batch_ctx; + + /* + * Iterate over the folios passed in. Construct sub-batches of up to + * SWAP_CRYPTO_BATCH_SIZE pages, if necessary, by iterating through + * multiple folios from the input "folios". Process each sub-batch + * with IAA batch compression. Detect errors from batch compression + * and set the impacted folio's error status (this happens in + * zswap_store_process_errors()). + */ + for (batch_idx =3D 0; batch_idx < nr_folios; ++batch_idx) { + struct folio *folio =3D folios[batch_idx]; + BUG_ON(!folio); + long folio_start_idx, nr_pages =3D folio_nr_pages(folio); + struct zswap_entry *entries[SWAP_CRYPTO_BATCH_SIZE]; + struct obj_cgroup *objcg =3D NULL; + struct mem_cgroup *memcg =3D NULL; + + VM_WARN_ON_ONCE(!folio_test_locked(folio)); + VM_WARN_ON_ONCE(!folio_test_swapcache(folio)); + + /* + * If zswap is disabled, we must invalidate the possibly stale entry + * which was previously stored at this offset. Otherwise, writeback + * could overwrite the new data in the swapfile. + */ + if (!zswap_enabled) + continue; + + /* Check cgroup limits */ + objcg =3D get_obj_cgroup_from_folio(folio); + if (objcg && !obj_cgroup_may_zswap(objcg)) { + memcg =3D get_mem_cgroup_from_objcg(objcg); + if (shrink_memcg(memcg)) { + mem_cgroup_put(memcg); + goto put_objcg; + } + mem_cgroup_put(memcg); + } + + if (zswap_check_limits()) + goto put_objcg; + + if (objcg) { + memcg =3D get_mem_cgroup_from_objcg(objcg); + if (memcg_list_lru_alloc(memcg, &zswap_list_lru, GFP_KERNEL)) { + mem_cgroup_put(memcg); + goto put_objcg; + } + mem_cgroup_put(memcg); + } + + /* + * By default, set zswap status to "success" for use in + * swap_writepage() when this returns. In case of errors, + * a negative error number will over-write this when + * zswap_store_process_errors() is called. + */ + errors[batch_idx] =3D 0; + + folio_start_idx =3D 0; + + while (nr_pages > 0) { + u8 add_nr_pages; + + /* + * If we have accumulated SWAP_CRYPTO_BATCH_SIZE + * pages, process the sub-batch: it could contain pages + * from multiple folios. + */ + if (zst.nr_comp_pages =3D=3D SWAP_CRYPTO_BATCH_SIZE) { + zswap_store_sub_batch(&zst); + zswap_store_reset_sub_batch(&zst); + /* + * Stop processing this folio if it had + * compress errors. + */ + if (errors[batch_idx]) + goto put_objcg; + } + + add_nr_pages =3D min3(( + (long)SWAP_CRYPTO_BATCH_SIZE - + (long)zst.nr_comp_pages), + nr_pages, + (long)SWAP_CRYPTO_BATCH_SIZE); + + /* + * Allocate zswap_entries for this sub-batch. If we + * get errors while doing so, we can flag an error + * for the folio, call the shrinker and move on. + */ + if (zswap_alloc_entries(add_nr_pages, + entries, node_id)) { + zswap_store_reset_sub_batch(&zst); + errors[batch_idx] =3D -EINVAL; + goto put_objcg; + } + + zswap_add_folio_pages_to_sb( + &zst, + folio, + batch_idx, + objcg, + entries, + folio_start_idx, + add_nr_pages); + + nr_pages -=3D add_nr_pages; + folio_start_idx +=3D add_nr_pages; + } /* this folio has pages to be compressed. */ + + obj_cgroup_put(objcg); + continue; + +put_objcg: + obj_cgroup_put(objcg); + if (zswap_pool_reached_full) + queue_work(shrink_wq, &zswap_shrink_work); + } /* for batch folios */ + + if (!zswap_enabled) + goto check_old; + + /* + * Process last sub-batch: it could contain pages from + * multiple folios. + */ + if (zst.nr_comp_pages) + zswap_store_sub_batch(&zst); + + mutex_unlock(&acomp_batch_ctx->mutex); + zswap_pool_put(pool); +check_old: + zswap_store_process_folio_errors(folios, errors, nr_folios); + return true; +} + bool zswap_load(struct folio *folio) { swp_entry_t swp =3D folio->swap; --=20 2.27.0