From nobody Sun Nov 24 08:38:38 2024 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1BCC1E3786; Wed, 6 Nov 2024 12:38:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730896692; cv=none; b=VPOpyNMjfWBKhi6N/gIaZ7Sn/5mKDTGPGvpTj0eiCQaAX93hWVuMCw3rX8SmPhLLiJvKPCCfvJZviRfmarmEqYOYsba2DKxlrfWuDCzQoLXjE7RwVQUVUcxlOhwzWpqFhLMo0ao5RXzKhjQLKJv32Xah/IQglrgaxf0CDt7xw6U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730896692; c=relaxed/simple; bh=eanpZhSG9dWUmjWfMe7zVrerkItvUw0VQ0neWEkUkUk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NLg4L7HQphcyfYSKM+OhPVsZE2udXuBbt42bodpZ2UyiKKnc8bN1IPhD9IE+ysNl8TCDJ9Ng4YjtGycyKa4sOp1e7TWGL4Lft5F5lljj8YvqqQwE5lAgJ26JPRPf2JAF6v954NMcU7PHG2tnJZmC/qt2lhor72rRIxTKIWwyUck= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=0XvfO7h+; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="0XvfO7h+" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=JPM/CaXFyY/a4sEGw6rIBS5Qu/8VC3MAZ527UKrKvBE=; b=0XvfO7h+50cRfYq5ugr8nVZedy pIwW6k5wH1Vnc4pCdF9kLUUTZ8MTVKLCFxscstV04UZJDLe9ZJInOxn1JwLY3GbUk8gfMchWlUSvE HVJXfgA65vKX2++sthIS4QK6JPIsegsLM7TdAauX4irbk/rpPutUfzto1gS6B1xvopk3ChMurcjfl vOF5o0tEs5VGWjkfzQxmWRsuqXfeQe8UapKLb/kOiP7naj7KdMg5k0DdFpNIOTGGxL6t8+TkcQJLJ 7f7a1akkSDqqRwVLG6U7WWoAZj4D7RieONfMmq1S407nchi9veuMjbMtcnDUFAkkuVTUCEPZi55hc ZqoM/C2Q==; Received: from i53875b28.versanet.de ([83.135.91.40] helo=localhost.localdomain) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1t8fIV-0007A8-TR; Wed, 06 Nov 2024 13:38:07 +0100 From: Heiko Stuebner To: heiko@sntech.de Cc: quentin.schulz@cherry.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Heiko Stuebner Subject: [PATCH 1/3] arm64: dts: rockchip: add mipi dcphy nodes to rk3588 Date: Wed, 6 Nov 2024 13:37:56 +0100 Message-ID: <20241106123758.423584-2-heiko@sntech.de> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241106123758.423584-1-heiko@sntech.de> References: <20241106123758.423584-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Heiko Stuebner Add the two MIPI-DC-phy nodes to the RK3588, that will be used by the DSI2 controllers and hopefully in some future also for camera input. Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk3588-base.dtsi index 51ba7563f7d0..8c95c56e8097 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -576,6 +576,16 @@ sys_grf: syscon@fd58c000 { reg =3D <0x0 0xfd58c000 0x0 0x1000>; }; =20 + mipidcphy0_grf: syscon@fd5e8000 { + compatible =3D "rockchip,rk3588-dcphy-grf", "syscon"; + reg =3D <0x0 0xfd5e8000 0x0 0x4000>; + }; + + mipidcphy1_grf: syscon@fd5ec000 { + compatible =3D "rockchip,rk3588-dcphy-grf", "syscon"; + reg =3D <0x0 0xfd5ec000 0x0 0x4000>; + }; + vop_grf: syscon@fd5a4000 { compatible =3D "rockchip,rk3588-vop-grf", "syscon"; reg =3D <0x0 0xfd5a4000 0x0 0x2000>; @@ -2878,6 +2888,38 @@ usbdp_phy0: phy@fed80000 { status =3D "disabled"; }; =20 + mipidcphy0: phy@feda0000 { + compatible =3D "rockchip,rk3588-mipi-dcphy"; + reg =3D <0x0 0xfeda0000 0x0 0x10000>; + rockchip,grf =3D <&mipidcphy0_grf>; + clocks =3D <&cru PCLK_MIPI_DCPHY0>, + <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>; + clock-names =3D "pclk", "ref"; + resets =3D <&cru SRST_M_MIPI_DCPHY0>, + <&cru SRST_P_MIPI_DCPHY0>, + <&cru SRST_P_MIPI_DCPHY0_GRF>, + <&cru SRST_S_MIPI_DCPHY0>; + reset-names =3D "m_phy", "apb", "grf", "s_phy"; + #phy-cells =3D <0>; + status =3D "disabled"; + }; + + mipidcphy1: phy@fedb0000 { + compatible =3D "rockchip,rk3588-mipi-dcphy"; + reg =3D <0x0 0xfedb0000 0x0 0x10000>; + rockchip,grf =3D <&mipidcphy1_grf>; + clocks =3D <&cru PCLK_MIPI_DCPHY1>, + <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>; + clock-names =3D "pclk", "ref"; + resets =3D <&cru SRST_M_MIPI_DCPHY1>, + <&cru SRST_P_MIPI_DCPHY1>, + <&cru SRST_P_MIPI_DCPHY1_GRF>, + <&cru SRST_S_MIPI_DCPHY1>; + reset-names =3D "m_phy", "apb", "grf", "s_phy"; + #phy-cells =3D <0>; + status =3D "disabled"; + }; + combphy0_ps: phy@fee00000 { compatible =3D "rockchip,rk3588-naneng-combphy"; reg =3D <0x0 0xfee00000 0x0 0x100>; --=20 2.45.2 From nobody Sun Nov 24 08:38:38 2024 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2810C1F8F13; Wed, 6 Nov 2024 12:38:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730896691; cv=none; b=EcxhQfHTJquAD9t8uWaaV/nHNz0gx3aZ++A9P58E1ZP2FoKm38Pa5b5ilPfHfGW9C7jHwsXZYXwgfpZQYSQ3n7VcUNivY0EOEI7T8M6KixV4VmcD7RmZbZL4rziTVlJD/ZovCUiMcVpeq3+VomvDB5BlY5Yc7L3vklnm5LmCs3c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730896691; c=relaxed/simple; bh=zhWvmrEiopHjJe+O7D5Vx0z+Lx0rjErsDW9o4V/CGJA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NoEHkgnrjI6Q/vWn2VskMz24JJO3oRAIGP8e0+j9s2KONnJbmlQyrMG4Mojyg0lUDjfoh9S+PQqklrQw5UF8AqIYehoNQxazjzlPNI2sJ30x2QKjzz896P4rwaaAu52j7bsG3xwMLGV5MrKRc96PFS7loOs8FRWW1PCvy2Jj6Ck= ARC-Authentication-Results: i=1; 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charset="utf-8" From: Heiko Stuebner The RK3588 comes with two DSI2 controllers based on a new Synopsis IP. Add the necessary nodes for them. Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk3588-base.dtsi index 8c95c56e8097..6d31de2a6930 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1414,6 +1414,62 @@ i2s9_8ch: i2s@fddfc000 { status =3D "disabled"; }; =20 + dsi0: dsi@fde20000 { + compatible =3D "rockchip,rk3588-mipi-dsi2"; + reg =3D <0x0 0xfde20000 0x0 0x10000>; + interrupts =3D ; + clocks =3D <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>; + clock-names =3D "pclk", "sys"; + resets =3D <&cru SRST_P_DSIHOST0>; + reset-names =3D "apb"; + power-domains =3D <&power RK3588_PD_VOP>; + phys =3D <&mipidcphy0>; + phy-names =3D "dcphy"; + rockchip,grf =3D <&vop_grf>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + dsi0_in: port@0 { + reg =3D <0>; + }; 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Received: from i53875b28.versanet.de ([83.135.91.40] helo=localhost.localdomain) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1t8fIW-0007A8-Ko; Wed, 06 Nov 2024 13:38:08 +0100 From: Heiko Stuebner To: heiko@sntech.de Cc: quentin.schulz@cherry.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Heiko Stuebner Subject: [PATCH 3/3] arm64: dts: rockchip: add overlay for tiger-haikou video-demo adapter Date: Wed, 6 Nov 2024 13:37:58 +0100 Message-ID: <20241106123758.423584-4-heiko@sntech.de> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241106123758.423584-1-heiko@sntech.de> References: <20241106123758.423584-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Heiko Stuebner This adds support for the video-demo-adapter for the Haikou devkit with Tiger RK3588 SoM. The Video Demo adapter is an adapter connected to the fake PCIe slot labeled "Video Connector" on the Haikou devkit. It's main feature is a Leadtek DSI-display with touchscreen. To drive these components a number of additional regulators are grouped on the adapter as well as a PCA9670 gpio-expander to provide the needed additional gpio-lines. Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../rk3588-tiger-haikou-video-demo.dtso | 153 ++++++++++++++++++ 2 files changed, 154 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou-video-= demo.dtso diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 09423070c992..0c4ee6a767b8 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -143,6 +143,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-rock-5b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-rock-5b-pcie-ep.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-rock-5b-pcie-srns.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-tiger-haikou.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-tiger-haikou-video-demo.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-toybrick-x0.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-turing-rk1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-coolpi-4b.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou-video-demo.dt= so b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou-video-demo.dtso new file mode 100644 index 000000000000..c7416349e7d5 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou-video-demo.dtso @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * DT-overlay for the camera / DSI demo appliance for Haikou boards. + * In the flavour for use with a Tiger system-on-module. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +&{/} { + video-adapter-leds { + compatible =3D "gpio-leds"; + status =3D "okay"; + + video-adapter-led { + color =3D ; + gpios =3D <&pca9670 7 GPIO_ACTIVE_HIGH>; + label =3D "video-adapter-led"; + linux,default-trigger =3D "none"; + }; + }; + + backlight: backlight { + compatible =3D "pwm-backlight"; + power-supply =3D <&dc_12v>; + pwms =3D <&pwm0 0 25000 0>; + }; + + hdmi-con { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint =3D <&hdmi0_out_con>; + }; + }; + }; + + vcc1v8_video: regulator-vcc1v8-video { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc1v8-video"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&vcc3v3_baseboard>; + }; + + vcc2v8_video: regulator-vcc2v8-video { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc2v8-video"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + vin-supply =3D <&vcc3v3_baseboard>; + }; +}; + +&dsi0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + panel@0 { + compatible =3D "leadtek,ltk050h3148w"; + reg =3D <0>; + backlight =3D <&backlight>; + iovcc-supply =3D <&vcc1v8_video>; + reset-gpios =3D <&pca9670 0 GPIO_ACTIVE_LOW>; + vci-supply =3D <&vcc2v8_video>; + + port { + mipi_panel_in: endpoint { + remote-endpoint =3D <&dsi0_out_panel>; + }; + }; + }; +}; + +&dsi0_in { + dsi0_in_vp3: endpoint { + remote-endpoint =3D <&vp3_out_dsi0>; + }; +}; + +&dsi0_out { + dsi0_out_panel: endpoint { + remote-endpoint =3D <&mipi_panel_in>; + }; +}; + +&i2c6 { + /* OV5675, GT911, DW9714 are limited to 400KHz */ + clock-frequency =3D <400000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + touchscreen@14 { + compatible =3D "goodix,gt911"; + reg =3D <0x14>; + interrupt-parent =3D <&gpio3>; + interrupts =3D ; + irq-gpios =3D <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&touch_int>; + pinctrl-names =3D "default"; + reset-gpios =3D <&pca9670 1 GPIO_ACTIVE_HIGH>; + AVDD28-supply =3D <&vcc2v8_video>; + VDDIO-supply =3D <&vcc3v3_baseboard>; + }; + + pca9670: gpio@27 { + compatible =3D "nxp,pca9670"; + reg =3D <0x27>; + gpio-controller; + #gpio-cells =3D <2>; + }; +}; + +&mipidcphy0 { + status =3D "okay"; +}; + +&pinctrl { + touch { + touch_int: touch-int { + rockchip,pins =3D <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + pinctrl-0 =3D <&pwm0m1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&vp3 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + vp3_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 { + reg =3D ; + remote-endpoint =3D <&dsi0_in_vp3>; + }; +}; --=20 2.45.2