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[114.74.229.70]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-211057d3f87sm93796755ad.249.2024.11.06.03.41.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2024 03:41:44 -0800 (PST) From: Orange Kao To: tony.luck@intel.com, qiuxu.zhuo@intel.com Cc: bp@alien8.de, james.morse@arm.com, orange@kaosy.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, mchehab@kernel.org, rric@kernel.org, Orange Kao Subject: [PATCH 3/3] EDAC/igen6: Allow setting edac_op_state Date: Wed, 6 Nov 2024 11:35:47 +0000 Message-ID: <20241106114024.941659-4-orange@aiven.io> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241106114024.941659-1-orange@aiven.io> References: <20241106114024.941659-1-orange@aiven.io> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Current implementation does not allow users to set edac_op_state. As a result, if a user needs to test different edac_op_state, they need to compile the kernel. This commit accepts module parameter edac_op_state which makes it easier for users to test IBECC on their hardware. Signed-off-by: Orange Kao --- drivers/edac/igen6_edac.c | 34 ++++++++++++++++++++++++++-------- 1 file changed, 26 insertions(+), 8 deletions(-) diff --git a/drivers/edac/igen6_edac.c b/drivers/edac/igen6_edac.c index dd62aa1ea9c3..025f994f7bf0 100644 --- a/drivers/edac/igen6_edac.c +++ b/drivers/edac/igen6_edac.c @@ -1341,16 +1341,18 @@ static int register_err_handler(void) { int rc; =20 - if (res_cfg->machine_check) { + if (edac_op_state =3D=3D EDAC_OPSTATE_INT) { mce_register_decode_chain(&ecclog_mce_dec); return 0; } =20 - rc =3D register_nmi_handler(NMI_SERR, ecclog_nmi_handler, - 0, IGEN6_NMI_NAME); - if (rc) { - igen6_printk(KERN_ERR, "Failed to register NMI handler\n"); - return rc; + if (edac_op_state =3D=3D EDAC_OPSTATE_NMI) { + rc =3D register_nmi_handler(NMI_SERR, ecclog_nmi_handler, + 0, IGEN6_NMI_NAME); + if (rc) { + igen6_printk(KERN_ERR, "Failed to register NMI handler\n"); + return rc; + } } =20 return 0; @@ -1358,16 +1360,29 @@ static int register_err_handler(void) =20 static void unregister_err_handler(void) { - if (res_cfg->machine_check) { + if (edac_op_state =3D=3D EDAC_OPSTATE_INT) { mce_unregister_decode_chain(&ecclog_mce_dec); return; } =20 - unregister_nmi_handler(NMI_SERR, IGEN6_NMI_NAME); + if (edac_op_state =3D=3D EDAC_OPSTATE_NMI) + unregister_nmi_handler(NMI_SERR, IGEN6_NMI_NAME); } =20 static void opstate_set(struct res_config *cfg, const struct pci_device_id= *ent) { + switch (edac_op_state) { + case EDAC_OPSTATE_POLL: + case EDAC_OPSTATE_NMI: + case EDAC_OPSTATE_INT: + return; + case EDAC_OPSTATE_INVAL: + break; + default: + edac_op_state =3D EDAC_OPSTATE_INVAL; + break; + } + /* * Quirk: Certain SoCs' error reporting interrupts don't work. * Force polling mode for them to ensure that memory error @@ -1509,3 +1524,6 @@ module_exit(igen6_exit); MODULE_LICENSE("GPL v2"); MODULE_AUTHOR("Qiuxu Zhuo"); MODULE_DESCRIPTION("MC Driver for Intel client SoC using In-Band ECC"); + +module_param(edac_op_state, int, 0444); +MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=3DPoll, 1= =3DNMI, 2=3DMachine Check, Default=3DAuto detect"); --=20 2.47.0