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[114.74.229.70]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-211057d3f87sm93796755ad.249.2024.11.06.03.41.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2024 03:41:30 -0800 (PST) From: Orange Kao To: tony.luck@intel.com, qiuxu.zhuo@intel.com Cc: bp@alien8.de, james.morse@arm.com, orange@kaosy.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, mchehab@kernel.org, rric@kernel.org, Orange Kao Subject: [PATCH 2/3] EDAC/igen6: Add polling support Date: Wed, 6 Nov 2024 11:35:46 +0000 Message-ID: <20241106114024.941659-3-orange@aiven.io> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241106114024.941659-1-orange@aiven.io> References: <20241106114024.941659-1-orange@aiven.io> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some PCs with Intel N100 (with PCI device 8086:461c, DID_ADL_N_SKU4) experienced issues with error interrupts not working, even with the following configuration in the BIOS. In-Band ECC Support: Enabled In-Band ECC Operation Mode: 2 (make all requests protected and ignore range checks) IBECC Error Injection Control: Inject Correctable Error on insertion counter Error Injection Insertion Count: 251658240 (0xf000000) Add polling mode support for these machines to ensure that memory error events are handled. Signed-off-by: Orange Kao --- drivers/edac/igen6_edac.c | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/drivers/edac/igen6_edac.c b/drivers/edac/igen6_edac.c index fa488ba15059..dd62aa1ea9c3 100644 --- a/drivers/edac/igen6_edac.c +++ b/drivers/edac/igen6_edac.c @@ -1170,6 +1170,20 @@ static int igen6_pci_setup(struct pci_dev *pdev, u64= *mchbar) return -ENODEV; } =20 +static void igen6_check(struct mem_ctl_info *mci) +{ + struct igen6_imc *imc =3D mci->pvt_info; + u64 ecclog; + + /* errsts_clear() isn't NMI-safe. Delay it in the IRQ context */ + ecclog =3D ecclog_read_and_clear(imc); + if (!ecclog) + return; + + if (!ecclog_gen_pool_add(imc->mc, ecclog)) + irq_work_queue(&ecclog_irq_work); +} + static int igen6_register_mci(int mc, u64 mchbar, struct pci_dev *pdev) { struct edac_mc_layer layers[2]; @@ -1211,6 +1225,8 @@ static int igen6_register_mci(int mc, u64 mchbar, str= uct pci_dev *pdev) mci->edac_cap =3D EDAC_FLAG_SECDED; mci->mod_name =3D EDAC_MOD_STR; mci->dev_name =3D pci_name(pdev); + if (edac_op_state =3D=3D EDAC_OPSTATE_POLL) + mci->edac_check =3D igen6_check; mci->pvt_info =3D &igen6_pvt->imc[mc]; =20 imc =3D mci->pvt_info; @@ -1350,8 +1366,18 @@ static void unregister_err_handler(void) unregister_nmi_handler(NMI_SERR, IGEN6_NMI_NAME); } =20 -static void opstate_set(struct res_config *cfg) +static void opstate_set(struct res_config *cfg, const struct pci_device_id= *ent) { + /* + * Quirk: Certain SoCs' error reporting interrupts don't work. + * Force polling mode for them to ensure that memory error + * events can be handled. + */ + if (ent->device =3D=3D DID_ADL_N_SKU4) { + edac_op_state =3D EDAC_OPSTATE_POLL; + return; + } + /* Set the mode according to the configuration data. */ if (cfg->machine_check) edac_op_state =3D EDAC_OPSTATE_INT; @@ -1376,7 +1402,7 @@ static int igen6_probe(struct pci_dev *pdev, const st= ruct pci_device_id *ent) if (rc) goto fail; =20 - opstate_set(res_cfg); + opstate_set(res_cfg, ent); =20 for (i =3D 0; i < res_cfg->num_imc; i++) { rc =3D igen6_register_mci(i, mchbar, pdev); --=20 2.47.0