From nobody Sun Nov 24 08:24:48 2024 Received: from mail-43166.protonmail.ch (mail-43166.protonmail.ch [185.70.43.166]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 47FE218C00E; Wed, 6 Nov 2024 11:14:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.43.166 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730891678; cv=none; b=egNsQY/1cnHQVNN6QpuXmJJtNJx4pG5MHvdAO2ftVoIQEa3GmxFJsqqSkAaFGSM7zRcrSc8Ddnf+ImFvN4c/pPJc8DtnBcSpVn48J/+b0LFrXuf+AnIErHX0yYWAf9wjNVg/OU0N7M1PE2T3VUbNek5E6x4NlRPMXUcPxPSayKs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730891678; c=relaxed/simple; bh=sz29BWhsMKvi3hg3lJ2xWbNvjd6NkavB0nd1gEBfOAY=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=WVcsIAD8qxvsHml0bryc9DipL1e7+YgJQm9Axdj3qEl4nQ+PtDURYAdeGDuTuhAHE4KOzt+LS69nEHys5PRvO/stqUidldSRiWeqzSVMUHZTGzPPOP6zqil8xu/6JHA0lRFmchedHuzoFR1hfuGEIbO7sCJyJf1+3wmS3Y3EUXg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=protonmail.com; spf=pass smtp.mailfrom=protonmail.com; dkim=pass (2048-bit key) header.d=protonmail.com header.i=@protonmail.com header.b=JbZc5I4r; arc=none smtp.client-ip=185.70.43.166 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=protonmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=protonmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=protonmail.com header.i=@protonmail.com header.b="JbZc5I4r" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=protonmail.com; s=protonmail3; t=1730891674; x=1731150874; bh=f2Qe7fc8Rc+0pOAStlB9e/yB/Xw4CrjrYCA0t8+DY84=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector:List-Unsubscribe:List-Unsubscribe-Post; b=JbZc5I4rgog7sLjwZk6liHoCvGeRGqObx6qN9im77n1mYeUgDqN36G1sME+1H4Vjg p+iqKkr/99Z+KRfiffUMq7eqC5iZUQsc5gGduO1UBblhDkY44/bCFzezUgxw2DL4ov i88TXy+IwuF6PBrAE3gBqg1S4rrsUoecW+itPfzU5h8zQTwAfaNsMruwFqWOMMZr0k FkGhnEedjDgvF7NipJYGozMA1gbEe86OediChUMoGyNbruxXy0fGRt4TNNqfE4EqEj 3IOFyvSw7DTDWicTI76VdMJ6/123Z9dg60NyfwsGM57spg4tr1dK9R3osGSVuPRw/c MXsQhfYwj0LxQ== Date: Wed, 06 Nov 2024 11:14:30 +0000 To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Philipp Zabel , Sam Shih , Lukas Bulwahn , Daniel Golle From: Yassine Oudjana Cc: Yassine Oudjana , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Conor Dooley Subject: [PATCH v2 1/2] dt-bindings: clock: mediatek: Add bindings for MT6735 syscon clock and reset controllers Message-ID: <20241106111402.200940-2-y.oudjana@protonmail.com> In-Reply-To: <20241106111402.200940-1-y.oudjana@protonmail.com> References: <20241106111402.200940-1-y.oudjana@protonmail.com> Feedback-ID: 6882736:user:proton X-Pm-Message-ID: 3e1ea39ec08bb0cd65c2f895318f0493916e1ea4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree bindings for syscon clock and reset controllers (IMGSYS, MFGCFG, VDECSYS and VENCSYS). Signed-off-by: Yassine Oudjana Reviewed-by: AngeloGioacchino Del Regno Acked-by: Conor Dooley --- .../bindings/clock/mediatek,syscon.yaml | 4 ++++ MAINTAINERS | 6 ++++++ .../dt-bindings/clock/mediatek,mt6735-imgsys.h | 15 +++++++++++++++ .../dt-bindings/clock/mediatek,mt6735-mfgcfg.h | 8 ++++++++ .../dt-bindings/clock/mediatek,mt6735-vdecsys.h | 9 +++++++++ .../dt-bindings/clock/mediatek,mt6735-vencsys.h | 11 +++++++++++ .../dt-bindings/reset/mediatek,mt6735-mfgcfg.h | 9 +++++++++ .../dt-bindings/reset/mediatek,mt6735-vdecsys.h | 9 +++++++++ 8 files changed, 71 insertions(+) create mode 100644 include/dt-bindings/clock/mediatek,mt6735-imgsys.h create mode 100644 include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h create mode 100644 include/dt-bindings/clock/mediatek,mt6735-vdecsys.h create mode 100644 include/dt-bindings/clock/mediatek,mt6735-vencsys.h create mode 100644 include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h create mode 100644 include/dt-bindings/reset/mediatek,mt6735-vdecsys.h diff --git a/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml b= /Documentation/devicetree/bindings/clock/mediatek,syscon.yaml index 10483e26878fb..a86a64893c675 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml @@ -28,6 +28,10 @@ properties: - mediatek,mt2712-mfgcfg - mediatek,mt2712-vdecsys - mediatek,mt2712-vencsys + - mediatek,mt6735-imgsys + - mediatek,mt6735-mfgcfg + - mediatek,mt6735-vdecsys + - mediatek,mt6735-vencsys - mediatek,mt6765-camsys - mediatek,mt6765-imgsys - mediatek,mt6765-mipi0a diff --git a/MAINTAINERS b/MAINTAINERS index f595ee8c2d145..0ddb557f7fef9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14625,11 +14625,17 @@ F: drivers/clk/mediatek/clk-mt6735-infracfg.c F: drivers/clk/mediatek/clk-mt6735-pericfg.c F: drivers/clk/mediatek/clk-mt6735-topckgen.c F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h +F: include/dt-bindings/clock/mediatek,mt6735-imgsys.h F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h +F: include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h F: include/dt-bindings/clock/mediatek,mt6735-pericfg.h F: include/dt-bindings/clock/mediatek,mt6735-topckgen.h +F: include/dt-bindings/clock/mediatek,mt6735-vdecsys.h +F: include/dt-bindings/clock/mediatek,mt6735-vencsys.h F: include/dt-bindings/reset/mediatek,mt6735-infracfg.h +F: include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h F: include/dt-bindings/reset/mediatek,mt6735-pericfg.h +F: include/dt-bindings/reset/mediatek,mt6735-vdecsys.h =20 MEDIATEK MT76 WIRELESS LAN DRIVER M: Felix Fietkau diff --git a/include/dt-bindings/clock/mediatek,mt6735-imgsys.h b/include/d= t-bindings/clock/mediatek,mt6735-imgsys.h new file mode 100644 index 0000000000000..f250c26c5eb4d --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt6735-imgsys.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLK_MT6735_IMGSYS_H +#define _DT_BINDINGS_CLK_MT6735_IMGSYS_H + +#define CLK_IMG_SMI_LARB2 0 +#define CLK_IMG_CAM_SMI 1 +#define CLK_IMG_CAM_CAM 2 +#define CLK_IMG_SEN_TG 3 +#define CLK_IMG_SEN_CAM 4 +#define CLK_IMG_CAM_SV 5 +#define CLK_IMG_SUFOD 6 +#define CLK_IMG_FD 7 + +#endif /* _DT_BINDINGS_CLK_MT6735_IMGSYS_H */ diff --git a/include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h b/include/d= t-bindings/clock/mediatek,mt6735-mfgcfg.h new file mode 100644 index 0000000000000..d2d99a48348a0 --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt6735-mfgcfg.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLK_MT6735_MFGCFG_H +#define _DT_BINDINGS_CLK_MT6735_MFGCFG_H + +#define CLK_MFG_BG3D 0 + +#endif /* _DT_BINDINGS_CLK_MT6735_MFGCFG_H */ diff --git a/include/dt-bindings/clock/mediatek,mt6735-vdecsys.h b/include/= dt-bindings/clock/mediatek,mt6735-vdecsys.h new file mode 100644 index 0000000000000..f94cec10c89ff --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt6735-vdecsys.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLK_MT6735_VDECSYS_H +#define _DT_BINDINGS_CLK_MT6735_VDECSYS_H + +#define CLK_VDEC_VDEC 0 +#define CLK_VDEC_SMI_LARB1 1 + +#endif /* _DT_BINDINGS_CLK_MT6735_VDECSYS_H */ diff --git a/include/dt-bindings/clock/mediatek,mt6735-vencsys.h b/include/= dt-bindings/clock/mediatek,mt6735-vencsys.h new file mode 100644 index 0000000000000..e5a9cb4f269ff --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt6735-vencsys.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLK_MT6735_VENCSYS_H +#define _DT_BINDINGS_CLK_MT6735_VENCSYS_H + +#define CLK_VENC_SMI_LARB3 0 +#define CLK_VENC_VENC 1 +#define CLK_VENC_JPGENC 2 +#define CLK_VENC_JPGDEC 3 + +#endif /* _DT_BINDINGS_CLK_MT6735_VENCSYS_H */ diff --git a/include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h b/include/d= t-bindings/reset/mediatek,mt6735-mfgcfg.h new file mode 100644 index 0000000000000..c489242b226e2 --- /dev/null +++ b/include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_RESET_MT6735_MFGCFG_H +#define _DT_BINDINGS_RESET_MT6735_MFGCFG_H + +#define MT6735_MFG_RST0_AXI 0 +#define MT6735_MFG_RST0_G3D 1 + +#endif /* _DT_BINDINGS_RESET_MT6735_MFGCFG_H */ diff --git a/include/dt-bindings/reset/mediatek,mt6735-vdecsys.h b/include/= dt-bindings/reset/mediatek,mt6735-vdecsys.h new file mode 100644 index 0000000000000..b6ae5d249192b --- /dev/null +++ b/include/dt-bindings/reset/mediatek,mt6735-vdecsys.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_RESET_MT6735_VDECSYS_H +#define _DT_BINDINGS_RESET_MT6735_VDECSYS_H + +#define MT6735_VDEC_RST0_VDEC 0 +#define MT6735_VDEC_RST1_SMI_LARB1 1 + +#endif /* _DT_BINDINGS_RESET_MT6735_VDECSYS_H */ --=20 2.47.0 From nobody Sun Nov 24 08:24:48 2024 Received: from mail-4319.protonmail.ch (mail-4319.protonmail.ch [185.70.43.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F3D81DE886 for ; Wed, 6 Nov 2024 11:14:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.43.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730891686; cv=none; b=FwRXtENybZWCNzU8GeORnaU1um06MBwvRKtw8KxAb79Na/bG97R3JQ9WoBVtJlc+LuME+U7lQckUtS2Fks0D7M/hE1QZmyWiJkL6NXbxurAprdNQPLpmIYk51Nm9os8PetnyaEnYwbEzm9GbAVyLSkyd7dQEDeFhuXINdswO60A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730891686; c=relaxed/simple; bh=03pXt+HbCk3nApBhK6JMotbiaZ0oM+N5e5rfP3p/mRk=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: 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h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector:List-Unsubscribe:List-Unsubscribe-Post; b=VOPJh4ZUDC3lfmyz9SRbVX2kET4FLzs8fcJMvGuVJE5cGirkQdufazFm/bCphbKwX UgFIETVo8sMfahj3dirEb+KhXsuz5oVH3i/zfIrtIo8HlsW1m+etN/fkQdzZd2VDm4 5T+VSkOlUX88JJFEYsQrDS3w0SsLIs93UmAzmYvgHUCBeiqScDq912fZea2WOXfyeA nHtvPiapaCujzRqZsnNNDqPvVHx9K//15T+P/Qwe+n3IGuGliXtlTVtyRMZLRFNJTJ iUhqDCGvdDodgmUx5qXcxgfqeoT9p2h6SySZnDGkrocLkLOK3T1INaYBapIaaG5+Jg c2X39oVYCAjTg== Date: Wed, 06 Nov 2024 11:14:37 +0000 To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Philipp Zabel , Sam Shih , Lukas Bulwahn , Daniel Golle From: Yassine Oudjana Cc: Yassine Oudjana , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 2/2] clk: mediatek: Add drivers for MT6735 syscon clock and reset controllers Message-ID: <20241106111402.200940-3-y.oudjana@protonmail.com> In-Reply-To: <20241106111402.200940-1-y.oudjana@protonmail.com> References: <20241106111402.200940-1-y.oudjana@protonmail.com> Feedback-ID: 6882736:user:proton X-Pm-Message-ID: 1eb11f123cf4723be67fb6c20ef154d39bc46bd0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add drivers for IMGSYS, MFGCFG, VDECSYS and VENCSYS clocks and resets on MT6735. Signed-off-by: Yassine Oudjana --- MAINTAINERS | 4 ++ drivers/clk/mediatek/Kconfig | 28 ++++++++ drivers/clk/mediatek/Makefile | 4 ++ drivers/clk/mediatek/clk-mt6735-imgsys.c | 57 ++++++++++++++++ drivers/clk/mediatek/clk-mt6735-mfgcfg.c | 61 +++++++++++++++++ drivers/clk/mediatek/clk-mt6735-vdecsys.c | 79 +++++++++++++++++++++++ drivers/clk/mediatek/clk-mt6735-vencsys.c | 53 +++++++++++++++ 7 files changed, 286 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt6735-imgsys.c create mode 100644 drivers/clk/mediatek/clk-mt6735-mfgcfg.c create mode 100644 drivers/clk/mediatek/clk-mt6735-vdecsys.c create mode 100644 drivers/clk/mediatek/clk-mt6735-vencsys.c diff --git a/MAINTAINERS b/MAINTAINERS index 0ddb557f7fef9..16480ccd197a7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14621,9 +14621,13 @@ L: linux-clk@vger.kernel.org L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) S: Maintained F: drivers/clk/mediatek/clk-mt6735-apmixedsys.c +F: drivers/clk/mediatek/clk-mt6735-imgsys.c F: drivers/clk/mediatek/clk-mt6735-infracfg.c +F: drivers/clk/mediatek/clk-mt6735-mfgcfg.c F: drivers/clk/mediatek/clk-mt6735-pericfg.c F: drivers/clk/mediatek/clk-mt6735-topckgen.c +F: drivers/clk/mediatek/clk-mt6735-vdecsys.c +F: drivers/clk/mediatek/clk-mt6735-vencsys.c F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h F: include/dt-bindings/clock/mediatek,mt6735-imgsys.h F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 7a33f9e92d963..5f8e6d68fa148 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -133,6 +133,34 @@ config COMMON_CLK_MT6735 by apmixedsys, topckgen, infracfg and pericfg on the MediaTek MT6735 SoC. =20 +config COMMON_CLK_MT6735_IMGSYS + tristate "Clock driver for MediaTek MT6735 imgsys" + depends on COMMON_CLK_MT6735 + help + This enables a driver for clocks provided by imgsys + on the MediaTek MT6735 SoC. + +config COMMON_CLK_MT6735_MFGCFG + tristate "Clock driver for MediaTek MT6735 mfgcfg" + depends on COMMON_CLK_MT6735 + help + This enables a driver for clocks and resets provided + by mfgcfg on the MediaTek MT6735 SoC. + +config COMMON_CLK_MT6735_VDECSYS + tristate "Clock driver for MediaTek MT6735 vdecsys" + depends on COMMON_CLK_MT6735 + help + This enables a driver for clocks and resets provided + by vdecsys on the MediaTek MT6735 SoC. + +config COMMON_CLK_MT6735_VENCSYS + tristate "Clock driver for MediaTek MT6735 vencsys" + depends on COMMON_CLK_MT6735 + help + This enables a driver for clocks provided by vencsys + on the MediaTek MT6735 SoC. + config COMMON_CLK_MT6765 bool "Clock driver for MediaTek MT6765" depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 70456ffc6c492..6efec95406bd5 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -3,6 +3,10 @@ obj-$(CONFIG_COMMON_CLK_MEDIATEK) +=3D clk-mtk.o clk-pll.o= clk-gate.o clk-apmixed. obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) +=3D clk-fhctl.o clk-pllfh.o =20 obj-$(CONFIG_COMMON_CLK_MT6735) +=3D clk-mt6735-apmixedsys.o clk-mt6735-in= fracfg.o clk-mt6735-pericfg.o clk-mt6735-topckgen.o +obj-$(CONFIG_COMMON_CLK_MT6735_IMGSYS) +=3D clk-mt6735-imgsys.o +obj-$(CONFIG_COMMON_CLK_MT6735_MFGCFG) +=3D clk-mt6735-mfgcfg.o +obj-$(CONFIG_COMMON_CLK_MT6735_VDECSYS) +=3D clk-mt6735-vdecsys.o +obj-$(CONFIG_COMMON_CLK_MT6735_VENCSYS) +=3D clk-mt6735-vencsys.o obj-$(CONFIG_COMMON_CLK_MT6765) +=3D clk-mt6765.o obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) +=3D clk-mt6765-audio.o obj-$(CONFIG_COMMON_CLK_MT6765_CAMSYS) +=3D clk-mt6765-cam.o diff --git a/drivers/clk/mediatek/clk-mt6735-imgsys.c b/drivers/clk/mediate= k/clk-mt6735-imgsys.c new file mode 100644 index 0000000000000..c564f8f724324 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6735-imgsys.c @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Yassine Oudjana + */ + +#include +#include + +#include "clk-gate.h" +#include "clk-mtk.h" + +#include + +#define IMG_CG_CON 0x00 +#define IMG_CG_SET 0x04 +#define IMG_CG_CLR 0x08 + +static struct mtk_gate_regs imgsys_cg_regs =3D { + .set_ofs =3D IMG_CG_SET, + .clr_ofs =3D IMG_CG_CLR, + .sta_ofs =3D IMG_CG_CON, +}; + +static const struct mtk_gate imgsys_gates[] =3D { + GATE_MTK(CLK_IMG_SMI_LARB2, "smi_larb2", "mm_sel", &imgsys_cg_regs, 0, &m= tk_clk_gate_ops_setclr), + GATE_MTK(CLK_IMG_CAM_SMI, "cam_smi", "mm_sel", &imgsys_cg_regs, 5, &mtk_c= lk_gate_ops_setclr), + GATE_MTK(CLK_IMG_CAM_CAM, "cam_cam", "mm_sel", &imgsys_cg_regs, 6, &mtk_c= lk_gate_ops_setclr), + GATE_MTK(CLK_IMG_SEN_TG, "sen_tg", "mm_sel", &imgsys_cg_regs, 7, &mtk_clk= _gate_ops_setclr), + GATE_MTK(CLK_IMG_SEN_CAM, "sen_cam", "mm_sel", &imgsys_cg_regs, 8, &mtk_c= lk_gate_ops_setclr), + GATE_MTK(CLK_IMG_CAM_SV, "cam_sv", "mm_sel", &imgsys_cg_regs, 9, &mtk_clk= _gate_ops_setclr), + GATE_MTK(CLK_IMG_SUFOD, "sufod", "mm_sel", &imgsys_cg_regs, 10, &mtk_clk_= gate_ops_setclr), + GATE_MTK(CLK_IMG_FD, "fd", "mm_sel", &imgsys_cg_regs, 11, &mtk_clk_gate_o= ps_setclr), +}; + +static const struct mtk_clk_desc imgsys_clks =3D { + .clks =3D imgsys_gates, + .num_clks =3D ARRAY_SIZE(imgsys_gates), +}; + +static const struct of_device_id of_match_mt6735_imgsys[] =3D { + { .compatible =3D "mediatek,mt6735-imgsys", .data =3D &imgsys_clks }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt6735_imgsys =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt6735-imgsys", + .of_match_table =3D of_match_mt6735_imgsys, + }, +}; +module_platform_driver(clk_mt6735_imgsys); + +MODULE_AUTHOR("Yassine Oudjana "); +MODULE_DESCRIPTION("MediaTek MT6735 imgsys clock driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6735-mfgcfg.c b/drivers/clk/mediate= k/clk-mt6735-mfgcfg.c new file mode 100644 index 0000000000000..1f5aedddf209d --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6735-mfgcfg.c @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Yassine Oudjana + */ + +#include +#include + +#include "clk-gate.h" +#include "clk-mtk.h" + +#include + +#define MFG_CG_CON 0x00 +#define MFG_CG_SET 0x04 +#define MFG_CG_CLR 0x08 +#define MFG_RESET 0x0c + +static struct mtk_gate_regs mfgcfg_cg_regs =3D { + .set_ofs =3D MFG_CG_SET, + .clr_ofs =3D MFG_CG_CLR, + .sta_ofs =3D MFG_CG_CON, +}; + +static const struct mtk_gate mfgcfg_gates[] =3D { + GATE_MTK(CLK_MFG_BG3D, "bg3d", "mfg_sel", &mfgcfg_cg_regs, 0, &mtk_clk_ga= te_ops_setclr), +}; + +static u16 mfgcfg_rst_ofs[] =3D { MFG_RESET }; + +static const struct mtk_clk_rst_desc mfgcfg_resets =3D { + .version =3D MTK_RST_SIMPLE, + .rst_bank_ofs =3D mfgcfg_rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(mfgcfg_rst_ofs) +}; + +static const struct mtk_clk_desc mfgcfg_clks =3D { + .clks =3D mfgcfg_gates, + .num_clks =3D ARRAY_SIZE(mfgcfg_gates), + + .rst_desc =3D &mfgcfg_resets +}; + +static const struct of_device_id of_match_mt6735_mfgcfg[] =3D { + { .compatible =3D "mediatek,mt6735-mfgcfg", .data =3D &mfgcfg_clks }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt6735_mfgcfg =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt6735-mfgcfg", + .of_match_table =3D of_match_mt6735_mfgcfg, + }, +}; +module_platform_driver(clk_mt6735_mfgcfg); + +MODULE_AUTHOR("Yassine Oudjana "); +MODULE_DESCRIPTION("Mediatek MT6735 mfgcfg clock and reset driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6735-vdecsys.c b/drivers/clk/mediat= ek/clk-mt6735-vdecsys.c new file mode 100644 index 0000000000000..8817085fc1db4 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6735-vdecsys.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Yassine Oudjana + */ + +#include +#include + +#include "clk-gate.h" +#include "clk-mtk.h" + +#include +#include + +#define VDEC_CKEN_SET 0x00 +#define VDEC_CKEN_CLR 0x04 +#define SMI_LARB1_CKEN_SET 0x08 +#define SMI_LARB1_CKEN_CLR 0x0c +#define VDEC_RESETB_CON 0x10 +#define SMI_LARB1_RESETB_CON 0x14 + +#define RST_NR_PER_BANK 32 + +static struct mtk_gate_regs vdec_cg_regs =3D { + .set_ofs =3D VDEC_CKEN_SET, + .clr_ofs =3D VDEC_CKEN_CLR, + .sta_ofs =3D VDEC_CKEN_SET, +}; + +static struct mtk_gate_regs smi_larb1_cg_regs =3D { + .set_ofs =3D SMI_LARB1_CKEN_SET, + .clr_ofs =3D SMI_LARB1_CKEN_CLR, + .sta_ofs =3D SMI_LARB1_CKEN_SET, +}; + +static const struct mtk_gate vdecsys_gates[] =3D { + GATE_MTK(CLK_VDEC_VDEC, "vdec", "vdec_sel", &vdec_cg_regs, 0, &mtk_clk_ga= te_ops_setclr_inv), + GATE_MTK(CLK_VDEC_SMI_LARB1, "smi_larb1", "vdec_sel", &smi_larb1_cg_regs,= 0, &mtk_clk_gate_ops_setclr_inv), +}; + +static u16 vdecsys_rst_bank_ofs[] =3D { VDEC_RESETB_CON, SMI_LARB1_RESETB_= CON }; + +static u16 vdecsys_rst_idx_map[] =3D { + [MT6735_VDEC_RST0_VDEC] =3D 0 * RST_NR_PER_BANK + 0, + [MT6735_VDEC_RST1_SMI_LARB1] =3D 1 * RST_NR_PER_BANK + 0, +}; + +static const struct mtk_clk_rst_desc vdecsys_resets =3D { + .version =3D MTK_RST_SIMPLE, + .rst_bank_ofs =3D vdecsys_rst_bank_ofs, + .rst_bank_nr =3D ARRAY_SIZE(vdecsys_rst_bank_ofs), + .rst_idx_map =3D vdecsys_rst_idx_map, + .rst_idx_map_nr =3D ARRAY_SIZE(vdecsys_rst_idx_map) +}; + +static const struct mtk_clk_desc vdecsys_clks =3D { + .clks =3D vdecsys_gates, + .num_clks =3D ARRAY_SIZE(vdecsys_gates), + .rst_desc =3D &vdecsys_resets +}; + +static const struct of_device_id of_match_mt6735_vdecsys[] =3D { + { .compatible =3D "mediatek,mt6735-vdecsys", .data =3D &vdecsys_clks }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt6735_vdecsys =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt6735-vdecsys", + .of_match_table =3D of_match_mt6735_vdecsys, + }, +}; +module_platform_driver(clk_mt6735_vdecsys); + +MODULE_AUTHOR("Yassine Oudjana "); +MODULE_DESCRIPTION("MediaTek MT6735 vdecsys clock and reset driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6735-vencsys.c b/drivers/clk/mediat= ek/clk-mt6735-vencsys.c new file mode 100644 index 0000000000000..8dec7f98492ac --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6735-vencsys.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Yassine Oudjana + */ + +#include +#include + +#include "clk-gate.h" +#include "clk-mtk.h" + +#include + +#define VENC_CG_CON 0x00 +#define VENC_CG_SET 0x04 +#define VENC_CG_CLR 0x08 + +static struct mtk_gate_regs venc_cg_regs =3D { + .set_ofs =3D VENC_CG_SET, + .clr_ofs =3D VENC_CG_CLR, + .sta_ofs =3D VENC_CG_CON, +}; + +static const struct mtk_gate vencsys_gates[] =3D { + GATE_MTK(CLK_VENC_SMI_LARB3, "smi_larb3", "mm_sel", &venc_cg_regs, 0, &mt= k_clk_gate_ops_setclr_inv), + GATE_MTK(CLK_VENC_VENC, "venc", "mm_sel", &venc_cg_regs, 4, &mtk_clk_gate= _ops_setclr_inv), + GATE_MTK(CLK_VENC_JPGENC, "jpgenc", "mm_sel", &venc_cg_regs, 8, &mtk_clk_= gate_ops_setclr_inv), + GATE_MTK(CLK_VENC_JPGDEC, "jpgdec", "mm_sel", &venc_cg_regs, 12, &mtk_clk= _gate_ops_setclr_inv), +}; + +static const struct mtk_clk_desc vencsys_clks =3D { + .clks =3D vencsys_gates, + .num_clks =3D ARRAY_SIZE(vencsys_gates), +}; + +static const struct of_device_id of_match_mt6735_vencsys[] =3D { + { .compatible =3D "mediatek,mt6735-vencsys", .data =3D &vencsys_clks }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt6735_vencsys =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt6735-vencsys", + .of_match_table =3D of_match_mt6735_vencsys, + }, +}; +module_platform_driver(clk_mt6735_vencsys); + +MODULE_AUTHOR("Yassine Oudjana "); +MODULE_DESCRIPTION("Mediatek MT6735 vencsys clock driver"); +MODULE_LICENSE("GPL"); --=20 2.47.0