From nobody Sun Nov 24 11:42:27 2024 Received: from mail-ej1-f52.google.com (mail-ej1-f52.google.com [209.85.218.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A49641DED7F for ; Wed, 6 Nov 2024 09:06:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730883977; cv=none; b=rUYb5IITCCGNKihdj+ExRNkjwBIZ0AjZJPMnKOgb5w2tqTKxAW7TpwgYLOCTllNZyDD2xRpdAb7/8D/Ufqdraq1KyNIxhfemiJkNHkWGuNuhoE/CihlAo7rdR+T8NGe8t2VTexn+k+KpE2DObluW5+/8LvuHHJh1AO2eSKYijWQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730883977; c=relaxed/simple; bh=TppeIDLKz2J3v9NGgQy7CfNROB4hnypZb4DnJxcFOxA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KYtCzsiHXyZ2aKBIrbKHxer/eNt1OP5Ir/EaLw+FeTz/UorWj0eGadgiVUMoMmOq8DGGD7A4U+REWWg7YH0rGZluETzsCoMo6eS2qISiJ0F/LixIot/Tdm2B3a3raZn1uZnEh+F/bAbkpLGYO6wyYrlR7DzX0IiTol/2TljaBYc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=ow8DGRow; arc=none smtp.client-ip=209.85.218.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="ow8DGRow" Received: by mail-ej1-f52.google.com with SMTP id a640c23a62f3a-a9a4031f69fso1021383666b.0 for ; Wed, 06 Nov 2024 01:06:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1730883974; x=1731488774; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=K9/BOp61tpriPDyxNyMCGSbfD3+1Oa6yDDGnpxFC9Dw=; b=ow8DGRowV9NSqDFfecxAch4eL6DvXZW790emT4fwYqj/xRTiAd6tRUnEkVKIlsSVuU 4BmaGhXA2PHTB8tiSqiOq9wYK61iMEwB519BGuxHWorDZoUUZ1WjqcRJzx2wIxpJPuI2 e7caG+Ll+F5LMB+QCTAOCzxa+SWBAdVLjnfwU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730883974; x=1731488774; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=K9/BOp61tpriPDyxNyMCGSbfD3+1Oa6yDDGnpxFC9Dw=; b=LeUl3XxQv5L1n3x1TiaSBk/BmcE2xpFtryNc2ItkiBpbCiV9e9d+CzUVO7GolFYWlL 7Zrx+GrxgC16l9N/tPo79wXhwWUPKiqotgq3HjZvVO2EMHfZ/wHgVeAuYajHxWcfAFCz qexLLBvJzYR1h8udStZQmm9XWeZkSgD9jILoh9Y2qocrTycx5OpzJLakXNtY3j/EBKl+ Kp1WlFES6TfVAYwfgiX4n37ObMw07PX3p6fRGwcUom1El4oaDqqjpdKgtYYwtqwU1Wy6 qzbKKn825DShFluF9G/36EBddLj+752sq05MVVzGn8iCRJ6HoeqTpRmIe7crGXD2q4p1 EpXQ== X-Gm-Message-State: AOJu0YyVJazdfzGroqLrQ9f9IViFsDx+YGCd3uMPDNKv3YYSYSbEyXLI Q3ANjIEevEI28+8Vppbb8aDtT4HdPBx4Vy8WNIo/0+prK/1rLFMdzFtOdS6nQbXts63pyDM+4wK 9 X-Google-Smtp-Source: AGHT+IGbarReVcIseTtrWVGt5DsLJTc3HofctKlcKh62g7M+A86hpOYiju+giKRxbsLJxNh3bBiAbg== X-Received: by 2002:a17:906:f58e:b0:a9a:2afc:e4cc with SMTP id a640c23a62f3a-a9de61a128amr3626458166b.58.1730883973693; Wed, 06 Nov 2024 01:06:13 -0800 (PST) Received: from localhost.localdomain ([2001:b07:6474:ebbf:afb5:f524:6416:8e3]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9eb17f9422sm247781366b.139.2024.11.06.01.06.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2024 01:06:13 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v3 4/8] clk: imx8mm: support spread spectrum clock generation Date: Wed, 6 Nov 2024 09:58:00 +0100 Message-ID: <20241106090549.3684963-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241106090549.3684963-1-dario.binacchi@amarulasolutions.com> References: <20241106090549.3684963-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The patch adds support for spread spectrum clock generation for the audio, video, and DRAM PLLs. Signed-off-by: Dario Binacchi --- Changes in v3: - Use ccm node device drivers/clk/imx/clk-imx8mm.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 0cf53b5b15c8..482e471d086b 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -302,6 +302,7 @@ static int imx8mm_clocks_probe(struct platform_device *= pdev) struct device_node *np =3D dev->of_node; struct device_node *anatop_np; void __iomem *base, *anatop_base; + struct imx_pll14xx_ssc pll1443x_ssc; int ret; =20 clk_hw_data =3D kzalloc(struct_size(clk_hw_data, hws, @@ -335,10 +336,14 @@ static int imx8mm_clocks_probe(struct platform_device= *pdev) hws[IMX8MM_ARM_PLL_REF_SEL] =3D imx_clk_hw_mux("arm_pll_ref_sel", anatop_= base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MM_SYS_PLL3_REF_SEL] =3D imx_clk_hw_mux("sys_pll3_ref_sel", anato= p_base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); =20 - hws[IMX8MM_AUDIO_PLL1] =3D imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_r= ef_sel", anatop_base, &imx_1443x_pll); - hws[IMX8MM_AUDIO_PLL2] =3D imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_r= ef_sel", anatop_base + 0x14, &imx_1443x_pll); - hws[IMX8MM_VIDEO_PLL1] =3D imx_clk_hw_pll14xx("video_pll1", "video_pll1_r= ef_sel", anatop_base + 0x28, &imx_1443x_pll); - hws[IMX8MM_DRAM_PLL] =3D imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel= ", anatop_base + 0x50, &imx_1443x_dram_pll); + imx_clk_pll14xx_get_ssc_conf(np, IMX8MM_AUDIO_PLL1, &pll1443x_ssc); + hws[IMX8MM_AUDIO_PLL1] =3D imx_clk_hw_pll14xx_ssc("audio_pll1", "audio_pl= l1_ref_sel", anatop_base, &imx_1443x_pll, &pll1443x_ssc); + imx_clk_pll14xx_get_ssc_conf(np, IMX8MM_AUDIO_PLL2, &pll1443x_ssc); + hws[IMX8MM_AUDIO_PLL2] =3D imx_clk_hw_pll14xx_ssc("audio_pll2", "audio_pl= l2_ref_sel", anatop_base + 0x14, &imx_1443x_pll, &pll1443x_ssc); + imx_clk_pll14xx_get_ssc_conf(np, IMX8MM_VIDEO_PLL1, &pll1443x_ssc); + hws[IMX8MM_VIDEO_PLL1] =3D imx_clk_hw_pll14xx_ssc("video_pll1", "video_pl= l1_ref_sel", anatop_base + 0x28, &imx_1443x_pll, &pll1443x_ssc); + imx_clk_pll14xx_get_ssc_conf(np, IMX8MM_DRAM_PLL, &pll1443x_ssc); + hws[IMX8MM_DRAM_PLL] =3D imx_clk_hw_pll14xx_ssc("dram_pll", "dram_pll_ref= _sel", anatop_base + 0x50, &imx_1443x_dram_pll, &pll1443x_ssc); hws[IMX8MM_GPU_PLL] =3D imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", = anatop_base + 0x64, &imx_1416x_pll); hws[IMX8MM_VPU_PLL] =3D imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", = anatop_base + 0x74, &imx_1416x_pll); hws[IMX8MM_ARM_PLL] =3D imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", = anatop_base + 0x84, &imx_1416x_pll); --=20 2.43.0