From nobody Sun Nov 24 08:41:14 2024 Received: from mail-ej1-f46.google.com (mail-ej1-f46.google.com [209.85.218.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A159E1DDA3C for ; Wed, 6 Nov 2024 09:06:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730883973; cv=none; b=kFRcdYq0dKAT2AOr++RW/ZAobyUmuQ7FRNHOxgpkGAKd7cxxdkMNEAJUhYKG+mKSdxYFy6yqcx5kmCeqgwdaG7Vp1OyW3Vk7PSz2HoVVVet3z5QzK1bP6MUmg+ovY7elsZjbJ2XCBWB+Psi++g3qAEW8Nq2f8FD5ABaXYRL/erk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730883973; c=relaxed/simple; bh=zSVT1VPPzMwphatbGwv5SHnw+nnYzwL4oiYG0Aw/df8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PiReJBQLpnvm7iCsy/z2AtsD1d9hcpB8JExYyQgj3jcspi4+cHPKxVS8zew43k1CFMPOCeKUzokJaxpslVEzGt7n8sp7ck72DHMpZ9KtKvvfZtXX24xEnQRsp1E5uXVRhBgl+HdEj7k5fzEHw+zcrob+ZWEnrzHbmw+WTSu4Ei8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=C7KL3aUV; arc=none smtp.client-ip=209.85.218.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="C7KL3aUV" Received: by mail-ej1-f46.google.com with SMTP id a640c23a62f3a-a9eaaab29bcso425217166b.2 for ; Wed, 06 Nov 2024 01:06:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1730883970; x=1731488770; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QrNsJPPKHO5Lk6rFyymH1MtDjL//mpL7mQleFPtlyis=; b=C7KL3aUVanbJnZ6jZMV/2blywshqT8OscQIzN5c4yCiDVTP4FULpMU6mHXJLf9q+t6 CV+07NXh7NUViKoiEZ5eh06YiYr+mPKEHoZVKo7VwvjuukK2g3FWbbAjROpEhlyxV6pF 4BokP7Pkztjtey7BQoDKJUyy7ZuuQF91eLmyA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730883970; x=1731488770; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QrNsJPPKHO5Lk6rFyymH1MtDjL//mpL7mQleFPtlyis=; b=lwYdJepYt7txdZRtfZxpd7Elw/66ZFUpFrDKzSBJOp9Fc7Kd3hsuGvFjbI5Vls48+t G6PDQ5iIw1MdmvGNn7zsK78K2cfUfYdCaD/a80noEIvw5JXQVecIlYd/npXYWTI8VjL6 s3n3PiVtHSOuFtugq9fGrAuQTgQXzmp1jI4AW6wm9/S59OL24z/0Y/Fiwg0PfrKLcP4+ xzWsokVTZ588GPToYVPOl4p45R2FdlBV5s+ZI8BkrtSeQ8xdjugqn3AZBXIX4sNeMDRs uuscKJ3JyiI56ufpBoy3DXZPS9Odn7mpPtGpGw6MXpnihQvQm8Bt57tt1CTmF/C0Jf59 Hf/g== X-Gm-Message-State: AOJu0YzRPSBQoh+tmMZnV7G0UBhN6ROltWrD3xSbOVfbtTNe0vraQaY9 3bk2IloUO3d1wfT7Vnx36zaWIEhg6YSNWRvp+eYwiIFfT3+AUshX+Zb8TVGi6mRuY27UczNsFl5 i X-Google-Smtp-Source: AGHT+IEsxqy1QIMoDY4Ou1LJy4yOq+pq9/YaekGJg8fDbyA6VV3xENMscgOLE+Qbj+VEcc4PHGIAOQ== X-Received: by 2002:a17:907:3f9f:b0:a9a:2afc:e4d7 with SMTP id a640c23a62f3a-a9e50b948d0mr2311624866b.44.1730883969647; Wed, 06 Nov 2024 01:06:09 -0800 (PST) Received: from localhost.localdomain ([2001:b07:6474:ebbf:afb5:f524:6416:8e3]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9eb17f9422sm247781366b.139.2024.11.06.01.06.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2024 01:06:09 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , Stephen Boyd , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v3 1/8] dt-bindings: clock: imx8m-clock: support spread spectrum clocking Date: Wed, 6 Nov 2024 09:57:57 +0100 Message-ID: <20241106090549.3684963-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241106090549.3684963-1-dario.binacchi@amarulasolutions.com> References: <20241106090549.3684963-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The patch adds the DT bindings for enabling and tuning spread spectrum clocking generation. Signed-off-by: Dario Binacchi --- Changes in v3: - Added in v3 - The dt-bindings have been moved from fsl,imx8m-anatop.yaml to imx8m-clock.yaml. The anatop device (fsl,imx8m-anatop.yaml) is indeed more or less a syscon, so it represents a memory area accessible by ccm (imx8m-clock.yaml) to setup the PLLs. .../bindings/clock/imx8m-clock.yaml | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml b/Doc= umentation/devicetree/bindings/clock/imx8m-clock.yaml index c643d4a81478..7920393e518e 100644 --- a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml @@ -43,6 +43,40 @@ properties: ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8m= -clock.h for the full list of i.MX8M clock IDs. =20 + fsl,ssc-clocks: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Phandles of the PLL with spread spectrum generation hardware capabil= ity. + minItems: 1 + maxItems: 4 + + fsl,ssc-modfreq-hz: + description: + The values of modulation frequency (Hz unit) of spread spectrum + clocking for each PLL. + minItems: 1 + maxItems: 4 + + fsl,ssc-modrate-percent: + description: + The percentage values of modulation rate of spread spectrum + clocking for each PLL. + minItems: 1 + maxItems: 4 + + fsl,ssc-modmethod: + $ref: /schemas/types.yaml#/definitions/string-array + description: + The modulation techniques of spread spectrum clocking for + each PLL. + minItems: 1 + maxItems: 4 + items: + enum: + - down-spread + - up-spread + - center-spread + required: - compatible - reg @@ -76,6 +110,11 @@ allOf: - const: clk_ext2 - const: clk_ext3 - const: clk_ext4 + fsl,ssc-clocks: false + fsl,ssc-modfreq-hz: false + fsl,ssc-modrate-percent: false + fsl,ssc-modmethod: false + else: properties: clocks: @@ -101,6 +140,8 @@ additionalProperties: false examples: # Clock Control Module node: - | + #include + clock-controller@30380000 { compatible =3D "fsl,imx8mm-ccm"; reg =3D <0x30380000 0x10000>; @@ -109,6 +150,11 @@ examples: <&clk_ext3>, <&clk_ext4>; clock-names =3D "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; + fsl,ssc-clocks =3D <&clk IMX8MM_AUDIO_PLL1>, + <&clk IMX8MM_VIDEO_PLL1>; + fsl,ssc-modfreq-hz =3D <6818>, <2419>; + fsl,ssc-modrate-percent =3D <3>, <7>; + fsl,ssc-modmethod =3D "down-spread", "center-spread"; }; =20 - | --=20 2.43.0 From nobody Sun Nov 24 08:41:14 2024 Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED88D1DDC0B for ; Wed, 6 Nov 2024 09:06:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730883974; cv=none; b=LxF7JXeK+0pdO5p/V8ScFvuD7H7ZGSUrGrY9cewznzkWwszOtikxXm+j4BJvvzq9mbi0mgePPbYPyPsK5EeCfWhh2rd/ZcDjaFjcMf4nkYBFxtYztiHDtA226eh8sSpLR0xD6srSa5GoKSCAbrYzZsCWioh15m+zqddi0SJBk7Y= ARC-Message-Signature: i=1; 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Wed, 06 Nov 2024 01:06:10 -0800 (PST) Received: from localhost.localdomain ([2001:b07:6474:ebbf:afb5:f524:6416:8e3]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9eb17f9422sm247781366b.139.2024.11.06.01.06.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2024 01:06:10 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v3 2/8] clk: imx: pll14xx: support spread spectrum clock generation Date: Wed, 6 Nov 2024 09:57:58 +0100 Message-ID: <20241106090549.3684963-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241106090549.3684963-1-dario.binacchi@amarulasolutions.com> References: <20241106090549.3684963-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch adds support for spread spectrum clock (SSC) generation for the pll14xxx. The addition of the "imx_clk_hw_pll14xx_ssc" macro has minimized the number of changes required to avoid compilation errors following the addition of the SSC setup parameter to the "imx_dev_clk_hw_pll14xx" macro used in the files clk-imx8m{m,n,p}.c. The change to the clk-imx8mp-audiomix.c file prevents the patch from causing a compilation error. Signed-off-by: Dario Binacchi --- (no changes since v1) drivers/clk/imx/clk-imx8mp-audiomix.c | 2 +- drivers/clk/imx/clk-pll14xx.c | 102 +++++++++++++++++++++++++- drivers/clk/imx/clk.h | 24 +++++- 3 files changed, 124 insertions(+), 4 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mp-audiomix.c b/drivers/clk/imx/clk-im= x8mp-audiomix.c index b2cb157703c5..bfcf2975c217 100644 --- a/drivers/clk/imx/clk-imx8mp-audiomix.c +++ b/drivers/clk/imx/clk-imx8mp-audiomix.c @@ -365,7 +365,7 @@ static int clk_imx8mp_audiomix_probe(struct platform_de= vice *pdev) clk_hw_data->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL] =3D hw; =20 hw =3D imx_dev_clk_hw_pll14xx(dev, "sai_pll", "sai_pll_ref_sel", - base + 0x400, &imx_1443x_pll); + base + 0x400, &imx_1443x_pll, NULL); if (IS_ERR(hw)) { ret =3D PTR_ERR(hw); goto err_clk_register; diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index d63564dbb12c..76014e243a57 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -20,6 +20,8 @@ #define GNRL_CTL 0x0 #define DIV_CTL0 0x4 #define DIV_CTL1 0x8 +#define SSCG_CTRL 0xc + #define LOCK_STATUS BIT(31) #define LOCK_SEL_MASK BIT(29) #define CLKE_MASK BIT(11) @@ -31,6 +33,10 @@ #define KDIV_MASK GENMASK(15, 0) #define KDIV_MIN SHRT_MIN #define KDIV_MAX SHRT_MAX +#define SSCG_ENABLE BIT(31) +#define MFREQ_CTL_MASK GENMASK(19, 12) +#define MRAT_CTL_MASK GENMASK(9, 4) +#define SEL_PF_MASK GENMASK(1, 0) =20 #define LOCK_TIMEOUT_US 10000 =20 @@ -40,6 +46,7 @@ struct clk_pll14xx { enum imx_pll14xx_type type; const struct imx_pll14xx_rate_table *rate_table; int rate_count; + struct imx_pll14xx_ssc ssc; }; =20 #define to_clk_pll14xx(_hw) container_of(_hw, struct clk_pll14xx, hw) @@ -347,6 +354,27 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, un= signed long drate, return 0; } =20 +static void clk_pll1443x_set_sscg(struct clk_hw *hw, unsigned long parent_= rate, + unsigned int pdiv, unsigned int mdiv) +{ + struct clk_pll14xx *pll =3D to_clk_pll14xx(hw); + struct imx_pll14xx_ssc *ssc =3D &pll->ssc; + u32 sscg_ctrl =3D readl_relaxed(pll->base + SSCG_CTRL); + + sscg_ctrl &=3D + ~(SSCG_ENABLE | MFREQ_CTL_MASK | MRAT_CTL_MASK | SEL_PF_MASK); + if (ssc->enable) { + u32 mfr =3D parent_rate / (ssc->mod_freq * pdiv * (1 << 5)); + u32 mrr =3D (ssc->mod_rate * mdiv * (1 << 6)) / (100 * mfr); + + sscg_ctrl |=3D SSCG_ENABLE | FIELD_PREP(MFREQ_CTL_MASK, mfr) | + FIELD_PREP(MRAT_CTL_MASK, mrr) | + FIELD_PREP(SEL_PF_MASK, ssc->mod_type); + } + + writel_relaxed(sscg_ctrl, pll->base + SSCG_CTRL); +} + static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) { @@ -368,6 +396,9 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, uns= igned long drate, writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv), pll->base + DIV_CTL1); =20 + if (pll->ssc.enable) + clk_pll1443x_set_sscg(hw, prate, rate.pdiv, rate.mdiv); + return 0; } =20 @@ -408,6 +439,9 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, uns= igned long drate, gnrl_ctl &=3D ~BYPASS_MASK; writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); =20 + if (pll->ssc.enable) + clk_pll1443x_set_sscg(hw, prate, rate.pdiv, rate.mdiv); + return 0; } =20 @@ -487,7 +521,8 @@ static const struct clk_ops clk_pll1443x_ops =3D { =20 struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, const char *parent_name, void __iomem *base, - const struct imx_pll14xx_clk *pll_clk) + const struct imx_pll14xx_clk *pll_clk, + const struct imx_pll14xx_ssc *ssc) { struct clk_pll14xx *pll; struct clk_hw *hw; @@ -525,6 +560,8 @@ struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *de= v, const char *name, pll->type =3D pll_clk->type; pll->rate_table =3D pll_clk->rate_table; pll->rate_count =3D pll_clk->rate_count; + if (ssc) + memcpy(&pll->ssc, ssc, sizeof(pll->ssc)); =20 val =3D readl_relaxed(pll->base + GNRL_CTL); val &=3D ~BYPASS_MASK; @@ -542,3 +579,66 @@ struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *d= ev, const char *name, return hw; } EXPORT_SYMBOL_GPL(imx_dev_clk_hw_pll14xx); + +static enum imx_pll14xx_ssc_mod_type clk_pll14xx_ssc_mode(const char *name, + enum imx_pll14xx_ssc_mod_type def) +{ + int i; + struct { + const char *name; + enum imx_pll14xx_ssc_mod_type id; + } mod_methods[] =3D { + { .name =3D "down-spread", .id =3D IMX_PLL14XX_SSC_DOWN_SPREAD }, + { .name =3D "up-spread", .id =3D IMX_PLL14XX_SSC_UP_SPREAD }, + { .name =3D "center-spread", .id =3D IMX_PLL14XX_SSC_CENTER_SPREAD } + }; + + for (i =3D 0; i < ARRAY_SIZE(mod_methods); i++) { + if (!strcmp(name, mod_methods[i].name)) + return mod_methods[i].id; + } + + return def; +} + +void imx_clk_pll14xx_get_ssc_conf(struct device_node *np, int pll_id, + struct imx_pll14xx_ssc *ssc) +{ + int i, ret, offset, num_clks; + u32 clk_id, clk_cell_size; + const char *s; + + if (!ssc) + return; + + memset(ssc, 0, sizeof(*ssc)); + + num_clks =3D of_count_phandle_with_args(np, "fsl,ssc-clocks", + "#clock-cells"); + if (num_clks <=3D 0) + return; + + ret =3D of_property_read_u32(np, "#clock-cells", &clk_cell_size); + if (ret) + return; + + for (i =3D 0; i < num_clks; i++) { + offset =3D i * clk_cell_size + 1; + of_property_read_u32_index(np, "fsl,ssc-clocks", offset, + &clk_id); + if (clk_id !=3D pll_id) + continue; + + of_property_read_u32_index(np, "fsl,ssc-modfreq-hz", i, + &ssc->mod_freq); + of_property_read_u32_index(np, "fsl,ssc-modrate-percent", i, + &ssc->mod_rate); + if (!of_property_read_string(np, "fsl,ssc-modmethod", &s)) + ssc->mod_type =3D clk_pll14xx_ssc_mode( + s, IMX_PLL14XX_SSC_DOWN_SPREAD); + + ssc->enable =3D true; + break; + } +} +EXPORT_SYMBOL_GPL(imx_clk_pll14xx_get_ssc_conf); diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index aa5202f284f3..8cbc75480569 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -62,6 +62,19 @@ struct imx_pll14xx_rate_table { unsigned int kdiv; }; =20 +enum imx_pll14xx_ssc_mod_type { + IMX_PLL14XX_SSC_DOWN_SPREAD, + IMX_PLL14XX_SSC_UP_SPREAD, + IMX_PLL14XX_SSC_CENTER_SPREAD, +}; + +struct imx_pll14xx_ssc { + bool enable; + unsigned int mod_freq; + unsigned int mod_rate; + enum imx_pll14xx_ssc_mod_type mod_type; +}; + struct imx_pll14xx_clk { enum imx_pll14xx_type type; const struct imx_pll14xx_rate_table *rate_table; @@ -222,11 +235,18 @@ extern struct imx_fracn_gppll_clk imx_fracn_gppll_int= eger; __imx_clk_hw_divider(name, parent, reg, shift, width, flags) =20 #define imx_clk_hw_pll14xx(name, parent_name, base, pll_clk) \ - imx_dev_clk_hw_pll14xx(NULL, name, parent_name, base, pll_clk) + imx_dev_clk_hw_pll14xx(NULL, name, parent_name, base, pll_clk, NULL) + +#define imx_clk_hw_pll14xx_ssc(name, parent_name, base, pll_clk, ssc) \ + imx_dev_clk_hw_pll14xx(NULL, name, parent_name, base, pll_clk, ssc) =20 struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, const char *parent_name, void __iomem *base, - const struct imx_pll14xx_clk *pll_clk); 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Wed, 06 Nov 2024 01:06:12 -0800 (PST) Received: from localhost.localdomain ([2001:b07:6474:ebbf:afb5:f524:6416:8e3]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9eb17f9422sm247781366b.139.2024.11.06.01.06.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2024 01:06:11 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v3 3/8] clk: imx: imx8mm: distinguish between ccm and anatop references Date: Wed, 6 Nov 2024 09:57:59 +0100 Message-ID: <20241106090549.3684963-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241106090549.3684963-1-dario.binacchi@amarulasolutions.com> References: <20241106090549.3684963-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The patch distinguishes between the references to the ccm node (np, base) and those to the anatop node (anatop_np, anatop_base). In this way, the code improves in readability and is less prone to errors. The patch is also preparatory for future developments. Signed-off-by: Dario Binacchi --- Changes in v3: - Added in version 3 drivers/clk/imx/clk-imx8mm.c | 94 ++++++++++++++++++------------------ 1 file changed, 47 insertions(+), 47 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 342049b847b9..0cf53b5b15c8 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -300,7 +300,8 @@ static int imx8mm_clocks_probe(struct platform_device *= pdev) { struct device *dev =3D &pdev->dev; struct device_node *np =3D dev->of_node; - void __iomem *base; + struct device_node *anatop_np; + void __iomem *base, *anatop_base; int ret; =20 clk_hw_data =3D kzalloc(struct_size(clk_hw_data, hws, @@ -319,54 +320,54 @@ static int imx8mm_clocks_probe(struct platform_device= *pdev) hws[IMX8MM_CLK_EXT3] =3D imx_get_clk_hw_by_name(np, "clk_ext3"); hws[IMX8MM_CLK_EXT4] =3D imx_get_clk_hw_by_name(np, "clk_ext4"); =20 - np =3D of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop"); - base =3D of_iomap(np, 0); - of_node_put(np); - if (WARN_ON(!base)) + anatop_np =3D of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop"); + anatop_base =3D of_iomap(anatop_np, 0); + of_node_put(anatop_np); + if (WARN_ON(!anatop_base)) return -ENOMEM; =20 - hws[IMX8MM_AUDIO_PLL1_REF_SEL] =3D imx_clk_hw_mux("audio_pll1_ref_sel", b= ase + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MM_AUDIO_PLL2_REF_SEL] =3D imx_clk_hw_mux("audio_pll2_ref_sel", b= ase + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MM_VIDEO_PLL1_REF_SEL] =3D imx_clk_hw_mux("video_pll1_ref_sel", b= ase + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MM_DRAM_PLL_REF_SEL] =3D imx_clk_hw_mux("dram_pll_ref_sel", base = + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MM_GPU_PLL_REF_SEL] =3D imx_clk_hw_mux("gpu_pll_ref_sel", base + = 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MM_VPU_PLL_REF_SEL] =3D imx_clk_hw_mux("vpu_pll_ref_sel", base + = 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MM_ARM_PLL_REF_SEL] =3D imx_clk_hw_mux("arm_pll_ref_sel", base + = 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MM_SYS_PLL3_REF_SEL] =3D imx_clk_hw_mux("sys_pll3_ref_sel", base = + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - - hws[IMX8MM_AUDIO_PLL1] =3D imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_r= ef_sel", base, &imx_1443x_pll); - hws[IMX8MM_AUDIO_PLL2] =3D imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_r= ef_sel", base + 0x14, &imx_1443x_pll); - hws[IMX8MM_VIDEO_PLL1] =3D imx_clk_hw_pll14xx("video_pll1", "video_pll1_r= ef_sel", base + 0x28, &imx_1443x_pll); - hws[IMX8MM_DRAM_PLL] =3D imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel= ", base + 0x50, &imx_1443x_dram_pll); - hws[IMX8MM_GPU_PLL] =3D imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", = base + 0x64, &imx_1416x_pll); - hws[IMX8MM_VPU_PLL] =3D imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", = base + 0x74, &imx_1416x_pll); - hws[IMX8MM_ARM_PLL] =3D imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", = base + 0x84, &imx_1416x_pll); + hws[IMX8MM_AUDIO_PLL1_REF_SEL] =3D imx_clk_hw_mux("audio_pll1_ref_sel", a= natop_base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MM_AUDIO_PLL2_REF_SEL] =3D imx_clk_hw_mux("audio_pll2_ref_sel", a= natop_base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MM_VIDEO_PLL1_REF_SEL] =3D imx_clk_hw_mux("video_pll1_ref_sel", a= natop_base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MM_DRAM_PLL_REF_SEL] =3D imx_clk_hw_mux("dram_pll_ref_sel", anato= p_base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MM_GPU_PLL_REF_SEL] =3D imx_clk_hw_mux("gpu_pll_ref_sel", anatop_= base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MM_VPU_PLL_REF_SEL] =3D imx_clk_hw_mux("vpu_pll_ref_sel", anatop_= base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MM_ARM_PLL_REF_SEL] =3D imx_clk_hw_mux("arm_pll_ref_sel", anatop_= base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MM_SYS_PLL3_REF_SEL] =3D imx_clk_hw_mux("sys_pll3_ref_sel", anato= p_base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + + hws[IMX8MM_AUDIO_PLL1] =3D imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_r= ef_sel", anatop_base, &imx_1443x_pll); + hws[IMX8MM_AUDIO_PLL2] =3D imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_r= ef_sel", anatop_base + 0x14, &imx_1443x_pll); + hws[IMX8MM_VIDEO_PLL1] =3D imx_clk_hw_pll14xx("video_pll1", "video_pll1_r= ef_sel", anatop_base + 0x28, &imx_1443x_pll); + hws[IMX8MM_DRAM_PLL] =3D imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel= ", anatop_base + 0x50, &imx_1443x_dram_pll); + hws[IMX8MM_GPU_PLL] =3D imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", = anatop_base + 0x64, &imx_1416x_pll); + hws[IMX8MM_VPU_PLL] =3D imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", = anatop_base + 0x74, &imx_1416x_pll); + hws[IMX8MM_ARM_PLL] =3D imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", = anatop_base + 0x84, &imx_1416x_pll); hws[IMX8MM_SYS_PLL1] =3D imx_clk_hw_fixed("sys_pll1", 800000000); hws[IMX8MM_SYS_PLL2] =3D imx_clk_hw_fixed("sys_pll2", 1000000000); - hws[IMX8MM_SYS_PLL3] =3D imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel= ", base + 0x114, &imx_1416x_pll); + hws[IMX8MM_SYS_PLL3] =3D imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel= ", anatop_base + 0x114, &imx_1416x_pll); =20 /* PLL bypass out */ - hws[IMX8MM_AUDIO_PLL1_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll1_bypass= ", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels),= CLK_SET_RATE_PARENT); - hws[IMX8MM_AUDIO_PLL2_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll2_bypass= ", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass= _sels), CLK_SET_RATE_PARENT); - hws[IMX8MM_VIDEO_PLL1_BYPASS] =3D imx_clk_hw_mux_flags("video_pll1_bypass= ", base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass= _sels), CLK_SET_RATE_PARENT); - hws[IMX8MM_DRAM_PLL_BYPASS] =3D imx_clk_hw_mux_flags("dram_pll_bypass", b= ase + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), = CLK_SET_RATE_PARENT); - hws[IMX8MM_GPU_PLL_BYPASS] =3D imx_clk_hw_mux_flags("gpu_pll_bypass", bas= e + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_= SET_RATE_PARENT); - hws[IMX8MM_VPU_PLL_BYPASS] =3D imx_clk_hw_mux_flags("vpu_pll_bypass", bas= e + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_= SET_RATE_PARENT); - hws[IMX8MM_ARM_PLL_BYPASS] =3D imx_clk_hw_mux_flags("arm_pll_bypass", bas= e + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_= SET_RATE_PARENT); - hws[IMX8MM_SYS_PLL3_BYPASS] =3D imx_clk_hw_mux_flags("sys_pll3_bypass", b= ase + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels),= CLK_SET_RATE_PARENT); + hws[IMX8MM_AUDIO_PLL1_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll1_bypass= ", anatop_base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass= _sels), CLK_SET_RATE_PARENT); + hws[IMX8MM_AUDIO_PLL2_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll2_bypass= ", anatop_base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2= _bypass_sels), CLK_SET_RATE_PARENT); + hws[IMX8MM_VIDEO_PLL1_BYPASS] =3D imx_clk_hw_mux_flags("video_pll1_bypass= ", anatop_base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1= _bypass_sels), CLK_SET_RATE_PARENT); + hws[IMX8MM_DRAM_PLL_BYPASS] =3D imx_clk_hw_mux_flags("dram_pll_bypass", a= natop_base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_= sels), CLK_SET_RATE_PARENT); + hws[IMX8MM_GPU_PLL_BYPASS] =3D imx_clk_hw_mux_flags("gpu_pll_bypass", ana= top_base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels= ), CLK_SET_RATE_PARENT); + hws[IMX8MM_VPU_PLL_BYPASS] =3D imx_clk_hw_mux_flags("vpu_pll_bypass", ana= top_base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels= ), CLK_SET_RATE_PARENT); + hws[IMX8MM_ARM_PLL_BYPASS] =3D imx_clk_hw_mux_flags("arm_pll_bypass", ana= top_base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels= ), CLK_SET_RATE_PARENT); + hws[IMX8MM_SYS_PLL3_BYPASS] =3D imx_clk_hw_mux_flags("sys_pll3_bypass", a= natop_base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass= _sels), CLK_SET_RATE_PARENT); =20 /* PLL out gate */ - hws[IMX8MM_AUDIO_PLL1_OUT] =3D imx_clk_hw_gate("audio_pll1_out", "audio_p= ll1_bypass", base, 13); - hws[IMX8MM_AUDIO_PLL2_OUT] =3D imx_clk_hw_gate("audio_pll2_out", "audio_p= ll2_bypass", base + 0x14, 13); - hws[IMX8MM_VIDEO_PLL1_OUT] =3D imx_clk_hw_gate("video_pll1_out", "video_p= ll1_bypass", base + 0x28, 13); - hws[IMX8MM_DRAM_PLL_OUT] =3D imx_clk_hw_gate("dram_pll_out", "dram_pll_by= pass", base + 0x50, 13); - hws[IMX8MM_GPU_PLL_OUT] =3D imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypas= s", base + 0x64, 11); - hws[IMX8MM_VPU_PLL_OUT] =3D imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypas= s", base + 0x74, 11); - hws[IMX8MM_ARM_PLL_OUT] =3D imx_clk_hw_gate("arm_pll_out", "arm_pll_bypas= s", base + 0x84, 11); - hws[IMX8MM_SYS_PLL3_OUT] =3D imx_clk_hw_gate("sys_pll3_out", "sys_pll3_by= pass", base + 0x114, 11); + hws[IMX8MM_AUDIO_PLL1_OUT] =3D imx_clk_hw_gate("audio_pll1_out", "audio_p= ll1_bypass", anatop_base, 13); + hws[IMX8MM_AUDIO_PLL2_OUT] =3D imx_clk_hw_gate("audio_pll2_out", "audio_p= ll2_bypass", anatop_base + 0x14, 13); + hws[IMX8MM_VIDEO_PLL1_OUT] =3D imx_clk_hw_gate("video_pll1_out", "video_p= ll1_bypass", anatop_base + 0x28, 13); + hws[IMX8MM_DRAM_PLL_OUT] =3D imx_clk_hw_gate("dram_pll_out", "dram_pll_by= pass", anatop_base + 0x50, 13); + hws[IMX8MM_GPU_PLL_OUT] =3D imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypas= s", anatop_base + 0x64, 11); + hws[IMX8MM_VPU_PLL_OUT] =3D imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypas= s", anatop_base + 0x74, 11); + hws[IMX8MM_ARM_PLL_OUT] =3D imx_clk_hw_gate("arm_pll_out", "arm_pll_bypas= s", anatop_base + 0x84, 11); + hws[IMX8MM_SYS_PLL3_OUT] =3D imx_clk_hw_gate("sys_pll3_out", "sys_pll3_by= pass", anatop_base + 0x114, 11); =20 /* SYS PLL1 fixed output */ - hws[IMX8MM_SYS_PLL1_OUT] =3D imx_clk_hw_gate("sys_pll1_out", "sys_pll1", = base + 0x94, 11); + hws[IMX8MM_SYS_PLL1_OUT] =3D imx_clk_hw_gate("sys_pll1_out", "sys_pll1", = anatop_base + 0x94, 11); =20 hws[IMX8MM_SYS_PLL1_40M] =3D imx_clk_hw_fixed_factor("sys_pll1_40m", "sys= _pll1_out", 1, 20); hws[IMX8MM_SYS_PLL1_80M] =3D imx_clk_hw_fixed_factor("sys_pll1_80m", "sys= _pll1_out", 1, 10); @@ -379,7 +380,7 @@ static int imx8mm_clocks_probe(struct platform_device *= pdev) hws[IMX8MM_SYS_PLL1_800M] =3D imx_clk_hw_fixed_factor("sys_pll1_800m", "s= ys_pll1_out", 1, 1); =20 /* SYS PLL2 fixed output */ - hws[IMX8MM_SYS_PLL2_OUT] =3D imx_clk_hw_gate("sys_pll2_out", "sys_pll2", = base + 0x104, 11); + hws[IMX8MM_SYS_PLL2_OUT] =3D imx_clk_hw_gate("sys_pll2_out", "sys_pll2", = anatop_base + 0x104, 11); hws[IMX8MM_SYS_PLL2_50M] =3D imx_clk_hw_fixed_factor("sys_pll2_50m", "sys= _pll2_out", 1, 20); hws[IMX8MM_SYS_PLL2_100M] =3D imx_clk_hw_fixed_factor("sys_pll2_100m", "s= ys_pll2_out", 1, 10); hws[IMX8MM_SYS_PLL2_125M] =3D imx_clk_hw_fixed_factor("sys_pll2_125m", "s= ys_pll2_out", 1, 8); @@ -390,14 +391,13 @@ static int imx8mm_clocks_probe(struct platform_device= *pdev) hws[IMX8MM_SYS_PLL2_500M] =3D imx_clk_hw_fixed_factor("sys_pll2_500m", "s= ys_pll2_out", 1, 2); hws[IMX8MM_SYS_PLL2_1000M] =3D imx_clk_hw_fixed_factor("sys_pll2_1000m", = "sys_pll2_out", 1, 1); =20 - hws[IMX8MM_CLK_CLKOUT1_SEL] =3D imx_clk_hw_mux2("clkout1_sel", base + 0x1= 28, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels)); - hws[IMX8MM_CLK_CLKOUT1_DIV] =3D imx_clk_hw_divider("clkout1_div", "clkout= 1_sel", base + 0x128, 0, 4); - hws[IMX8MM_CLK_CLKOUT1] =3D imx_clk_hw_gate("clkout1", "clkout1_div", bas= e + 0x128, 8); - hws[IMX8MM_CLK_CLKOUT2_SEL] =3D imx_clk_hw_mux2("clkout2_sel", base + 0x1= 28, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels)); - hws[IMX8MM_CLK_CLKOUT2_DIV] =3D imx_clk_hw_divider("clkout2_div", "clkout= 2_sel", base + 0x128, 16, 4); - hws[IMX8MM_CLK_CLKOUT2] =3D imx_clk_hw_gate("clkout2", "clkout2_div", bas= e + 0x128, 24); + hws[IMX8MM_CLK_CLKOUT1_SEL] =3D imx_clk_hw_mux2("clkout1_sel", anatop_bas= e + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels)); + hws[IMX8MM_CLK_CLKOUT1_DIV] =3D imx_clk_hw_divider("clkout1_div", "clkout= 1_sel", anatop_base + 0x128, 0, 4); + hws[IMX8MM_CLK_CLKOUT1] =3D imx_clk_hw_gate("clkout1", "clkout1_div", ana= top_base + 0x128, 8); + hws[IMX8MM_CLK_CLKOUT2_SEL] =3D imx_clk_hw_mux2("clkout2_sel", anatop_bas= e + 0x128, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels)); + hws[IMX8MM_CLK_CLKOUT2_DIV] =3D imx_clk_hw_divider("clkout2_div", "clkout= 2_sel", anatop_base + 0x128, 16, 4); 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Wed, 06 Nov 2024 01:06:13 -0800 (PST) Received: from localhost.localdomain ([2001:b07:6474:ebbf:afb5:f524:6416:8e3]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9eb17f9422sm247781366b.139.2024.11.06.01.06.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2024 01:06:13 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v3 4/8] clk: imx8mm: support spread spectrum clock generation Date: Wed, 6 Nov 2024 09:58:00 +0100 Message-ID: <20241106090549.3684963-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241106090549.3684963-1-dario.binacchi@amarulasolutions.com> References: <20241106090549.3684963-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The patch adds support for spread spectrum clock generation for the audio, video, and DRAM PLLs. Signed-off-by: Dario Binacchi --- Changes in v3: - Use ccm node device drivers/clk/imx/clk-imx8mm.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 0cf53b5b15c8..482e471d086b 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -302,6 +302,7 @@ static int imx8mm_clocks_probe(struct platform_device *= pdev) struct device_node *np =3D dev->of_node; struct device_node *anatop_np; void __iomem *base, *anatop_base; + struct imx_pll14xx_ssc pll1443x_ssc; int ret; =20 clk_hw_data =3D kzalloc(struct_size(clk_hw_data, hws, @@ -335,10 +336,14 @@ static int imx8mm_clocks_probe(struct platform_device= *pdev) hws[IMX8MM_ARM_PLL_REF_SEL] =3D imx_clk_hw_mux("arm_pll_ref_sel", anatop_= base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MM_SYS_PLL3_REF_SEL] =3D imx_clk_hw_mux("sys_pll3_ref_sel", anato= p_base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); =20 - hws[IMX8MM_AUDIO_PLL1] =3D imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_r= ef_sel", anatop_base, &imx_1443x_pll); - hws[IMX8MM_AUDIO_PLL2] =3D imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_r= ef_sel", anatop_base + 0x14, &imx_1443x_pll); - hws[IMX8MM_VIDEO_PLL1] =3D imx_clk_hw_pll14xx("video_pll1", "video_pll1_r= ef_sel", anatop_base + 0x28, &imx_1443x_pll); - hws[IMX8MM_DRAM_PLL] =3D imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel= ", anatop_base + 0x50, &imx_1443x_dram_pll); + imx_clk_pll14xx_get_ssc_conf(np, IMX8MM_AUDIO_PLL1, &pll1443x_ssc); + hws[IMX8MM_AUDIO_PLL1] =3D imx_clk_hw_pll14xx_ssc("audio_pll1", "audio_pl= l1_ref_sel", anatop_base, &imx_1443x_pll, &pll1443x_ssc); + imx_clk_pll14xx_get_ssc_conf(np, IMX8MM_AUDIO_PLL2, &pll1443x_ssc); + hws[IMX8MM_AUDIO_PLL2] =3D imx_clk_hw_pll14xx_ssc("audio_pll2", "audio_pl= l2_ref_sel", anatop_base + 0x14, &imx_1443x_pll, &pll1443x_ssc); + imx_clk_pll14xx_get_ssc_conf(np, IMX8MM_VIDEO_PLL1, &pll1443x_ssc); + hws[IMX8MM_VIDEO_PLL1] =3D imx_clk_hw_pll14xx_ssc("video_pll1", "video_pl= l1_ref_sel", anatop_base + 0x28, &imx_1443x_pll, &pll1443x_ssc); + imx_clk_pll14xx_get_ssc_conf(np, IMX8MM_DRAM_PLL, &pll1443x_ssc); + hws[IMX8MM_DRAM_PLL] =3D imx_clk_hw_pll14xx_ssc("dram_pll", "dram_pll_ref= _sel", anatop_base + 0x50, &imx_1443x_dram_pll, &pll1443x_ssc); hws[IMX8MM_GPU_PLL] =3D imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", = anatop_base + 0x64, &imx_1416x_pll); hws[IMX8MM_VPU_PLL] =3D imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", = anatop_base + 0x74, &imx_1416x_pll); hws[IMX8MM_ARM_PLL] =3D imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", = anatop_base + 0x84, &imx_1416x_pll); --=20 2.43.0 From nobody Sun Nov 24 08:41:14 2024 Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A3761DEFE8 for ; Wed, 6 Nov 2024 09:06:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.54 ARC-Seal: i=1; a=rsa-sha256; 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Wed, 06 Nov 2024 01:06:15 -0800 (PST) Received: from localhost.localdomain ([2001:b07:6474:ebbf:afb5:f524:6416:8e3]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9eb17f9422sm247781366b.139.2024.11.06.01.06.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2024 01:06:14 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v3 5/8] clk: imx: imx8mn: distinguish between ccm and anatop references Date: Wed, 6 Nov 2024 09:58:01 +0100 Message-ID: <20241106090549.3684963-6-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241106090549.3684963-1-dario.binacchi@amarulasolutions.com> References: <20241106090549.3684963-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The patch distinguishes between the references to the ccm node (np, base) and those to the anatop node (anatop_np, anatop_base). In this way, the code improves in readability and is less prone to errors. The patch is also preparatory for future developments. Signed-off-by: Dario Binacchi --- Changes in v3: - Added in version 3 drivers/clk/imx/clk-imx8mn.c | 96 ++++++++++++++++++------------------ 1 file changed, 48 insertions(+), 48 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index ab77e148e70c..feefc9ef4f51 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -320,7 +320,8 @@ static int imx8mn_clocks_probe(struct platform_device *= pdev) { struct device *dev =3D &pdev->dev; struct device_node *np =3D dev->of_node; - void __iomem *base; + struct device_node *anatop_np; + void __iomem *base, *anatop_base; int ret; =20 clk_hw_data =3D devm_kzalloc(dev, struct_size(clk_hw_data, hws, @@ -339,56 +340,56 @@ static int imx8mn_clocks_probe(struct platform_device= *pdev) hws[IMX8MN_CLK_EXT3] =3D imx_get_clk_hw_by_name(np, "clk_ext3"); hws[IMX8MN_CLK_EXT4] =3D imx_get_clk_hw_by_name(np, "clk_ext4"); =20 - np =3D of_find_compatible_node(NULL, NULL, "fsl,imx8mn-anatop"); - base =3D devm_of_iomap(dev, np, 0, NULL); - of_node_put(np); - if (WARN_ON(IS_ERR(base))) { - ret =3D PTR_ERR(base); + anatop_np =3D of_find_compatible_node(NULL, NULL, "fsl,imx8mn-anatop"); + anatop_base =3D devm_of_iomap(dev, anatop_np, 0, NULL); + of_node_put(anatop_np); + if (WARN_ON(IS_ERR(anatop_base))) { + ret =3D PTR_ERR(anatop_base); goto unregister_hws; } =20 - hws[IMX8MN_AUDIO_PLL1_REF_SEL] =3D imx_clk_hw_mux("audio_pll1_ref_sel", b= ase + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_AUDIO_PLL2_REF_SEL] =3D imx_clk_hw_mux("audio_pll2_ref_sel", b= ase + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_VIDEO_PLL_REF_SEL] =3D imx_clk_hw_mux("video_pll_ref_sel", bas= e + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_DRAM_PLL_REF_SEL] =3D imx_clk_hw_mux("dram_pll_ref_sel", base = + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_GPU_PLL_REF_SEL] =3D imx_clk_hw_mux("gpu_pll_ref_sel", base + = 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_M7_ALT_PLL_REF_SEL] =3D imx_clk_hw_mux("m7_alt_pll_ref_sel", b= ase + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_ARM_PLL_REF_SEL] =3D imx_clk_hw_mux("arm_pll_ref_sel", base + = 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MN_SYS_PLL3_REF_SEL] =3D imx_clk_hw_mux("sys_pll3_ref_sel", base = + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - - hws[IMX8MN_AUDIO_PLL1] =3D imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_r= ef_sel", base, &imx_1443x_pll); - hws[IMX8MN_AUDIO_PLL2] =3D imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_r= ef_sel", base + 0x14, &imx_1443x_pll); - hws[IMX8MN_VIDEO_PLL] =3D imx_clk_hw_pll14xx("video_pll", "video_pll_ref_= sel", base + 0x28, &imx_1443x_pll); - hws[IMX8MN_DRAM_PLL] =3D imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel= ", base + 0x50, &imx_1443x_dram_pll); - hws[IMX8MN_GPU_PLL] =3D imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", = base + 0x64, &imx_1416x_pll); - hws[IMX8MN_M7_ALT_PLL] =3D imx_clk_hw_pll14xx("m7_alt_pll", "m7_alt_pll_r= ef_sel", base + 0x74, &imx_1416x_pll); - hws[IMX8MN_ARM_PLL] =3D imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", = base + 0x84, &imx_1416x_pll); + hws[IMX8MN_AUDIO_PLL1_REF_SEL] =3D imx_clk_hw_mux("audio_pll1_ref_sel", a= natop_base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_AUDIO_PLL2_REF_SEL] =3D imx_clk_hw_mux("audio_pll2_ref_sel", a= natop_base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_VIDEO_PLL_REF_SEL] =3D imx_clk_hw_mux("video_pll_ref_sel", ana= top_base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_DRAM_PLL_REF_SEL] =3D imx_clk_hw_mux("dram_pll_ref_sel", anato= p_base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_GPU_PLL_REF_SEL] =3D imx_clk_hw_mux("gpu_pll_ref_sel", anatop_= base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_M7_ALT_PLL_REF_SEL] =3D imx_clk_hw_mux("m7_alt_pll_ref_sel", a= natop_base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_ARM_PLL_REF_SEL] =3D imx_clk_hw_mux("arm_pll_ref_sel", anatop_= base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MN_SYS_PLL3_REF_SEL] =3D imx_clk_hw_mux("sys_pll3_ref_sel", anato= p_base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + + hws[IMX8MN_AUDIO_PLL1] =3D imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_r= ef_sel", anatop_base, &imx_1443x_pll); + hws[IMX8MN_AUDIO_PLL2] =3D imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_r= ef_sel", anatop_base + 0x14, &imx_1443x_pll); + hws[IMX8MN_VIDEO_PLL] =3D imx_clk_hw_pll14xx("video_pll", "video_pll_ref_= sel", anatop_base + 0x28, &imx_1443x_pll); + hws[IMX8MN_DRAM_PLL] =3D imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel= ", anatop_base + 0x50, &imx_1443x_dram_pll); + hws[IMX8MN_GPU_PLL] =3D imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", = anatop_base + 0x64, &imx_1416x_pll); + hws[IMX8MN_M7_ALT_PLL] =3D imx_clk_hw_pll14xx("m7_alt_pll", "m7_alt_pll_r= ef_sel", anatop_base + 0x74, &imx_1416x_pll); + hws[IMX8MN_ARM_PLL] =3D imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", = anatop_base + 0x84, &imx_1416x_pll); hws[IMX8MN_SYS_PLL1] =3D imx_clk_hw_fixed("sys_pll1", 800000000); hws[IMX8MN_SYS_PLL2] =3D imx_clk_hw_fixed("sys_pll2", 1000000000); - hws[IMX8MN_SYS_PLL3] =3D imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel= ", base + 0x114, &imx_1416x_pll); + hws[IMX8MN_SYS_PLL3] =3D imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel= ", anatop_base + 0x114, &imx_1416x_pll); =20 /* PLL bypass out */ - hws[IMX8MN_AUDIO_PLL1_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll1_bypass= ", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels),= CLK_SET_RATE_PARENT); - hws[IMX8MN_AUDIO_PLL2_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll2_bypass= ", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass= _sels), CLK_SET_RATE_PARENT); - hws[IMX8MN_VIDEO_PLL_BYPASS] =3D imx_clk_hw_mux_flags("video_pll_bypass",= base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sel= s), CLK_SET_RATE_PARENT); - hws[IMX8MN_DRAM_PLL_BYPASS] =3D imx_clk_hw_mux_flags("dram_pll_bypass", b= ase + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), = CLK_SET_RATE_PARENT); - hws[IMX8MN_GPU_PLL_BYPASS] =3D imx_clk_hw_mux_flags("gpu_pll_bypass", bas= e + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_= SET_RATE_PARENT); - hws[IMX8MN_M7_ALT_PLL_BYPASS] =3D imx_clk_hw_mux_flags("m7_alt_pll_bypass= ", base + 0x74, 28, 1, m7_alt_pll_bypass_sels, ARRAY_SIZE(m7_alt_pll_bypass= _sels), CLK_SET_RATE_PARENT); - hws[IMX8MN_ARM_PLL_BYPASS] =3D imx_clk_hw_mux_flags("arm_pll_bypass", bas= e + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_= SET_RATE_PARENT); - hws[IMX8MN_SYS_PLL3_BYPASS] =3D imx_clk_hw_mux_flags("sys_pll3_bypass", b= ase + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels),= CLK_SET_RATE_PARENT); + hws[IMX8MN_AUDIO_PLL1_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll1_bypass= ", anatop_base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass= _sels), CLK_SET_RATE_PARENT); + hws[IMX8MN_AUDIO_PLL2_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll2_bypass= ", anatop_base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2= _bypass_sels), CLK_SET_RATE_PARENT); + hws[IMX8MN_VIDEO_PLL_BYPASS] =3D imx_clk_hw_mux_flags("video_pll_bypass",= anatop_base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_byp= ass_sels), CLK_SET_RATE_PARENT); + hws[IMX8MN_DRAM_PLL_BYPASS] =3D imx_clk_hw_mux_flags("dram_pll_bypass", a= natop_base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_= sels), CLK_SET_RATE_PARENT); + hws[IMX8MN_GPU_PLL_BYPASS] =3D imx_clk_hw_mux_flags("gpu_pll_bypass", ana= top_base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels= ), CLK_SET_RATE_PARENT); + hws[IMX8MN_M7_ALT_PLL_BYPASS] =3D imx_clk_hw_mux_flags("m7_alt_pll_bypass= ", anatop_base + 0x74, 28, 1, m7_alt_pll_bypass_sels, ARRAY_SIZE(m7_alt_pll= _bypass_sels), CLK_SET_RATE_PARENT); + hws[IMX8MN_ARM_PLL_BYPASS] =3D imx_clk_hw_mux_flags("arm_pll_bypass", ana= top_base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels= ), CLK_SET_RATE_PARENT); + hws[IMX8MN_SYS_PLL3_BYPASS] =3D imx_clk_hw_mux_flags("sys_pll3_bypass", a= natop_base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass= _sels), CLK_SET_RATE_PARENT); =20 /* PLL out gate */ - hws[IMX8MN_AUDIO_PLL1_OUT] =3D imx_clk_hw_gate("audio_pll1_out", "audio_p= ll1_bypass", base, 13); - hws[IMX8MN_AUDIO_PLL2_OUT] =3D imx_clk_hw_gate("audio_pll2_out", "audio_p= ll2_bypass", base + 0x14, 13); - hws[IMX8MN_VIDEO_PLL_OUT] =3D imx_clk_hw_gate("video_pll_out", "video_pll= _bypass", base + 0x28, 13); - hws[IMX8MN_DRAM_PLL_OUT] =3D imx_clk_hw_gate("dram_pll_out", "dram_pll_by= pass", base + 0x50, 13); - hws[IMX8MN_GPU_PLL_OUT] =3D imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypas= s", base + 0x64, 11); - hws[IMX8MN_M7_ALT_PLL_OUT] =3D imx_clk_hw_gate("m7_alt_pll_out", "m7_alt_= pll_bypass", base + 0x74, 11); - hws[IMX8MN_ARM_PLL_OUT] =3D imx_clk_hw_gate("arm_pll_out", "arm_pll_bypas= s", base + 0x84, 11); - hws[IMX8MN_SYS_PLL3_OUT] =3D imx_clk_hw_gate("sys_pll3_out", "sys_pll3_by= pass", base + 0x114, 11); + hws[IMX8MN_AUDIO_PLL1_OUT] =3D imx_clk_hw_gate("audio_pll1_out", "audio_p= ll1_bypass", anatop_base, 13); + hws[IMX8MN_AUDIO_PLL2_OUT] =3D imx_clk_hw_gate("audio_pll2_out", "audio_p= ll2_bypass", anatop_base + 0x14, 13); + hws[IMX8MN_VIDEO_PLL_OUT] =3D imx_clk_hw_gate("video_pll_out", "video_pll= _bypass", anatop_base + 0x28, 13); + hws[IMX8MN_DRAM_PLL_OUT] =3D imx_clk_hw_gate("dram_pll_out", "dram_pll_by= pass", anatop_base + 0x50, 13); + hws[IMX8MN_GPU_PLL_OUT] =3D imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypas= s", anatop_base + 0x64, 11); + hws[IMX8MN_M7_ALT_PLL_OUT] =3D imx_clk_hw_gate("m7_alt_pll_out", "m7_alt_= pll_bypass", anatop_base + 0x74, 11); + hws[IMX8MN_ARM_PLL_OUT] =3D imx_clk_hw_gate("arm_pll_out", "arm_pll_bypas= s", anatop_base + 0x84, 11); + hws[IMX8MN_SYS_PLL3_OUT] =3D imx_clk_hw_gate("sys_pll3_out", "sys_pll3_by= pass", anatop_base + 0x114, 11); =20 /* SYS PLL1 fixed output */ - hws[IMX8MN_SYS_PLL1_OUT] =3D imx_clk_hw_gate("sys_pll1_out", "sys_pll1", = base + 0x94, 11); + hws[IMX8MN_SYS_PLL1_OUT] =3D imx_clk_hw_gate("sys_pll1_out", "sys_pll1", = anatop_base + 0x94, 11); hws[IMX8MN_SYS_PLL1_40M] =3D imx_clk_hw_fixed_factor("sys_pll1_40m", "sys= _pll1_out", 1, 20); hws[IMX8MN_SYS_PLL1_80M] =3D imx_clk_hw_fixed_factor("sys_pll1_80m", "sys= _pll1_out", 1, 10); hws[IMX8MN_SYS_PLL1_100M] =3D imx_clk_hw_fixed_factor("sys_pll1_100m", "s= ys_pll1_out", 1, 8); @@ -400,7 +401,7 @@ static int imx8mn_clocks_probe(struct platform_device *= pdev) hws[IMX8MN_SYS_PLL1_800M] =3D imx_clk_hw_fixed_factor("sys_pll1_800m", "s= ys_pll1_out", 1, 1); =20 /* SYS PLL2 fixed output */ - hws[IMX8MN_SYS_PLL2_OUT] =3D imx_clk_hw_gate("sys_pll2_out", "sys_pll2", = base + 0x104, 11); + hws[IMX8MN_SYS_PLL2_OUT] =3D imx_clk_hw_gate("sys_pll2_out", "sys_pll2", = anatop_base + 0x104, 11); hws[IMX8MN_SYS_PLL2_50M] =3D imx_clk_hw_fixed_factor("sys_pll2_50m", "sys= _pll2_out", 1, 20); hws[IMX8MN_SYS_PLL2_100M] =3D imx_clk_hw_fixed_factor("sys_pll2_100m", "s= ys_pll2_out", 1, 10); hws[IMX8MN_SYS_PLL2_125M] =3D imx_clk_hw_fixed_factor("sys_pll2_125m", "s= ys_pll2_out", 1, 8); @@ -411,14 +412,13 @@ static int imx8mn_clocks_probe(struct platform_device= *pdev) hws[IMX8MN_SYS_PLL2_500M] =3D imx_clk_hw_fixed_factor("sys_pll2_500m", "s= ys_pll2_out", 1, 2); hws[IMX8MN_SYS_PLL2_1000M] =3D imx_clk_hw_fixed_factor("sys_pll2_1000m", = "sys_pll2_out", 1, 1); =20 - hws[IMX8MN_CLK_CLKOUT1_SEL] =3D imx_clk_hw_mux2("clkout1_sel", base + 0x1= 28, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels)); 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Wed, 06 Nov 2024 01:06:16 -0800 (PST) Received: from localhost.localdomain ([2001:b07:6474:ebbf:afb5:f524:6416:8e3]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9eb17f9422sm247781366b.139.2024.11.06.01.06.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2024 01:06:16 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v3 6/8] clk: imx8mn: support spread spectrum clock generation Date: Wed, 6 Nov 2024 09:58:02 +0100 Message-ID: <20241106090549.3684963-7-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241106090549.3684963-1-dario.binacchi@amarulasolutions.com> References: <20241106090549.3684963-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The patch adds support for spread spectrum clock generation for the audio, video, and DRAM PLLs. Signed-off-by: Dario Binacchi --- Changes in v3: - Use ccm node device drivers/clk/imx/clk-imx8mn.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index feefc9ef4f51..91b819d1c523 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -322,6 +322,7 @@ static int imx8mn_clocks_probe(struct platform_device *= pdev) struct device_node *np =3D dev->of_node; struct device_node *anatop_np; void __iomem *base, *anatop_base; + struct imx_pll14xx_ssc pll1443x_ssc; int ret; =20 clk_hw_data =3D devm_kzalloc(dev, struct_size(clk_hw_data, hws, @@ -357,13 +358,18 @@ static int imx8mn_clocks_probe(struct platform_device= *pdev) hws[IMX8MN_ARM_PLL_REF_SEL] =3D imx_clk_hw_mux("arm_pll_ref_sel", anatop_= base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MN_SYS_PLL3_REF_SEL] =3D imx_clk_hw_mux("sys_pll3_ref_sel", anato= p_base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); =20 - hws[IMX8MN_AUDIO_PLL1] =3D imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_r= ef_sel", anatop_base, &imx_1443x_pll); - hws[IMX8MN_AUDIO_PLL2] =3D imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_r= ef_sel", anatop_base + 0x14, &imx_1443x_pll); - hws[IMX8MN_VIDEO_PLL] =3D imx_clk_hw_pll14xx("video_pll", "video_pll_ref_= sel", anatop_base + 0x28, &imx_1443x_pll); - hws[IMX8MN_DRAM_PLL] =3D imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel= ", anatop_base + 0x50, &imx_1443x_dram_pll); + imx_clk_pll14xx_get_ssc_conf(np, IMX8MN_AUDIO_PLL1, &pll1443x_ssc); + hws[IMX8MN_AUDIO_PLL1] =3D imx_clk_hw_pll14xx_ssc("audio_pll1", "audio_pl= l1_ref_sel", anatop_base, &imx_1443x_pll, &pll1443x_ssc); + imx_clk_pll14xx_get_ssc_conf(np, IMX8MN_AUDIO_PLL2, &pll1443x_ssc); + hws[IMX8MN_AUDIO_PLL2] =3D imx_clk_hw_pll14xx_ssc("audio_pll2", "audio_pl= l2_ref_sel", anatop_base + 0x14, &imx_1443x_pll, &pll1443x_ssc); + imx_clk_pll14xx_get_ssc_conf(np, IMX8MN_VIDEO_PLL, &pll1443x_ssc); + hws[IMX8MN_VIDEO_PLL] =3D imx_clk_hw_pll14xx_ssc("video_pll", "video_pll_= ref_sel", anatop_base + 0x28, &imx_1443x_pll, &pll1443x_ssc); + imx_clk_pll14xx_get_ssc_conf(np, IMX8MN_DRAM_PLL, &pll1443x_ssc); + hws[IMX8MN_DRAM_PLL] =3D imx_clk_hw_pll14xx_ssc("dram_pll", "dram_pll_ref= _sel", anatop_base + 0x50, &imx_1443x_dram_pll, &pll1443x_ssc); hws[IMX8MN_GPU_PLL] =3D imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", = anatop_base + 0x64, &imx_1416x_pll); hws[IMX8MN_M7_ALT_PLL] =3D imx_clk_hw_pll14xx("m7_alt_pll", "m7_alt_pll_r= ef_sel", anatop_base + 0x74, &imx_1416x_pll); hws[IMX8MN_ARM_PLL] =3D imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", = anatop_base + 0x84, &imx_1416x_pll); + hws[IMX8MN_SYS_PLL1] =3D imx_clk_hw_fixed("sys_pll1", 800000000); hws[IMX8MN_SYS_PLL2] =3D imx_clk_hw_fixed("sys_pll2", 1000000000); hws[IMX8MN_SYS_PLL3] =3D imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel= ", anatop_base + 0x114, &imx_1416x_pll); --=20 2.43.0 From nobody Sun Nov 24 08:41:14 2024 Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com [209.85.208.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E94551DF729 for ; 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charset="utf-8" Setting the "clk" (clock-controller@30380000) device node caused the reference to the "anatop" (clock-controller@30360000) device node to be lost. This patch, similar to what was already done for the base address, now distinguishes between the "anatop" device node and the "clk" device node. This change is preparatory for future developments. Signed-off-by: Dario Binacchi --- (no changes since v1) drivers/clk/imx/clk-imx8mp.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 516dbd170c8a..b2778958a572 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -408,13 +408,13 @@ static struct clk_hw_onecell_data *clk_hw_data; static int imx8mp_clocks_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; - struct device_node *np; + struct device_node *np, *anatop_np; void __iomem *anatop_base, *ccm_base; int err; =20 - np =3D of_find_compatible_node(NULL, NULL, "fsl,imx8mp-anatop"); - anatop_base =3D devm_of_iomap(dev, np, 0, NULL); - of_node_put(np); + anatop_np =3D of_find_compatible_node(NULL, NULL, "fsl,imx8mp-anatop"); + anatop_base =3D devm_of_iomap(dev, anatop_np, 0, NULL); + of_node_put(anatop_np); if (WARN_ON(IS_ERR(anatop_base))) return PTR_ERR(anatop_base); =20 --=20 2.43.0 From nobody Sun Nov 24 08:41:14 2024 Received: from mail-ej1-f41.google.com (mail-ej1-f41.google.com [209.85.218.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F1211DF73D for ; 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Wed, 06 Nov 2024 01:06:19 -0800 (PST) Received: from localhost.localdomain ([2001:b07:6474:ebbf:afb5:f524:6416:8e3]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9eb17f9422sm247781366b.139.2024.11.06.01.06.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2024 01:06:19 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v3 8/8] clk: imx8mp: support spread spectrum clock generation Date: Wed, 6 Nov 2024 09:58:04 +0100 Message-ID: <20241106090549.3684963-9-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241106090549.3684963-1-dario.binacchi@amarulasolutions.com> References: <20241106090549.3684963-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The patch adds support for spread spectrum clock generation for the audio, video, and DRAM PLLs. Signed-off-by: Dario Binacchi --- Changes in v3: - Use ccm node device Changes in v2: - Add "allOf:" and place it after "required:" block, like in the example schema. - Move the properties definition to the top-level. - Drop unit types as requested by the "make dt_binding_check" command. drivers/clk/imx/clk-imx8mp.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index b2778958a572..e53a688d2cfe 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -410,6 +410,7 @@ static int imx8mp_clocks_probe(struct platform_device *= pdev) struct device *dev =3D &pdev->dev; struct device_node *np, *anatop_np; void __iomem *anatop_base, *ccm_base; + struct imx_pll14xx_ssc pll1443x_ssc; int err; =20 anatop_np =3D of_find_compatible_node(NULL, NULL, "fsl,imx8mp-anatop"); @@ -449,10 +450,14 @@ static int imx8mp_clocks_probe(struct platform_device= *pdev) hws[IMX8MP_SYS_PLL2_REF_SEL] =3D imx_clk_hw_mux("sys_pll2_ref_sel", anato= p_base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MP_SYS_PLL3_REF_SEL] =3D imx_clk_hw_mux("sys_pll3_ref_sel", anato= p_base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); =20 - hws[IMX8MP_AUDIO_PLL1] =3D imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_r= ef_sel", anatop_base, &imx_1443x_pll); - hws[IMX8MP_AUDIO_PLL2] =3D imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_r= ef_sel", anatop_base + 0x14, &imx_1443x_pll); - hws[IMX8MP_VIDEO_PLL1] =3D imx_clk_hw_pll14xx("video_pll1", "video_pll1_r= ef_sel", anatop_base + 0x28, &imx_1443x_pll); - hws[IMX8MP_DRAM_PLL] =3D imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel= ", anatop_base + 0x50, &imx_1443x_dram_pll); + imx_clk_pll14xx_get_ssc_conf(np, IMX8MP_AUDIO_PLL1, &pll1443x_ssc); + hws[IMX8MP_AUDIO_PLL1] =3D imx_clk_hw_pll14xx_ssc("audio_pll1", "audio_pl= l1_ref_sel", anatop_base, &imx_1443x_pll, &pll1443x_ssc); + imx_clk_pll14xx_get_ssc_conf(np, IMX8MP_AUDIO_PLL2, &pll1443x_ssc); + hws[IMX8MP_AUDIO_PLL2] =3D imx_clk_hw_pll14xx_ssc("audio_pll2", "audio_pl= l2_ref_sel", anatop_base + 0x14, &imx_1443x_pll, &pll1443x_ssc); + imx_clk_pll14xx_get_ssc_conf(np, IMX8MP_VIDEO_PLL1, &pll1443x_ssc); + hws[IMX8MP_VIDEO_PLL1] =3D imx_clk_hw_pll14xx_ssc("video_pll1", "video_pl= l1_ref_sel", anatop_base + 0x28, &imx_1443x_pll, &pll1443x_ssc); + imx_clk_pll14xx_get_ssc_conf(np, IMX8MP_DRAM_PLL, &pll1443x_ssc); + hws[IMX8MP_DRAM_PLL] =3D imx_clk_hw_pll14xx_ssc("dram_pll", "dram_pll_ref= _sel", anatop_base + 0x50, &imx_1443x_dram_pll, &pll1443x_ssc); hws[IMX8MP_GPU_PLL] =3D imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", = anatop_base + 0x64, &imx_1416x_pll); hws[IMX8MP_VPU_PLL] =3D imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", = anatop_base + 0x74, &imx_1416x_pll); hws[IMX8MP_ARM_PLL] =3D imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", = anatop_base + 0x84, &imx_1416x_pll); --=20 2.43.0