From nobody Sun Nov 24 11:43:37 2024 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C2801D54E9 for ; Wed, 6 Nov 2024 08:55:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730883316; cv=none; b=foa2B8mR/jh5HwoTl0R4LuxWYuRz73se/CalAX+O1VJ49iZKqLwD5QrYnijkD5AtIBR5dhu4bRN/kOusqZ1XEZgOVBHKf9c9fs9jYEdIUQaQvGjQ5NoRJ5Ud4NMD/Xw8uD9eEvT9D2RVVE30uMJG7nBi8wuL4srCyzOuMXsZA9M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730883316; c=relaxed/simple; bh=skscjiDjbECr8LEHn636Jjj33TB2P8DYAK7RVp07Gds=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZxlsuAu2KAMkkTT5FxTYCT8z4bky/ekRPZOYu+0oOgSU4epHEKwIeVPjjHCWEkwsnRaGMzHLkdW0G+k9kzSxuHIIRhqJPX69u5wbmcd4YRpqgW/hJ3e2CW0CykWrcLWKC0TZq2XDWXA2VsmMwonDc7KIt61IbXu9izvsY9CDSq8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=BauBFOL9; arc=none smtp.client-ip=217.70.183.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="BauBFOL9" Received: by mail.gandi.net (Postfix) with ESMTPA id 13BE51C0006; Wed, 6 Nov 2024 08:55:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730883312; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=OnTNOv2IUCnGeo4ueCgcKRKkmgfN7QyKHxPbRmRTdao=; b=BauBFOL9UNS92/kJNNktBTjDB8EcF6avG2E6SCuUiRg9doJzdU5xgoX6HzY7lEMBzqMVtE hkmhSI21B28Q0Us6TAJFl/WPPqbIZWJsbfoxxIcD0bsoeD+z2XtBdaP5tJtybg8+Y8mXmx RB2oncISyptybc8av8tBeICQAuWilVJFCeIDPllMVbzR2GqX9+VUsbXDM2s2CF+1vghj3D kZBiqtTOoxVp3kjjPK2ZHzWNzQAMl5Dinii9BfQIIM4iafG6jNz9MP0a/FssgF3u9rpalt G6fRFFfqFbv5fZvIMU64EtwtWNCWoYhGnC9rC5HqGoZffLX0mXEXJmcszrwXwQ== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet Subject: [PATCH v2 1/6] memory: ti-aemif: Create aemif_set_cs_timings() Date: Wed, 6 Nov 2024 09:55:02 +0100 Message-ID: <20241106085507.76425-2-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241106085507.76425-1-bastien.curutchet@bootlin.com> References: <20241106085507.76425-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com Content-Type: text/plain; charset="utf-8" Create an aemif_set_cs_timings() function to isolate the setting of a chip select timing configuration and ease its exportation. Move the check of the configuration validity from aemif_calc_rate() to this new function. Signed-off-by: Bastien Curutchet Reviewed-by: Miquel Raynal --- drivers/memory/ti-aemif.c | 111 ++++++++++++++++++++++++++------------ 1 file changed, 78 insertions(+), 33 deletions(-) diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c index d54dc3cfff73..8d27b2513b2c 100644 --- a/drivers/memory/ti-aemif.c +++ b/drivers/memory/ti-aemif.c @@ -69,15 +69,15 @@ #define ACR_SSTROBE_MASK BIT(31) #define ASIZE_16BIT 1 =20 -#define CONFIG_MASK (TA(TA_MAX) | \ - RHOLD(RHOLD_MAX) | \ - RSTROBE(RSTROBE_MAX) | \ - RSETUP(RSETUP_MAX) | \ - WHOLD(WHOLD_MAX) | \ - WSTROBE(WSTROBE_MAX) | \ - WSETUP(WSETUP_MAX) | \ - EW(EW_MAX) | SSTROBE(SSTROBE_MAX) | \ - ASIZE_MAX) +#define TIMINGS_MASK (TA(TA_MAX) | \ + RHOLD(RHOLD_MAX) | \ + RSTROBE(RSTROBE_MAX) | \ + RSETUP(RSETUP_MAX) | \ + WHOLD(WHOLD_MAX) | \ + WSTROBE(WSTROBE_MAX) | \ + WSETUP(WSETUP_MAX)) + +#define CONFIG_MASK (EW(EW_MAX) | SSTROBE(SSTROBE_MAX) | ASIZE_MAX) =20 /** * struct aemif_cs_data: structure to hold cs parameters @@ -107,6 +107,27 @@ struct aemif_cs_data { u8 asize; }; =20 +/** + * struct aemif_cs_timings: structure to hold cs timing configuration + * values are expressed in number of clock cycles - 1 + * @ta: minimum turn around time + * @rhold: read hold width + * @rstrobe: read strobe width + * @rsetup: read setup width + * @whold: write hold width + * @wstrobe: write strobe width + * @wsetup: write setup width + */ +struct aemif_cs_timings { + u32 ta; + u32 rhold; + u32 rstrobe; + u32 rsetup; + u32 whold; + u32 wstrobe; + u32 wsetup; +}; + /** * struct aemif_device: structure to hold device data * @base: base address of AEMIF registers @@ -125,6 +146,44 @@ struct aemif_device { struct aemif_cs_data cs_data[NUM_CS]; }; =20 +/** + * aemif_set_cs_timings - Set the timing configuration of a given chip sel= ect. + * @aemif: aemif device to configure + * @cs: index of the chip select to configure. + * @timings: timings configuration to set + * + * Returns 0 on success, else negative errno. + */ +static int aemif_set_cs_timings(struct aemif_device *aemif, u8 cs, struct = aemif_cs_timings *timings) +{ + unsigned int offset; + u32 val, set; + + if (!timings || !aemif) + return -EINVAL; + + if (cs > aemif->num_cs) + return -EINVAL; + + if (timings->ta > TA_MAX || timings->rhold > RHOLD_MAX || timings->rstrob= e > RSTROBE_MAX || + timings->rsetup > RSETUP_MAX || timings->whold > WHOLD_MAX || + timings->wstrobe > WSTROBE_MAX || timings->wsetup > WSETUP_MAX) + return -EINVAL; + + set =3D TA(timings->ta) | RHOLD(timings->rhold) | RSTROBE(timings->rstrob= e) | + RSETUP(timings->rsetup) | WHOLD(timings->whold) | + WSTROBE(timings->wstrobe) | WSETUP(timings->wsetup); + + offset =3D A1CR_OFFSET + cs * 4; + + val =3D readl(aemif->base + offset); + val &=3D ~TIMINGS_MASK; + val |=3D set; + writel(val, aemif->base + offset); + + return 0; +} + /** * aemif_calc_rate - calculate timing data. * @pdev: platform device to calculate for @@ -149,10 +208,6 @@ static int aemif_calc_rate(struct platform_device *pde= v, int wanted, if (result < 0) result =3D 0; =20 - /* ... But configuring tighter timings is not an option. */ - else if (result > max) - result =3D -EINVAL; - return result; } =20 @@ -174,32 +229,22 @@ static int aemif_config_abus(struct platform_device *= pdev, int csnum) { struct aemif_device *aemif =3D platform_get_drvdata(pdev); struct aemif_cs_data *data =3D &aemif->cs_data[csnum]; - int ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup; unsigned long clk_rate =3D aemif->clk_rate; + struct aemif_cs_timings timings; unsigned offset; u32 set, val; =20 offset =3D A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4; =20 - ta =3D aemif_calc_rate(pdev, data->ta, clk_rate, TA_MAX); - rhold =3D aemif_calc_rate(pdev, data->rhold, clk_rate, RHOLD_MAX); - rstrobe =3D aemif_calc_rate(pdev, data->rstrobe, clk_rate, RSTROBE_MAX); - rsetup =3D aemif_calc_rate(pdev, data->rsetup, clk_rate, RSETUP_MAX); - whold =3D aemif_calc_rate(pdev, data->whold, clk_rate, WHOLD_MAX); - wstrobe =3D aemif_calc_rate(pdev, data->wstrobe, clk_rate, WSTROBE_MAX); - wsetup =3D aemif_calc_rate(pdev, data->wsetup, clk_rate, WSETUP_MAX); - - if (ta < 0 || rhold < 0 || rstrobe < 0 || rsetup < 0 || - whold < 0 || wstrobe < 0 || wsetup < 0) { - dev_err(&pdev->dev, "%s: cannot get suitable timings\n", - __func__); - return -EINVAL; - } - - set =3D TA(ta) | RHOLD(rhold) | RSTROBE(rstrobe) | RSETUP(rsetup) | - WHOLD(whold) | WSTROBE(wstrobe) | WSETUP(wsetup); + timings.ta =3D aemif_calc_rate(pdev, data->ta, clk_rate, TA_MAX); + timings.rhold =3D aemif_calc_rate(pdev, data->rhold, clk_rate, RHOLD_MAX); + timings.rstrobe =3D aemif_calc_rate(pdev, data->rstrobe, clk_rate, RSTROB= E_MAX); + timings.rsetup =3D aemif_calc_rate(pdev, data->rsetup, clk_rate, RSETUP_M= AX); + timings.whold =3D aemif_calc_rate(pdev, data->whold, clk_rate, WHOLD_MAX); + timings.wstrobe =3D aemif_calc_rate(pdev, data->wstrobe, clk_rate, WSTROB= E_MAX); + timings.wsetup =3D aemif_calc_rate(pdev, data->wsetup, clk_rate, WSETUP_M= AX); =20 - set |=3D (data->asize & ACR_ASIZE_MASK); + set =3D (data->asize & ACR_ASIZE_MASK); if (data->enable_ew) set |=3D ACR_EW_MASK; if (data->enable_ss) @@ -210,7 +255,7 @@ static int aemif_config_abus(struct platform_device *pd= ev, int csnum) val |=3D set; writel(val, aemif->base + offset); =20 - return 0; + return aemif_set_cs_timings(aemif, data->cs - aemif->cs_offset, &timings); } =20 static inline int aemif_cycles_to_nsec(int val, unsigned long clk_rate) --=20 2.47.0