From nobody Sun Nov 24 09:57:31 2024 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C2801D54E9 for ; Wed, 6 Nov 2024 08:55:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730883316; cv=none; b=foa2B8mR/jh5HwoTl0R4LuxWYuRz73se/CalAX+O1VJ49iZKqLwD5QrYnijkD5AtIBR5dhu4bRN/kOusqZ1XEZgOVBHKf9c9fs9jYEdIUQaQvGjQ5NoRJ5Ud4NMD/Xw8uD9eEvT9D2RVVE30uMJG7nBi8wuL4srCyzOuMXsZA9M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730883316; c=relaxed/simple; bh=skscjiDjbECr8LEHn636Jjj33TB2P8DYAK7RVp07Gds=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZxlsuAu2KAMkkTT5FxTYCT8z4bky/ekRPZOYu+0oOgSU4epHEKwIeVPjjHCWEkwsnRaGMzHLkdW0G+k9kzSxuHIIRhqJPX69u5wbmcd4YRpqgW/hJ3e2CW0CykWrcLWKC0TZq2XDWXA2VsmMwonDc7KIt61IbXu9izvsY9CDSq8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=BauBFOL9; arc=none smtp.client-ip=217.70.183.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="BauBFOL9" Received: by mail.gandi.net (Postfix) with ESMTPA id 13BE51C0006; Wed, 6 Nov 2024 08:55:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730883312; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=OnTNOv2IUCnGeo4ueCgcKRKkmgfN7QyKHxPbRmRTdao=; b=BauBFOL9UNS92/kJNNktBTjDB8EcF6avG2E6SCuUiRg9doJzdU5xgoX6HzY7lEMBzqMVtE hkmhSI21B28Q0Us6TAJFl/WPPqbIZWJsbfoxxIcD0bsoeD+z2XtBdaP5tJtybg8+Y8mXmx RB2oncISyptybc8av8tBeICQAuWilVJFCeIDPllMVbzR2GqX9+VUsbXDM2s2CF+1vghj3D kZBiqtTOoxVp3kjjPK2ZHzWNzQAMl5Dinii9BfQIIM4iafG6jNz9MP0a/FssgF3u9rpalt G6fRFFfqFbv5fZvIMU64EtwtWNCWoYhGnC9rC5HqGoZffLX0mXEXJmcszrwXwQ== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet Subject: [PATCH v2 1/6] memory: ti-aemif: Create aemif_set_cs_timings() Date: Wed, 6 Nov 2024 09:55:02 +0100 Message-ID: <20241106085507.76425-2-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241106085507.76425-1-bastien.curutchet@bootlin.com> References: <20241106085507.76425-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com Content-Type: text/plain; charset="utf-8" Create an aemif_set_cs_timings() function to isolate the setting of a chip select timing configuration and ease its exportation. Move the check of the configuration validity from aemif_calc_rate() to this new function. Signed-off-by: Bastien Curutchet Reviewed-by: Miquel Raynal --- drivers/memory/ti-aemif.c | 111 ++++++++++++++++++++++++++------------ 1 file changed, 78 insertions(+), 33 deletions(-) diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c index d54dc3cfff73..8d27b2513b2c 100644 --- a/drivers/memory/ti-aemif.c +++ b/drivers/memory/ti-aemif.c @@ -69,15 +69,15 @@ #define ACR_SSTROBE_MASK BIT(31) #define ASIZE_16BIT 1 =20 -#define CONFIG_MASK (TA(TA_MAX) | \ - RHOLD(RHOLD_MAX) | \ - RSTROBE(RSTROBE_MAX) | \ - RSETUP(RSETUP_MAX) | \ - WHOLD(WHOLD_MAX) | \ - WSTROBE(WSTROBE_MAX) | \ - WSETUP(WSETUP_MAX) | \ - EW(EW_MAX) | SSTROBE(SSTROBE_MAX) | \ - ASIZE_MAX) +#define TIMINGS_MASK (TA(TA_MAX) | \ + RHOLD(RHOLD_MAX) | \ + RSTROBE(RSTROBE_MAX) | \ + RSETUP(RSETUP_MAX) | \ + WHOLD(WHOLD_MAX) | \ + WSTROBE(WSTROBE_MAX) | \ + WSETUP(WSETUP_MAX)) + +#define CONFIG_MASK (EW(EW_MAX) | SSTROBE(SSTROBE_MAX) | ASIZE_MAX) =20 /** * struct aemif_cs_data: structure to hold cs parameters @@ -107,6 +107,27 @@ struct aemif_cs_data { u8 asize; }; =20 +/** + * struct aemif_cs_timings: structure to hold cs timing configuration + * values are expressed in number of clock cycles - 1 + * @ta: minimum turn around time + * @rhold: read hold width + * @rstrobe: read strobe width + * @rsetup: read setup width + * @whold: write hold width + * @wstrobe: write strobe width + * @wsetup: write setup width + */ +struct aemif_cs_timings { + u32 ta; + u32 rhold; + u32 rstrobe; + u32 rsetup; + u32 whold; + u32 wstrobe; + u32 wsetup; +}; + /** * struct aemif_device: structure to hold device data * @base: base address of AEMIF registers @@ -125,6 +146,44 @@ struct aemif_device { struct aemif_cs_data cs_data[NUM_CS]; }; =20 +/** + * aemif_set_cs_timings - Set the timing configuration of a given chip sel= ect. + * @aemif: aemif device to configure + * @cs: index of the chip select to configure. + * @timings: timings configuration to set + * + * Returns 0 on success, else negative errno. + */ +static int aemif_set_cs_timings(struct aemif_device *aemif, u8 cs, struct = aemif_cs_timings *timings) +{ + unsigned int offset; + u32 val, set; + + if (!timings || !aemif) + return -EINVAL; + + if (cs > aemif->num_cs) + return -EINVAL; + + if (timings->ta > TA_MAX || timings->rhold > RHOLD_MAX || timings->rstrob= e > RSTROBE_MAX || + timings->rsetup > RSETUP_MAX || timings->whold > WHOLD_MAX || + timings->wstrobe > WSTROBE_MAX || timings->wsetup > WSETUP_MAX) + return -EINVAL; + + set =3D TA(timings->ta) | RHOLD(timings->rhold) | RSTROBE(timings->rstrob= e) | + RSETUP(timings->rsetup) | WHOLD(timings->whold) | + WSTROBE(timings->wstrobe) | WSETUP(timings->wsetup); + + offset =3D A1CR_OFFSET + cs * 4; + + val =3D readl(aemif->base + offset); + val &=3D ~TIMINGS_MASK; + val |=3D set; + writel(val, aemif->base + offset); + + return 0; +} + /** * aemif_calc_rate - calculate timing data. * @pdev: platform device to calculate for @@ -149,10 +208,6 @@ static int aemif_calc_rate(struct platform_device *pde= v, int wanted, if (result < 0) result =3D 0; =20 - /* ... But configuring tighter timings is not an option. */ - else if (result > max) - result =3D -EINVAL; - return result; } =20 @@ -174,32 +229,22 @@ static int aemif_config_abus(struct platform_device *= pdev, int csnum) { struct aemif_device *aemif =3D platform_get_drvdata(pdev); struct aemif_cs_data *data =3D &aemif->cs_data[csnum]; - int ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup; unsigned long clk_rate =3D aemif->clk_rate; + struct aemif_cs_timings timings; unsigned offset; u32 set, val; =20 offset =3D A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4; =20 - ta =3D aemif_calc_rate(pdev, data->ta, clk_rate, TA_MAX); - rhold =3D aemif_calc_rate(pdev, data->rhold, clk_rate, RHOLD_MAX); - rstrobe =3D aemif_calc_rate(pdev, data->rstrobe, clk_rate, RSTROBE_MAX); - rsetup =3D aemif_calc_rate(pdev, data->rsetup, clk_rate, RSETUP_MAX); - whold =3D aemif_calc_rate(pdev, data->whold, clk_rate, WHOLD_MAX); - wstrobe =3D aemif_calc_rate(pdev, data->wstrobe, clk_rate, WSTROBE_MAX); - wsetup =3D aemif_calc_rate(pdev, data->wsetup, clk_rate, WSETUP_MAX); - - if (ta < 0 || rhold < 0 || rstrobe < 0 || rsetup < 0 || - whold < 0 || wstrobe < 0 || wsetup < 0) { - dev_err(&pdev->dev, "%s: cannot get suitable timings\n", - __func__); - return -EINVAL; - } - - set =3D TA(ta) | RHOLD(rhold) | RSTROBE(rstrobe) | RSETUP(rsetup) | - WHOLD(whold) | WSTROBE(wstrobe) | WSETUP(wsetup); + timings.ta =3D aemif_calc_rate(pdev, data->ta, clk_rate, TA_MAX); + timings.rhold =3D aemif_calc_rate(pdev, data->rhold, clk_rate, RHOLD_MAX); + timings.rstrobe =3D aemif_calc_rate(pdev, data->rstrobe, clk_rate, RSTROB= E_MAX); + timings.rsetup =3D aemif_calc_rate(pdev, data->rsetup, clk_rate, RSETUP_M= AX); + timings.whold =3D aemif_calc_rate(pdev, data->whold, clk_rate, WHOLD_MAX); + timings.wstrobe =3D aemif_calc_rate(pdev, data->wstrobe, clk_rate, WSTROB= E_MAX); + timings.wsetup =3D aemif_calc_rate(pdev, data->wsetup, clk_rate, WSETUP_M= AX); =20 - set |=3D (data->asize & ACR_ASIZE_MASK); + set =3D (data->asize & ACR_ASIZE_MASK); if (data->enable_ew) set |=3D ACR_EW_MASK; if (data->enable_ss) @@ -210,7 +255,7 @@ static int aemif_config_abus(struct platform_device *pd= ev, int csnum) val |=3D set; writel(val, aemif->base + offset); =20 - return 0; + return aemif_set_cs_timings(aemif, data->cs - aemif->cs_offset, &timings); } =20 static inline int aemif_cycles_to_nsec(int val, unsigned long clk_rate) --=20 2.47.0 From nobody Sun Nov 24 09:57:31 2024 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A98591D54D1 for ; Wed, 6 Nov 2024 08:55:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730883318; cv=none; b=PUETxSumnJ26emuhQhXvLjcAmzPufnuD6EHlyBN07r8Ezdp8Xmk+qgF4VO0DIinp9xArgI9lSfYqqAAQr12m7wVt6qQGoXzBLnbE6EPMjuo8nP54nPSmTpWomhaGn6UlPCS5cP47097AnFYhQNhZJva5JuB9H7U4b/yC0vwXVzQ= ARC-Message-Signature: i=1; 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Wed, 6 Nov 2024 08:55:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730883313; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=s+0pt+qgA3AeaxElP0RiAUhXdYVSmYqTnFBH1A+/viM=; b=F0SwiR+CYN9POeyxUNSZTLHnNidPv6k856mvl4/NeOBbuwNYouBjp15W862XgzPaAf4YpJ SOGzYUzwYA5OOu2F29bS1bGF7WFR6uwcv5/oMeF2PAtcButBZehQOhozEq5NTiwsFn0Ls2 wqqQNXqyGP7/pwP9vONAvWSufRLEwF6GnD67SHt7W785h7AGp5zKyRZ7oAw1QJqm+7OkeG QjHRDfRELlMJwmoPnJdcj0Uv5DX1zhqhsLJXf7TipQMye+dLBRIVSNPHWxObSEtPu7ukuE QNo0mAhP5N7m0Yi1WOuHct2ZV9WVjr0vxGnnL9L8EVrok1gWNZuT2m8YnhTIAQ== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet Subject: [PATCH v2 2/6] memory: ti-aemif: Export aemif_set_cs_timings() Date: Wed, 6 Nov 2024 09:55:03 +0100 Message-ID: <20241106085507.76425-3-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241106085507.76425-1-bastien.curutchet@bootlin.com> References: <20241106085507.76425-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com Content-Type: text/plain; charset="utf-8" Export the aemif_set_cs_timing() symbol so it can be used by other drivers Add a spinlock to protect the CS configuration register from concurrent accesses. Signed-off-by: Bastien Curutchet --- drivers/memory/ti-aemif.c | 35 ++++++++++++--------------------- include/linux/memory/ti-aemif.h | 31 +++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+), 22 deletions(-) create mode 100644 include/linux/memory/ti-aemif.h diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c index 8d27b2513b2c..4587095aa703 100644 --- a/drivers/memory/ti-aemif.c +++ b/drivers/memory/ti-aemif.c @@ -13,10 +13,12 @@ #include #include #include +#include #include #include #include #include +#include =20 #define TA_SHIFT 2 #define RHOLD_SHIFT 4 @@ -107,27 +109,6 @@ struct aemif_cs_data { u8 asize; }; =20 -/** - * struct aemif_cs_timings: structure to hold cs timing configuration - * values are expressed in number of clock cycles - 1 - * @ta: minimum turn around time - * @rhold: read hold width - * @rstrobe: read strobe width - * @rsetup: read setup width - * @whold: write hold width - * @wstrobe: write strobe width - * @wsetup: write setup width - */ -struct aemif_cs_timings { - u32 ta; - u32 rhold; - u32 rstrobe; - u32 rsetup; - u32 whold; - u32 wstrobe; - u32 wsetup; -}; - /** * struct aemif_device: structure to hold device data * @base: base address of AEMIF registers @@ -136,6 +117,7 @@ struct aemif_cs_timings { * @num_cs: number of assigned chip-selects * @cs_offset: start number of cs nodes * @cs_data: array of chip-select settings + * @config_cs_lock: lock used to access CS configuration */ struct aemif_device { void __iomem *base; @@ -144,6 +126,7 @@ struct aemif_device { u8 num_cs; int cs_offset; struct aemif_cs_data cs_data[NUM_CS]; + spinlock_t config_cs_lock; }; =20 /** @@ -154,8 +137,9 @@ struct aemif_device { * * Returns 0 on success, else negative errno. */ -static int aemif_set_cs_timings(struct aemif_device *aemif, u8 cs, struct = aemif_cs_timings *timings) +int aemif_set_cs_timings(struct aemif_device *aemif, u8 cs, struct aemif_c= s_timings *timings) { + unsigned long flags; unsigned int offset; u32 val, set; =20 @@ -176,13 +160,16 @@ static int aemif_set_cs_timings(struct aemif_device *= aemif, u8 cs, struct aemif_ =20 offset =3D A1CR_OFFSET + cs * 4; =20 + spin_lock_irqsave(&aemif->config_cs_lock, flags); val =3D readl(aemif->base + offset); val &=3D ~TIMINGS_MASK; val |=3D set; writel(val, aemif->base + offset); + spin_unlock_irqrestore(&aemif->config_cs_lock, flags); =20 return 0; } +EXPORT_SYMBOL(aemif_set_cs_timings); =20 /** * aemif_calc_rate - calculate timing data. @@ -231,6 +218,7 @@ static int aemif_config_abus(struct platform_device *pd= ev, int csnum) struct aemif_cs_data *data =3D &aemif->cs_data[csnum]; unsigned long clk_rate =3D aemif->clk_rate; struct aemif_cs_timings timings; + unsigned long flags; unsigned offset; u32 set, val; =20 @@ -250,10 +238,12 @@ static int aemif_config_abus(struct platform_device *= pdev, int csnum) if (data->enable_ss) set |=3D ACR_SSTROBE_MASK; =20 + spin_lock_irqsave(&aemif->config_cs_lock, flags); val =3D readl(aemif->base + offset); val &=3D ~CONFIG_MASK; val |=3D set; writel(val, aemif->base + offset); + spin_unlock_irqrestore(&aemif->config_cs_lock, flags); =20 return aemif_set_cs_timings(aemif, data->cs - aemif->cs_offset, &timings); } @@ -396,6 +386,7 @@ static int aemif_probe(struct platform_device *pdev) if (IS_ERR(aemif->base)) return PTR_ERR(aemif->base); =20 + spin_lock_init(&aemif->config_cs_lock); if (np) { /* * For every controller device node, there is a cs device node diff --git a/include/linux/memory/ti-aemif.h b/include/linux/memory/ti-aemi= f.h new file mode 100644 index 000000000000..809f0a68605a --- /dev/null +++ b/include/linux/memory/ti-aemif.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __TI_AEMIF_H +#define __TI_AEMIF_H + +/** + * struct aemif_cs_timings: structure to hold cs timing configuration + * values are expressed in number of clock cycles - 1 + * @ta: minimum turn around time + * @rhold: read hold width + * @rstrobe: read strobe width + * @rsetup: read setup width + * @whold: write hold width + * @wstrobe: write strobe width + * @wsetup: write setup width + */ +struct aemif_cs_timings { + u32 ta; + u32 rhold; + u32 rstrobe; + u32 rsetup; + u32 whold; + u32 wstrobe; + u32 wsetup; +}; + +struct aemif_device; + +int aemif_set_cs_timings(struct aemif_device *aemif, u8 cs, struct aemif_c= s_timings *timings); + +#endif // __TI_AEMIF_H --=20 2.47.0 From nobody Sun Nov 24 09:57:31 2024 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8523C1D6DA9 for ; Wed, 6 Nov 2024 08:55:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730883319; cv=none; b=r+QBXoS41rg7SBnt9yzQwV42fsxIeec+3sHoEtesmI33q2UEyDH76t8u0q0DSCFC2snmSsaJlxlZgYZvmSPGCgUE+AJ4b5uzgpqwXV5K2c9dTMigKPvR4YR78vhPagYg0srGGX2T+1EzAObVvVz+AKW0ywhMjPTQMrfru1hkww8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730883319; c=relaxed/simple; bh=h6Ixu3RgfB/yKWn7YlzSBsiXSugceNv8TIHypQHazUA=; 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d=bootlin.com; s=gm1; t=1730883314; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=260i8Kmy1qIGGfd2CxjTGXG+BKpSWuDOsQ7KscW8IdI=; b=RVDddowheMh2Y67227SddCz/E09oO7H6Uo62/Qz482isvIR8bpHboW4ogqNv0HRNzNx+HQ RROWE8ReS8ZJySauLtKzS+nbf/jphrpqUt1iA0YwlOK/2pme7oYlSRl6axRD0HcH0Bit1Y 9X0vSqiNbAiQ4h9ffLnx4Z6mYjU89P1/nYQ9iYAaH72pZpyEyXD1+3Oh7HaIB8lwQY1uug TU0twGZmgzdfDHhHxiRBLdOVqcBkwxbhgDCjc9z7WItkeWMCtTj25QKJyVyDoomx3nJoRv 3mSKKrEja8YKpU62+oPD3S0VUHfM+ULHIeJkhu4mlINbj8l+HUqYD73nIQqltg== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet , kernel test robot Subject: [PATCH v2 3/6] mtd: rawnand: davinci: Always depends on TI_AEMIF Date: Wed, 6 Nov 2024 09:55:04 +0100 Message-ID: <20241106085507.76425-4-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241106085507.76425-1-bastien.curutchet@bootlin.com> References: <20241106085507.76425-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com Content-Type: text/plain; charset="utf-8" DAVINCI_NAND depends on TI_AEMIF only when ARCH_KEYSTONE is selected while the NAND controller is also always a part of the AEMIF controller on DaVinci SoCs. Set a dependency on TI_AEMIF regardless of the selected architecture. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202411020140.3wsKJOSB-lkp@int= el.com/ Closes: https://lore.kernel.org/oe-kbuild-all/202411020957.X1T8T9ZR-lkp@int= el.com/ Signed-off-by: Bastien Curutchet --- drivers/mtd/nand/raw/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index d0aaccf72d78..bb61434347bd 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -279,8 +279,8 @@ config MTD_NAND_SH_FLCTL =20 config MTD_NAND_DAVINCI tristate "DaVinci/Keystone NAND controller" - depends on ARCH_DAVINCI || (ARCH_KEYSTONE && TI_AEMIF) || COMPILE_TEST - depends on HAS_IOMEM + depends on COMPILE_TEST || ARCH_DAVINCI || ARCH_KEYSTONE + depends on HAS_IOMEM && TI_AEMIF help Enable the driver for NAND flash chips on Texas Instruments DaVinci/Keystone processors. --=20 2.47.0 From nobody Sun Nov 24 09:57:31 2024 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 851DD1D63F8 for ; Wed, 6 Nov 2024 08:55:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730883319; cv=none; b=haTV9RE8Aa7Cn0GVvStbcwuKPIce2UUylYrTskC5t73yoIrko3COic3FTo6QXw5aD3BN3TVHp15XXGnZiXsL24Y2zIXtsyoiFT09tH7089OKHDyf87VOrufK3ZoobqEK/8QkzUFTJk1PbHvIEsTJoqtR+lD8f+gjxmUt5UhOlg8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730883319; c=relaxed/simple; bh=deaieWFiVONpNRlAhKMPRKsF7JDojpQ/DZGVZJ9W5Dg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rBerSnA2OM4a0xvdHYUGBgJgl8rpFy6j8vojLYhci/A06tM1keG8aEfQ4jdWo87L2pIos2JFcpDqCQT1piQpSaLr1BQY1+kmR0RtMVSS4gl/BK3ZDPA1JSGmO1OMJFH9JguEONgqAiu3U0E/d3RMPfhNlEgYh6nZjbz41kzeoHY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=BaOim/Ri; arc=none smtp.client-ip=217.70.183.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="BaOim/Ri" Received: by mail.gandi.net (Postfix) with ESMTPA id 5453D1C0011; Wed, 6 Nov 2024 08:55:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730883315; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=khZM5fFii6r1q+Z9uZi3Zgk6G9+0lCTuTox0qCES4xo=; b=BaOim/RiEk5dHGcktW6R1sY5hwjLW2MCkHaoo57gZKnhvU5SpYwcorRETyOoCBx9Avjx4j shUfh7lcCq4+j92aGGaeV16wU/Q+DQFuV79CuG2oz4ocx6b/ph/BFswyk8Rth9n6cl9r38 AW9O3tJ0hjTJxHsNliUrrq3fc4laoRoS0DxR4YdmppBJBSDHXywYywfuUhQAqHaNtDE6z5 m3BzKNFf2c8p79+w1bAsJlBOd2rRjgpNKg6KtNe3NhNDcJuLDR49gLVAxCl4Fk9TbtFhby qU7SACr8AKcKKwko16QfMj13cDveradcy7evwoCa3yN7nsC4Oto7i6XUHl9Wyw== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet Subject: [PATCH v2 4/6] mtd: rawnand: davinci: Order headers alphabetically Date: Wed, 6 Nov 2024 09:55:05 +0100 Message-ID: <20241106085507.76425-5-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241106085507.76425-1-bastien.curutchet@bootlin.com> References: <20241106085507.76425-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com Content-Type: text/plain; charset="utf-8" Order headers alphabetically for better readability. Signed-off-by: Bastien Curutchet --- drivers/mtd/nand/raw/davinci_nand.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/dav= inci_nand.c index 392678143a36..3c0efbdd789e 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -10,15 +10,15 @@ * Dirk Behme */ =20 -#include -#include -#include #include #include +#include +#include #include #include -#include #include +#include +#include =20 #define NRCSR_OFFSET 0x00 #define NANDFCR_OFFSET 0x60 --=20 2.47.0 From nobody Sun Nov 24 09:57:31 2024 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99B891D90A1 for ; Wed, 6 Nov 2024 08:55:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730883321; cv=none; b=sEYkZ0RZ0tZ4l5xUzQpMpoxzs6hFUfM80mhnBsc2livjkzv71DRscG1EwkX4y3QIQjgcKWIUel46zEDYMv53XAJpU/yL4+tkHprZNTL2wG9XmebV179pdz+/yBLzUv6bwI3oHVrKHp7zfDDwjTX4hcsG2htITZ1Swr9DdT6kXbU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730883321; c=relaxed/simple; bh=jq/HxwUks//QkKP3ZJZNN0GtGvXs1KXTbgyq1k0z2kU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=pCEUWEesf2zSQ5maD1c+kK1p5wqpVix8BWj7h22MUorBQ09gfGNBWTL2l8dkdfkutO/oug9czsIjApPRogh/GvEbQDUPuT56A3zWSiNRaMK6PNtDXu8w09Hy2cIyDbhWVshIyDdZt9iPx/YyIdOUJlbw1WovUI8oBce6RX+iHFA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=ck6Y+Zlw; arc=none smtp.client-ip=217.70.183.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="ck6Y+Zlw" Received: by mail.gandi.net (Postfix) with ESMTPA id 798181C000B; Wed, 6 Nov 2024 08:55:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730883317; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ONE5RIDa+M5HrCVn5iTpaeEU6VZHpy9NTdUHLDL3hak=; b=ck6Y+Zlw/AlY7e/Yr2LL6isIQVn9cSua0Dpk3NWwZPCSTn6A+f93jkfzgu9Oa9tu0JyWZ2 8GRk+NX98DyLdS/D35+tjG0DgISGywDFKi4JS4BCOPE7S5gq43Qq3gLwB0pDFgHueP/1qP VO54cKwHpddjrrWP+BlAbK645vfpvn1xWvG/cWFhD2CU2FElzE8KsTUWnbswE5VCCcRG2M AoavttgMtHPyhLMlof7K7LuKu0wd0v/pnlRSIoiWFJ8KM4v9IHmmDDQLyBQj4J8giQ3GJm D0+rbQ0Jy+6mp9uMM3h0/wvApZX2td/7U7/AzTR6R+xxImFkrsTzW/b9DObDwQ== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet Subject: [PATCH v2 5/6] mtd: rawnand: davinci: Add clock resource Date: Wed, 6 Nov 2024 09:55:06 +0100 Message-ID: <20241106085507.76425-6-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241106085507.76425-1-bastien.curutchet@bootlin.com> References: <20241106085507.76425-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com Content-Type: text/plain; charset="utf-8" NAND controller has a reference clock inherited from the AEMIF (cf. Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt) This clock isn't used yet by the driver. Add a struct clock in the struct davinci_nand_info so it can be used to compute timings. Signed-off-by: Bastien Curutchet --- drivers/mtd/nand/raw/davinci_nand.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/dav= inci_nand.c index 3c0efbdd789e..563045c7ce08 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -10,6 +10,7 @@ * Dirk Behme */ =20 +#include #include #include #include @@ -117,6 +118,8 @@ struct davinci_nand_info { uint32_t mask_cle; =20 uint32_t core_chipsel; + + struct clk *clk; }; =20 static DEFINE_SPINLOCK(davinci_nand_lock); @@ -822,6 +825,10 @@ static int nand_davinci_probe(struct platform_device *= pdev) return -EADDRNOTAVAIL; } =20 + info->clk =3D devm_clk_get_enabled(&pdev->dev, "aemif"); + if (IS_ERR(info->clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(info->clk), "failed to get cloc= k"); + info->pdev =3D pdev; info->base =3D base; info->vaddr =3D vaddr; --=20 2.47.0 From nobody Sun Nov 24 09:57:31 2024 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EAF471D90C5 for ; Wed, 6 Nov 2024 08:55:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730883322; cv=none; b=u6O6AmomB0HECwfDxvXOtnOeE0mwqeIgIc7t79TSfVyMoL3RAHVtVRcSp6oclp5q4fOCZiV7h9ogWR6RFKc6evcphkLANjN6S6uKh2XDVTGxkWH1ZN4uASV1AwuXm4n8k/p1tQjM9fMXZh+II1vNm7VoAeF+HYbiyar2eMTC/kk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730883322; c=relaxed/simple; bh=zrKk5ywALNSmj9VvfTnk2XFFMhWwhKs6UBoJLohqtoU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=R8nEPPF/SzOHCA5LeTERk0Vyh8TQXxg8Lw8zmPN0vcgwiMHBCEiWJV4ytRLOJ+82+drr/erpR++fyTku2Z/eXUF+H72mmHgm3WAaLlad9gu0SacPhPlFVUq2S/xjK9YDW8zfF1s8h6T/9JbK/bp/ighx9e/4t28y8z8ZAuk3uu4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=pobFL2EY; arc=none smtp.client-ip=217.70.183.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="pobFL2EY" Received: by mail.gandi.net (Postfix) with ESMTPA id CB7901C000F; Wed, 6 Nov 2024 08:55:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1730883318; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2oiWk53I171KwrAlfwDCvk5jTurbu1icBl8oHWKDmI0=; b=pobFL2EYMefb4EKi6ORoSqJ/fTSlEbYl6DBJxzWb8/8OagTnuTL+wOBF6rYF6WD2FHI23/ eUHB5W9n19Hgb1k75DSQp2loSgxvNSzyZCp+J4N5XBxyjheYhkdUWNb6t+sLJVvHYRckAu o6j3p/ELy6JNWyBox+lVO/fQNqjf0WjEPwkZ5TChsWhjzT/GKUU3n/m62K+K+aUY2rEMjf pBob7/NZ+1+jWBqV2MKGnoVjApqN2mPvOfhRrrNQ3+LgmFmeaF1lpU0zODRF2UTUwFici5 sXsybcmHrOMHKkQ3f2LfWMD+4WXbGa6xkg0MelsIFymBYmLjHaGa6WI6rDOV8Q== From: Bastien Curutchet To: Santosh Shilimkar , Krzysztof Kozlowski , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Thomas Petazzoni , Herve Codina , Christopher Cordahi , Bastien Curutchet Subject: [PATCH v2 6/6] mtd: rawnand: davinci: Implement setup_interface() operation Date: Wed, 6 Nov 2024 09:55:07 +0100 Message-ID: <20241106085507.76425-7-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241106085507.76425-1-bastien.curutchet@bootlin.com> References: <20241106085507.76425-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-GND-Sasl: bastien.curutchet@bootlin.com The setup_interface() operation isn't implemented. It forces the driver to use the ONFI mode 0, though it could use more optimal modes. Implement the setup_interface() operation. It uses the aemif_set_cs_timings() function from the AEMIF driver to update the chip select timings. The calculation of the register's contents is directly extracted from =C2=A720.3.2.3 of the DaVinci TRM [1] These timings are previously set by the AEMIF driver itself from device-tree properties. Therefore, IMHO, failing to update them in the setup_interface() isn't critical, which is why 0 is returned even when timings aren't updated. MAX_TH_PS and MAX_TSU_PS are the worst case timings based on the Keystone2 and DaVinci datasheets. [1] : https://www.ti.com/lit/ug/spruh77c/spruh77c.pdf Signed-off-by: Bastien Curutchet --- drivers/mtd/nand/raw/davinci_nand.c | 78 +++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/dav= inci_nand.c index 563045c7ce08..2d0c564c8d17 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -44,6 +45,9 @@ #define MASK_ALE 0x08 #define MASK_CLE 0x10 =20 +#define MAX_TSU_PS 3000 /* Input setup time in ps */ +#define MAX_TH_PS 1600 /* Input hold time in ps */ + struct davinci_nand_pdata { uint32_t mask_ale; uint32_t mask_cle; @@ -120,6 +124,7 @@ struct davinci_nand_info { uint32_t core_chipsel; =20 struct clk *clk; + struct aemif_device *aemif; }; =20 static DEFINE_SPINLOCK(davinci_nand_lock); @@ -767,9 +772,81 @@ static int davinci_nand_exec_op(struct nand_chip *chip, return 0; } =20 +#define TO_CYCLES(ps, period_ns) (DIV_ROUND_UP((ps) / 1000, (period_ns))) + +static int davinci_nand_setup_interface(struct nand_chip *chip, int chipnr, + const struct nand_interface_config *conf) +{ + struct davinci_nand_info *info =3D to_davinci_nand(nand_to_mtd(chip)); + const struct nand_sdr_timings *sdr; + struct aemif_cs_timings timings; + s32 cfg, min, cyc_ns; + + cyc_ns =3D 1000000000 / clk_get_rate(info->clk); + + sdr =3D nand_get_sdr_timings(conf); + if (IS_ERR(sdr)) + return PTR_ERR(sdr); + + cfg =3D TO_CYCLES(sdr->tCLR_min, cyc_ns) - 1; + timings.rsetup =3D cfg > 0 ? cfg : 0; + + cfg =3D max_t(s32, TO_CYCLES(sdr->tREA_max + MAX_TSU_PS, cyc_ns), + TO_CYCLES(sdr->tRP_min, cyc_ns)) - 1; + timings.rstrobe =3D cfg > 0 ? cfg : 0; + + min =3D TO_CYCLES(sdr->tCEA_max + MAX_TSU_PS, cyc_ns) - 2; + while ((s32)(timings.rsetup + timings.rstrobe) < min) + timings.rstrobe++; + + cfg =3D TO_CYCLES((s32)(MAX_TH_PS - sdr->tCHZ_max), cyc_ns) - 1; + timings.rhold =3D cfg > 0 ? cfg : 0; + + min =3D TO_CYCLES(sdr->tRC_min, cyc_ns) - 3; + while ((s32)(timings.rsetup + timings.rstrobe + timings.rhold) < min) + timings.rhold++; + + cfg =3D TO_CYCLES((s32)(sdr->tRHZ_max - (timings.rhold + 1) * cyc_ns * 10= 00), cyc_ns); + cfg =3D max_t(s32, cfg, TO_CYCLES(sdr->tCHZ_max, cyc_ns)) - 1; + timings.ta =3D cfg > 0 ? cfg : 0; + + cfg =3D TO_CYCLES(sdr->tWP_min, cyc_ns) - 1; + timings.wstrobe =3D cfg > 0 ? cfg : 0; + + cfg =3D max_t(s32, TO_CYCLES(sdr->tCLS_min, cyc_ns), TO_CYCLES(sdr->tALS_= min, cyc_ns)); + cfg =3D max_t(s32, cfg, TO_CYCLES(sdr->tCS_min, cyc_ns)) - 1; + timings.wsetup =3D cfg > 0 ? cfg : 0; + + min =3D TO_CYCLES(sdr->tDS_min, cyc_ns) - 2; + while ((s32)(timings.wsetup + timings.wstrobe) < min) + timings.wstrobe++; + + cfg =3D max_t(s32, TO_CYCLES(sdr->tCLH_min, cyc_ns), TO_CYCLES(sdr->tALH_= min, cyc_ns)); + cfg =3D max_t(s32, cfg, TO_CYCLES(sdr->tCH_min, cyc_ns)); + cfg =3D max_t(s32, cfg, TO_CYCLES(sdr->tDH_min, cyc_ns)) - 1; + timings.whold =3D cfg > 0 ? cfg : 0; + + min =3D TO_CYCLES(sdr->tWC_min, cyc_ns) - 2; + while ((s32)(timings.wsetup + timings.wstrobe + timings.whold) < min) + timings.whold++; + + dev_dbg(&info->pdev->dev, "RSETUP %x RSTROBE %x RHOLD %x\n", + timings.rsetup, timings.rstrobe, timings.rhold); + dev_dbg(&info->pdev->dev, "TA %x\n", timings.ta); + dev_dbg(&info->pdev->dev, "WSETUP %x WSTROBE %x WHOLD %x\n", + timings.wsetup, timings.wstrobe, timings.whold); + + if (aemif_set_cs_timings(info->aemif, info->core_chipsel, &timings) < 0) + dev_info(&info->pdev->dev, + "Failed to dynamically update the CS timings, keep them unchanged"); + + return 0; +} + static const struct nand_controller_ops davinci_nand_controller_ops =3D { .attach_chip =3D davinci_nand_attach_chip, .exec_op =3D davinci_nand_exec_op, + .setup_interface =3D davinci_nand_setup_interface, }; =20 static int nand_davinci_probe(struct platform_device *pdev) @@ -832,6 +909,7 @@ static int nand_davinci_probe(struct platform_device *p= dev) info->pdev =3D pdev; info->base =3D base; info->vaddr =3D vaddr; + info->aemif =3D dev_get_drvdata(pdev->dev.parent); =20 mtd =3D nand_to_mtd(&info->chip); mtd->dev.parent =3D &pdev->dev; --=20 2.47.0