From nobody Sun Nov 24 10:39:07 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF07B18F2C1; Wed, 6 Nov 2024 02:10:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730859037; cv=none; b=WR3KkhdR8jxiULVGoqz3QW+aziT0eMZSXtD0OLTSf85qiMIHgtQBHC4+TynkEeRnaKRp8gCu3dctniXWfA0Hl3QO0Bt9/dMnZpbqCiLYXy9wP/jCTJ2OsWoX3MnZFMv43h0Sao07fk4p9eZkbXKs24DmWQTQ/WGJgR8gtHaHmfI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730859037; c=relaxed/simple; bh=64rxGGHOzJlUyvWRWPZyt2BQTMQWnxD9Wzt/FVelKs8=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=ZXp4LbX+82tt2YGaHUc6yUIz8Ls/02mAWsLiTs9XwFI0T9u9rVUsobL9OPfLPr76FwTBbaELtuiPzTSwo7wEwmAjBNA52k99vJhxgm8eScFJHDBZvmqpTrv9DtSKwVeYXPHj4iVBqlx7cZ/f2xFX2ibtSqaRxn53k9fFlL0/xzE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Px42WH8Z; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Px42WH8Z" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AE558C4CECF; Wed, 6 Nov 2024 02:10:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1730859037; bh=64rxGGHOzJlUyvWRWPZyt2BQTMQWnxD9Wzt/FVelKs8=; h=From:To:Cc:Subject:Date:From; b=Px42WH8ZPWiZ2bmZUf/drxOOiv+poAtDxe9TczArmZotR9JmwdJGxzXhfzKTQqsEe KVd2RlY4yRXYwN9/d8/jex0kuVkyYTgB8aBKTSbw+HfRwB7fman65IILMLYn4so45r UCaFnd++nG7cBW82HvNtfGzR538I5p90s+pGeSAnwtefMefEXZcJ5l+bJNw+YluhQQ D+ErFu5G9tBMQTkX0nlhXEGg+XxHT78oHj2RT7zfbtSceWqYKfW/0aF88n0DkaOAE0 256RZps5WVlX8Q1768fMU8DNmd1wM7a5ZJgD8DMpGdb9TagL4wlWLk0naN7bnig5Z5 Tr+Ln14M9GvIw== From: Sasha Levin To: stable@vger.kernel.org, dan.j.williams@intel.com Cc: Gregory Price , Davidlohr Bueso , Jonathan Cameron , Dave Jiang , Alison Schofield , Vishal Verma , Ira Weiny , Jonathan Cameron , Alejandro Lucero , linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org Subject: FAILED: Patch "cxl/port: Fix CXL port initialization order when the subsystem is built-in" failed to apply to v6.1-stable tree Date: Tue, 5 Nov 2024 21:10:33 -0500 Message-ID: <20241106021034.181613-1-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Hint: ignore X-stable: review Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The patch below does not apply to the v6.1-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to . Thanks, Sasha Reported-by: Gregory Price Reviewed-by: Alejandro Lucero Reviewed-by: Ira Weiny Reviewed-by: Jonathan Cameron Tested-by: Alejandro Lucero Tested-by: Gregory Price ------------------ original commit in Linus's tree ------------------ From 6575b268157f37929948a8d1f3bafb3d7c055bc1 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Fri, 25 Oct 2024 12:32:55 -0700 Subject: [PATCH] cxl/port: Fix CXL port initialization order when the subsystem is built-in When the CXL subsystem is built-in the module init order is determined by Makefile order. That order violates expectations. The expectation is that cxl_acpi and cxl_mem can race to attach. If cxl_acpi wins the race, cxl_mem will find the enabled CXL root ports it needs. If cxl_acpi loses the race it will retrigger cxl_mem to attach via cxl_bus_rescan(). That flow only works if cxl_acpi can assume ports are enabled immediately upon cxl_acpi_probe() return. That in turn can only happen in the CONFIG_CXL_ACPI=3Dy case if the cxl_port driver is registered before cxl_acpi_probe() runs. Fix up the order to prevent initialization failures. Ensure that cxl_port is built-in when cxl_acpi is also built-in, arrange for Makefile order to resolve the subsys_initcall() order of cxl_port and cxl_acpi, and arrange for Makefile order to resolve the device_initcall() (module_init()) order of the remaining objects. As for what contributed to this not being found earlier, the CXL regression environment, cxl_test, builds all CXL functionality as a module to allow to symbol mocking and other dynamic reload tests. As a result there is no regression coverage for the built-in case. Reported-by: Gregory Price Closes: http://lore.kernel.org/20241004212504.1246-1-gourry@gourry.net Tested-by: Gregory Price Fixes: 8dd2bc0f8e02 ("cxl/mem: Add the cxl_mem driver") Cc: stable@vger.kernel.org Cc: Davidlohr Bueso Cc: Jonathan Cameron Cc: Dave Jiang Cc: Alison Schofield Cc: Vishal Verma Cc: Ira Weiny Reviewed-by: Jonathan Cameron Reviewed-by: Ira Weiny Tested-by: Alejandro Lucero Reviewed-by: Alejandro Lucero Signed-off-by: Dan Williams Link: https://patch.msgid.link/172988474904.476062.7961350937442459266.stgi= t@dwillia2-xfh.jf.intel.com Signed-off-by: Ira Weiny --- drivers/cxl/Kconfig | 1 + drivers/cxl/Makefile | 20 ++++++++++++++------ drivers/cxl/port.c | 17 ++++++++++++++++- 3 files changed, 31 insertions(+), 7 deletions(-) diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig index 29c192f20082c..876469e23f7a7 100644 --- a/drivers/cxl/Kconfig +++ b/drivers/cxl/Kconfig @@ -60,6 +60,7 @@ config CXL_ACPI default CXL_BUS select ACPI_TABLE_LIB select ACPI_HMAT + select CXL_PORT help Enable support for host managed device memory (HDM) resources published by a platform's ACPI CXL memory layout description. See diff --git a/drivers/cxl/Makefile b/drivers/cxl/Makefile index db321f48ba52e..2caa90fa4bf25 100644 --- a/drivers/cxl/Makefile +++ b/drivers/cxl/Makefile @@ -1,13 +1,21 @@ # SPDX-License-Identifier: GPL-2.0 + +# Order is important here for the built-in case: +# - 'core' first for fundamental init +# - 'port' before platform root drivers like 'acpi' so that CXL-root ports +# are immediately enabled +# - 'mem' and 'pmem' before endpoint drivers so that memdevs are +# immediately enabled +# - 'pci' last, also mirrors the hardware enumeration hierarchy obj-y +=3D core/ -obj-$(CONFIG_CXL_PCI) +=3D cxl_pci.o -obj-$(CONFIG_CXL_MEM) +=3D cxl_mem.o +obj-$(CONFIG_CXL_PORT) +=3D cxl_port.o obj-$(CONFIG_CXL_ACPI) +=3D cxl_acpi.o obj-$(CONFIG_CXL_PMEM) +=3D cxl_pmem.o -obj-$(CONFIG_CXL_PORT) +=3D cxl_port.o +obj-$(CONFIG_CXL_MEM) +=3D cxl_mem.o +obj-$(CONFIG_CXL_PCI) +=3D cxl_pci.o =20 -cxl_mem-y :=3D mem.o -cxl_pci-y :=3D pci.o +cxl_port-y :=3D port.o cxl_acpi-y :=3D acpi.o cxl_pmem-y :=3D pmem.o security.o -cxl_port-y :=3D port.o +cxl_mem-y :=3D mem.o +cxl_pci-y :=3D pci.o diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index 861dde65768fe..9dc394295e1fc 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -208,7 +208,22 @@ static struct cxl_driver cxl_port_driver =3D { }, }; =20 -module_cxl_driver(cxl_port_driver); +static int __init cxl_port_init(void) +{ + return cxl_driver_register(&cxl_port_driver); +} +/* + * Be ready to immediately enable ports emitted by the platform CXL root + * (e.g. cxl_acpi) when CONFIG_CXL_PORT=3Dy. + */ +subsys_initcall(cxl_port_init); + +static void __exit cxl_port_exit(void) +{ + cxl_driver_unregister(&cxl_port_driver); +} +module_exit(cxl_port_exit); + MODULE_DESCRIPTION("CXL: Port enumeration and services"); MODULE_LICENSE("GPL v2"); MODULE_IMPORT_NS(CXL); --=20 2.43.0