From nobody Thu Nov 28 03:01:49 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFE70207A2F; Wed, 6 Nov 2024 19:18:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730920695; cv=none; b=uZ3aAej3OVB5gp0aeBjEwoag8kk/rEXVJHe9NgQkZoeKf4EYG+WQU7do0pXCWMaFIM/Pz3z+YonYnmg06xRMVG1zoC1kS0rhcZxtHP6AICF4BeeVWmfd4/ZjvhitdfEgHQUsYBTGsFhiV2RanfanXn78MugBxzKMngfDsxX/I5U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730920695; c=relaxed/simple; bh=oU863Kwn7GFPSRJfsJTS+xW4A//cqLjSy0be7pAvEak=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=IMjU6MdZkJ1vFABB8pGs7WAgyajyGgDyFjgHZYRwzkSvnmZ7ow604UfwMv11PKeGolBIjzdYztrDrs1bydSGsFV3t7SeHEHsI1n5DTwGNt7gRhfi3GCEG5Qfnc3CUMILG5wATXMNNBowaWZFHpyxOJQSYGctw/Ixps3RnApN8Eo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=b1kIuSeU; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="b1kIuSeU" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1730920694; x=1762456694; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=oU863Kwn7GFPSRJfsJTS+xW4A//cqLjSy0be7pAvEak=; b=b1kIuSeU2EaCzwbAreO5ZZNTxKDwKuHYDtNQ8Wn61GAnax2pp70RzTBM oXe7zhD5RIt6+SuZ29b7wSz/d+RQ/Ki/qmt5b7w/BRVF8KDyNRGfeFBVH ogEHdOwnjS0IG9cL4pk4LY+HE2k40kcropTn+M9gmZ+w7fyXDHd6cuonY U+xex99UYFRvY4mZ4BJKy/XRRc2VGG98i37C+7q4GHKUI7nsM6k9Ahbnl ZZcBRQp4otxGCIVPaYgGIOkeFwEdaP6OL0mX6ra5hswsMM+aV5rWp0vy0 wEFApHJFipGS/08BgFezJJffqSORGx6slggzeyRNQs7viCf/vRVuHNKfa w==; X-CSE-ConnectionGUID: ZmZl/QlxSRaWd1IoElCqFw== X-CSE-MsgGUID: tmB5CBhDRj+1r6TTcTSFkQ== X-IronPort-AV: E=Sophos;i="6.11,263,1725346800"; d="scan'208";a="34481087" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 06 Nov 2024 12:18:13 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 6 Nov 2024 12:17:05 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 6 Nov 2024 12:17:03 -0700 From: Daniel Machon Date: Wed, 6 Nov 2024 20:16:39 +0100 Subject: [PATCH net-next 1/7] net: sparx5: do some preparation work Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241106-sparx5-lan969x-switch-driver-4-v1-1-f7f7316436bd@microchip.com> References: <20241106-sparx5-lan969x-switch-driver-4-v1-0-f7f7316436bd@microchip.com> In-Reply-To: <20241106-sparx5-lan969x-switch-driver-4-v1-0-f7f7316436bd@microchip.com> To: , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , "Lars Povlsen" , Steen Hegelund , Horatiu Vultur , Russell King , CC: , , X-Mailer: b4 0.14-dev The sparx5_port_init() does initial configuration of a variety of different features and options for each port. Some are shared for all types of devices, some are not. As it is now, common configuration is done after configuration of low-speed devices. This will not work when adding RGMII support in a subsequent patch. In preparation for lan969x RGMII support, move a block of code, that configures 2g5 devices, down. This ensures that the configuration common to all devices is done before configuration of 2g5, 5g, 10g and 25g devices. Also, expose the two symbols: SPX5_ETYPE_TAG_C and SPX5_ETYPE_TAG_S, which will be needed by the lan969x RGMII configuration in a subsequent patch. Reviewed-by: Steen Hegelund Reviewed-by: Horatiu Vultur Signed-off-by: Daniel Machon --- .../net/ethernet/microchip/sparx5/sparx5_main.h | 3 ++ .../net/ethernet/microchip/sparx5/sparx5_port.c | 39 ++++++++++--------= ---- 2 files changed, 21 insertions(+), 21 deletions(-) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h b/drivers/= net/ethernet/microchip/sparx5/sparx5_main.h index 146bdc938adc..91ae383a5555 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h @@ -134,6 +134,9 @@ enum sparx5_feature { =20 #define SPARX5_MAX_PTP_ID 512 =20 +#define SPX5_ETYPE_TAG_C 0x8100 +#define SPX5_ETYPE_TAG_S 0x88a8 + struct sparx5; =20 struct sparx5_calendar_data { diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c b/drivers/= net/ethernet/microchip/sparx5/sparx5_port.c index 1401761c6251..bb04c2ccf112 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c @@ -12,9 +12,6 @@ #include "sparx5_main.h" #include "sparx5_port.h" =20 -#define SPX5_ETYPE_TAG_C 0x8100 -#define SPX5_ETYPE_TAG_S 0x88a8 - #define SPX5_WAIT_US 1000 #define SPX5_WAIT_MAX_US 2000 =20 @@ -1067,24 +1064,6 @@ int sparx5_port_init(struct sparx5 *sparx5, if (err) return err; =20 - /* Configure MAC vlan awareness */ - err =3D sparx5_port_max_tags_set(sparx5, port); - if (err) - return err; - - /* Set Max Length */ - spx5_rmw(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(ETH_MAXLEN), - DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, - sparx5, - DEV2G5_MAC_MAXLEN_CFG(port->portno)); - - /* 1G/2G5: Signal Detect configuration */ - spx5_wr(DEV2G5_PCS1G_SD_CFG_SD_POL_SET(sd_pol) | - DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(sd_sel) | - DEV2G5_PCS1G_SD_CFG_SD_ENA_SET(sd_ena), - sparx5, - DEV2G5_PCS1G_SD_CFG(port->portno)); - /* Set Pause WM hysteresis */ spx5_rmw(QSYS_PAUSE_CFG_PAUSE_START_SET(pause_start) | QSYS_PAUSE_CFG_PAUSE_STOP_SET(pause_stop) | @@ -1108,6 +1087,24 @@ int sparx5_port_init(struct sparx5 *sparx5, ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, sparx5, ANA_CL_FILTER_CTRL(port->portno)); =20 + /* Configure MAC vlan awareness */ + err =3D sparx5_port_max_tags_set(sparx5, port); + if (err) + return err; + + /* Set Max Length */ + spx5_rmw(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(ETH_MAXLEN), + DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, + sparx5, + DEV2G5_MAC_MAXLEN_CFG(port->portno)); + + /* 1G/2G5: Signal Detect configuration */ + spx5_wr(DEV2G5_PCS1G_SD_CFG_SD_POL_SET(sd_pol) | + DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(sd_sel) | + DEV2G5_PCS1G_SD_CFG_SD_ENA_SET(sd_ena), + sparx5, + DEV2G5_PCS1G_SD_CFG(port->portno)); + if (conf->portmode =3D=3D PHY_INTERFACE_MODE_QSGMII || conf->portmode =3D=3D PHY_INTERFACE_MODE_SGMII) { err =3D sparx5_serdes_set(sparx5, port, conf); --=20 2.34.1