From nobody Thu Nov 28 00:32:36 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFE70207A2F; Wed, 6 Nov 2024 19:18:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730920695; cv=none; b=uZ3aAej3OVB5gp0aeBjEwoag8kk/rEXVJHe9NgQkZoeKf4EYG+WQU7do0pXCWMaFIM/Pz3z+YonYnmg06xRMVG1zoC1kS0rhcZxtHP6AICF4BeeVWmfd4/ZjvhitdfEgHQUsYBTGsFhiV2RanfanXn78MugBxzKMngfDsxX/I5U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730920695; c=relaxed/simple; bh=oU863Kwn7GFPSRJfsJTS+xW4A//cqLjSy0be7pAvEak=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=IMjU6MdZkJ1vFABB8pGs7WAgyajyGgDyFjgHZYRwzkSvnmZ7ow604UfwMv11PKeGolBIjzdYztrDrs1bydSGsFV3t7SeHEHsI1n5DTwGNt7gRhfi3GCEG5Qfnc3CUMILG5wATXMNNBowaWZFHpyxOJQSYGctw/Ixps3RnApN8Eo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=b1kIuSeU; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="b1kIuSeU" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1730920694; x=1762456694; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=oU863Kwn7GFPSRJfsJTS+xW4A//cqLjSy0be7pAvEak=; b=b1kIuSeU2EaCzwbAreO5ZZNTxKDwKuHYDtNQ8Wn61GAnax2pp70RzTBM oXe7zhD5RIt6+SuZ29b7wSz/d+RQ/Ki/qmt5b7w/BRVF8KDyNRGfeFBVH ogEHdOwnjS0IG9cL4pk4LY+HE2k40kcropTn+M9gmZ+w7fyXDHd6cuonY U+xex99UYFRvY4mZ4BJKy/XRRc2VGG98i37C+7q4GHKUI7nsM6k9Ahbnl ZZcBRQp4otxGCIVPaYgGIOkeFwEdaP6OL0mX6ra5hswsMM+aV5rWp0vy0 wEFApHJFipGS/08BgFezJJffqSORGx6slggzeyRNQs7viCf/vRVuHNKfa w==; X-CSE-ConnectionGUID: ZmZl/QlxSRaWd1IoElCqFw== X-CSE-MsgGUID: tmB5CBhDRj+1r6TTcTSFkQ== X-IronPort-AV: E=Sophos;i="6.11,263,1725346800"; d="scan'208";a="34481087" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 06 Nov 2024 12:18:13 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 6 Nov 2024 12:17:05 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 6 Nov 2024 12:17:03 -0700 From: Daniel Machon Date: Wed, 6 Nov 2024 20:16:39 +0100 Subject: [PATCH net-next 1/7] net: sparx5: do some preparation work Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241106-sparx5-lan969x-switch-driver-4-v1-1-f7f7316436bd@microchip.com> References: <20241106-sparx5-lan969x-switch-driver-4-v1-0-f7f7316436bd@microchip.com> In-Reply-To: <20241106-sparx5-lan969x-switch-driver-4-v1-0-f7f7316436bd@microchip.com> To: , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , "Lars Povlsen" , Steen Hegelund , Horatiu Vultur , Russell King , CC: , , X-Mailer: b4 0.14-dev The sparx5_port_init() does initial configuration of a variety of different features and options for each port. Some are shared for all types of devices, some are not. As it is now, common configuration is done after configuration of low-speed devices. This will not work when adding RGMII support in a subsequent patch. In preparation for lan969x RGMII support, move a block of code, that configures 2g5 devices, down. This ensures that the configuration common to all devices is done before configuration of 2g5, 5g, 10g and 25g devices. Also, expose the two symbols: SPX5_ETYPE_TAG_C and SPX5_ETYPE_TAG_S, which will be needed by the lan969x RGMII configuration in a subsequent patch. Reviewed-by: Steen Hegelund Reviewed-by: Horatiu Vultur Signed-off-by: Daniel Machon --- .../net/ethernet/microchip/sparx5/sparx5_main.h | 3 ++ .../net/ethernet/microchip/sparx5/sparx5_port.c | 39 ++++++++++--------= ---- 2 files changed, 21 insertions(+), 21 deletions(-) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h b/drivers/= net/ethernet/microchip/sparx5/sparx5_main.h index 146bdc938adc..91ae383a5555 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h @@ -134,6 +134,9 @@ enum sparx5_feature { =20 #define SPARX5_MAX_PTP_ID 512 =20 +#define SPX5_ETYPE_TAG_C 0x8100 +#define SPX5_ETYPE_TAG_S 0x88a8 + struct sparx5; =20 struct sparx5_calendar_data { diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c b/drivers/= net/ethernet/microchip/sparx5/sparx5_port.c index 1401761c6251..bb04c2ccf112 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c @@ -12,9 +12,6 @@ #include "sparx5_main.h" #include "sparx5_port.h" =20 -#define SPX5_ETYPE_TAG_C 0x8100 -#define SPX5_ETYPE_TAG_S 0x88a8 - #define SPX5_WAIT_US 1000 #define SPX5_WAIT_MAX_US 2000 =20 @@ -1067,24 +1064,6 @@ int sparx5_port_init(struct sparx5 *sparx5, if (err) return err; =20 - /* Configure MAC vlan awareness */ - err =3D sparx5_port_max_tags_set(sparx5, port); - if (err) - return err; - - /* Set Max Length */ - spx5_rmw(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(ETH_MAXLEN), - DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, - sparx5, - DEV2G5_MAC_MAXLEN_CFG(port->portno)); - - /* 1G/2G5: Signal Detect configuration */ - spx5_wr(DEV2G5_PCS1G_SD_CFG_SD_POL_SET(sd_pol) | - DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(sd_sel) | - DEV2G5_PCS1G_SD_CFG_SD_ENA_SET(sd_ena), - sparx5, - DEV2G5_PCS1G_SD_CFG(port->portno)); - /* Set Pause WM hysteresis */ spx5_rmw(QSYS_PAUSE_CFG_PAUSE_START_SET(pause_start) | QSYS_PAUSE_CFG_PAUSE_STOP_SET(pause_stop) | @@ -1108,6 +1087,24 @@ int sparx5_port_init(struct sparx5 *sparx5, ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, sparx5, ANA_CL_FILTER_CTRL(port->portno)); =20 + /* Configure MAC vlan awareness */ + err =3D sparx5_port_max_tags_set(sparx5, port); + if (err) + return err; + + /* Set Max Length */ + spx5_rmw(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(ETH_MAXLEN), + DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, + sparx5, + DEV2G5_MAC_MAXLEN_CFG(port->portno)); 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Wed, 6 Nov 2024 12:17:08 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 6 Nov 2024 12:17:06 -0700 From: Daniel Machon Date: Wed, 6 Nov 2024 20:16:40 +0100 Subject: [PATCH net-next 2/7] net: sparx5: add function for RGMII port check Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241106-sparx5-lan969x-switch-driver-4-v1-2-f7f7316436bd@microchip.com> References: <20241106-sparx5-lan969x-switch-driver-4-v1-0-f7f7316436bd@microchip.com> In-Reply-To: <20241106-sparx5-lan969x-switch-driver-4-v1-0-f7f7316436bd@microchip.com> To: , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , "Lars Povlsen" , Steen Hegelund , Horatiu Vultur , Russell King , CC: , , X-Mailer: b4 0.14-dev The lan969x device contains two RGMII interfaces, sitting at port 28 and 29. Add function: is_port_rgmii() to the match data ops, that checks if a given port is an RGMII port or not. For Sparx5, this function always returns false. Reviewed-by: Steen Hegelund Reviewed-by: Horatiu Vultur Signed-off-by: Daniel Machon --- drivers/net/ethernet/microchip/lan969x/lan969x.c | 1 + drivers/net/ethernet/microchip/lan969x/lan969x.h | 5 +++++ drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 1 + drivers/net/ethernet/microchip/sparx5/sparx5_main.h | 1 + drivers/net/ethernet/microchip/sparx5/sparx5_port.h | 5 +++++ 5 files changed, 13 insertions(+) diff --git a/drivers/net/ethernet/microchip/lan969x/lan969x.c b/drivers/net= /ethernet/microchip/lan969x/lan969x.c index 79e5bcefbd73..8ac2652ef22c 100644 --- a/drivers/net/ethernet/microchip/lan969x/lan969x.c +++ b/drivers/net/ethernet/microchip/lan969x/lan969x.c @@ -326,6 +326,7 @@ static const struct sparx5_ops lan969x_ops =3D { .is_port_5g =3D &lan969x_port_is_5g, .is_port_10g =3D &lan969x_port_is_10g, .is_port_25g =3D &lan969x_port_is_25g, + .is_port_rgmii =3D &lan969x_port_is_rgmii, .get_port_dev_index =3D &lan969x_port_dev_mapping, .get_port_dev_bit =3D &lan969x_get_dev_mode_bit, .get_hsch_max_group_rate =3D &lan969x_get_hsch_max_group_rate, diff --git a/drivers/net/ethernet/microchip/lan969x/lan969x.h b/drivers/net= /ethernet/microchip/lan969x/lan969x.h index 7ce047ad9ca4..47e2adce1bbb 100644 --- a/drivers/net/ethernet/microchip/lan969x/lan969x.h +++ b/drivers/net/ethernet/microchip/lan969x/lan969x.h @@ -51,6 +51,11 @@ static inline bool lan969x_port_is_25g(int portno) return false; } =20 +static inline bool lan969x_port_is_rgmii(int portno) +{ + return portno =3D=3D 28 || portno =3D=3D 29; +} + /* lan969x_calendar.c */ int lan969x_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, struct sparx5_calendar_data *data); diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c b/drivers/= net/ethernet/microchip/sparx5/sparx5_main.c index 4f2d5413a64f..1c12ea0e6fd3 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c @@ -1070,6 +1070,7 @@ static const struct sparx5_ops sparx5_ops =3D { .is_port_5g =3D &sparx5_port_is_5g, .is_port_10g =3D &sparx5_port_is_10g, .is_port_25g =3D &sparx5_port_is_25g, + .is_port_rgmii =3D &sparx5_port_is_rgmii, .get_port_dev_index =3D &sparx5_port_dev_mapping, .get_port_dev_bit =3D &sparx5_port_dev_mapping, .get_hsch_max_group_rate =3D &sparx5_get_hsch_max_group_rate, diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h b/drivers/= net/ethernet/microchip/sparx5/sparx5_main.h index 91ae383a5555..a622c01930e7 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h @@ -313,6 +313,7 @@ struct sparx5_ops { bool (*is_port_5g)(int portno); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241106-sparx5-lan969x-switch-driver-4-v1-3-f7f7316436bd@microchip.com> References: <20241106-sparx5-lan969x-switch-driver-4-v1-0-f7f7316436bd@microchip.com> In-Reply-To: <20241106-sparx5-lan969x-switch-driver-4-v1-0-f7f7316436bd@microchip.com> To: , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , "Lars Povlsen" , Steen Hegelund , Horatiu Vultur , Russell King , CC: , , X-Mailer: b4 0.14-dev Now that we can check if a given port is an RGMII port, use it in the following cases: - To set RGMII PHY modes for RGMII port devices. - To avoid checking for a SerDes node in the devicetree, when the port is an RGMII port. - To bail out of sparx5_port_init() when the common configuration is done. Reviewed-by: Steen Hegelund Reviewed-by: Horatiu Vultur Signed-off-by: Daniel Machon --- .../net/ethernet/microchip/sparx5/sparx5_main.c | 28 +++++++++++++++---= ---- .../net/ethernet/microchip/sparx5/sparx5_port.c | 3 +++ 2 files changed, 23 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c b/drivers/= net/ethernet/microchip/sparx5/sparx5_main.c index 1c12ea0e6fd3..23bcef0970a4 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c @@ -311,10 +311,13 @@ static int sparx5_create_port(struct sparx5 *sparx5, struct initial_port_config *config) { struct sparx5_port *spx5_port; + const struct sparx5_ops *ops; struct net_device *ndev; struct phylink *phylink; int err; =20 + ops =3D sparx5->data->ops; + ndev =3D sparx5_create_netdev(sparx5, config->portno); if (IS_ERR(ndev)) { dev_err(sparx5->dev, "Could not create net device: %02u\n", @@ -355,6 +358,9 @@ static int sparx5_create_port(struct sparx5 *sparx5, MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD | MAC_2500FD | MAC_5000FD | MAC_10000FD | MAC_25000FD; =20 + if (ops->is_port_rgmii(spx5_port->portno)) + phy_interface_set_rgmii(spx5_port->phylink_config.supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_SGMII, spx5_port->phylink_config.supported_interfaces); __set_bit(PHY_INTERFACE_MODE_QSGMII, @@ -831,6 +837,7 @@ static int mchp_sparx5_probe(struct platform_device *pd= ev) struct initial_port_config *configs, *config; struct device_node *np =3D pdev->dev.of_node; struct device_node *ports, *portnp; + const struct sparx5_ops *ops; struct reset_control *reset; struct sparx5 *sparx5; int idx =3D 0, err =3D 0; @@ -852,6 +859,7 @@ static int mchp_sparx5_probe(struct platform_device *pd= ev) return -EINVAL; =20 regs =3D sparx5->data->regs; + ops =3D sparx5->data->ops; =20 /* Do switch core reset if available */ reset =3D devm_reset_control_get_optional_shared(&pdev->dev, "switch"); @@ -881,7 +889,7 @@ static int mchp_sparx5_probe(struct platform_device *pd= ev) =20 for_each_available_child_of_node(ports, portnp) { struct sparx5_port_config *conf; - struct phy *serdes; + struct phy *serdes =3D NULL; u32 portno; =20 err =3D of_property_read_u32(portnp, "reg", &portno); @@ -911,13 +919,17 @@ static int mchp_sparx5_probe(struct platform_device *= pdev) conf->sd_sgpio =3D ~0; else sparx5->sd_sgpio_remapping =3D true; - serdes =3D devm_of_phy_get(sparx5->dev, portnp, NULL); - if (IS_ERR(serdes)) { - err =3D dev_err_probe(sparx5->dev, PTR_ERR(serdes), - "port %u: missing serdes\n", - portno); - of_node_put(portnp); - goto cleanup_config; + /* There is no SerDes node for RGMII ports. */ + if (!ops->is_port_rgmii(portno)) { + serdes =3D devm_of_phy_get(sparx5->dev, portnp, NULL); + if (IS_ERR(serdes)) { + err =3D dev_err_probe(sparx5->dev, + PTR_ERR(serdes), + "port %u: missing serdes\n", + portno); + of_node_put(portnp); + goto cleanup_config; + } } config->portno =3D portno; config->node =3D portnp; diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c b/drivers/= net/ethernet/microchip/sparx5/sparx5_port.c index bb04c2ccf112..61e81b061268 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c @@ -1087,6 +1087,9 @@ int sparx5_port_init(struct sparx5 *sparx5, ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, sparx5, ANA_CL_FILTER_CTRL(port->portno)); =20 + if (ops->is_port_rgmii(port->portno)) + return 0; + /* Configure MAC vlan awareness */ err =3D sparx5_port_max_tags_set(sparx5, port); if (err) --=20 2.34.1 From nobody Thu Nov 28 00:32:36 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B550020968D; Wed, 6 Nov 2024 19:17:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730920676; cv=none; b=KUotmYJfaTpiZJ+w8NpDWviBCARnsd5Mcp+EtbIt14DtP2PVdi/ZyALmukCZAIbNL+D0Jk++j6dcBZ3itBwRt7MhT10DnJA6Nt1JVBGj5W075yxbvV89NrmirulK+FBy5MF4Zi2bF04yeo6zYf9uIUc7hIci7W6vtN4ouqsk4Rg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730920676; c=relaxed/simple; bh=iXbLB9lnsnCTXauFFkO4eWvZ3JHaQcUHCqsFwidPQ7Q=; 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Wed, 6 Nov 2024 12:17:13 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 6 Nov 2024 12:17:11 -0700 From: Daniel Machon Date: Wed, 6 Nov 2024 20:16:42 +0100 Subject: [PATCH net-next 4/7] net: sparx5: use phy_interface_mode_is_rgmii() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241106-sparx5-lan969x-switch-driver-4-v1-4-f7f7316436bd@microchip.com> References: <20241106-sparx5-lan969x-switch-driver-4-v1-0-f7f7316436bd@microchip.com> In-Reply-To: <20241106-sparx5-lan969x-switch-driver-4-v1-0-f7f7316436bd@microchip.com> To: , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , "Lars Povlsen" , Steen Hegelund , Horatiu Vultur , Russell King , CC: , , X-Mailer: b4 0.14-dev Use the phy_interface_mode_is_rgmii() function to check if the PHY mode is set to any of: RGMII, RGMII_ID, RGMII_RXID or RGMII_TXID in the following places: - When selecting the MAC PCS, make sure we return NULL in case the PHY mode is RGMII (as there is no PCS to configure). - When doing a port config, make sure we do not do the low-speed device configuration, in case the PHY mode is RGMII. Note that we could also have used is_port_rgmii() here, but it makes more sense to me to use the phylink provided functions, as we are called by phylink, and the RGMII modes have already been validated against the supported interfaces of the ports. Reviewed-by: Steen Hegelund Reviewed-by: Horatiu Vultur Signed-off-by: Daniel Machon --- drivers/net/ethernet/microchip/sparx5/sparx5_phylink.c | 3 +++ drivers/net/ethernet/microchip/sparx5/sparx5_port.c | 3 ++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_phylink.c b/drive= rs/net/ethernet/microchip/sparx5/sparx5_phylink.c index f8562c1a894d..cb55e05e5611 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_phylink.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_phylink.c @@ -32,6 +32,9 @@ sparx5_phylink_mac_select_pcs(struct phylink_config *conf= ig, { struct sparx5_port *port =3D netdev_priv(to_net_dev(config->dev)); =20 + if (phy_interface_mode_is_rgmii(interface)) + return NULL; + return &port->phylink_pcs; } =20 diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c b/drivers/= net/ethernet/microchip/sparx5/sparx5_port.c index 61e81b061268..fc1ca0cc4bb7 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c @@ -991,6 +991,7 @@ int sparx5_port_config(struct sparx5 *sparx5, struct sparx5_port *port, struct sparx5_port_config *conf) { + bool rgmii =3D phy_interface_mode_is_rgmii(conf->phy_mode); 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Wed, 6 Nov 2024 12:17:16 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 6 Nov 2024 12:17:14 -0700 From: Daniel Machon Date: Wed, 6 Nov 2024 20:16:43 +0100 Subject: [PATCH net-next 5/7] net: sparx5: verify RGMII speeds Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241106-sparx5-lan969x-switch-driver-4-v1-5-f7f7316436bd@microchip.com> References: <20241106-sparx5-lan969x-switch-driver-4-v1-0-f7f7316436bd@microchip.com> In-Reply-To: <20241106-sparx5-lan969x-switch-driver-4-v1-0-f7f7316436bd@microchip.com> To: , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , "Lars Povlsen" , Steen Hegelund , Horatiu Vultur , Russell King , CC: , , X-Mailer: b4 0.14-dev When doing a port config, we verify the port speed against the PHY mode and supported speeds of that PHY mode. Add checks for the four RGMII phy modes: RGMII, RGMII_ID, RGMII_TXID and RGMII_RXID. Reviewed-by: Steen Hegelund Reviewed-by: Horatiu Vultur Signed-off-by: Daniel Machon --- drivers/net/ethernet/microchip/sparx5/sparx5_port.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c b/drivers/= net/ethernet/microchip/sparx5/sparx5_port.c index fc1ca0cc4bb7..bd1fa5da47d7 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c @@ -254,6 +254,15 @@ static int sparx5_port_verify_speed(struct sparx5 *spa= rx5, conf->speed !=3D SPEED_25000)) return sparx5_port_error(port, conf, SPX5_PERR_SPEED); break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + if (conf->speed !=3D SPEED_1000 && + conf->speed !=3D SPEED_100 && + conf->speed !=3D SPEED_10) + return sparx5_port_error(port, conf, SPX5_PERR_SPEED); + break; default: return sparx5_port_error(port, conf, SPX5_PERR_IFTYPE); } --=20 2.34.1 From nobody Thu Nov 28 00:32:36 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E0BF209F4F; Wed, 6 Nov 2024 19:17:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730920678; cv=none; b=kbbuf50lgWJGjVaJCF1v/eliEjVoRLTr3uuBf8RQjrm4RBrzvvyCR9ex7GRxMxCdY6LNJYZNi6IyWj0cV75/AdhV6YYQfr7MmrauDtWO/uZBdW3pyOe+8Flhzd1TXpveSFVzHlBcvxvBqQZgMizCZzL5Pl2PPxhLM0zwH1jQ11k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730920678; c=relaxed/simple; bh=b45vVtSN0yrCRwGiJJiPW1/u7sRXUetE4/jESrNuotk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=mhFp1xcUu3+JGZS4mxlahOobZlyH20UWVuasfBfVBFV6xRb4kVIpYu6t3xlUPc0Q2mUZW2jyqyRfUHhLV0Y5Ey9A1F110ort/ew+etyo1WJtIXXjIuj5DFXwdaUyDRPqWjAjusF8V4wa7FUFFxF6QJFef2B9w7Q1nUFgzzdS2G8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=mMR4h1Jt; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="mMR4h1Jt" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1730920676; x=1762456676; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=b45vVtSN0yrCRwGiJJiPW1/u7sRXUetE4/jESrNuotk=; b=mMR4h1JtJUGOGoBdEWPHFhosh2JENtdJNreJxt7FMLA1+MVwQJXd2fEQ OQNU3+scNuszGpg1t+ov5WtjztmMOlUluhQyvWsJaE9PWhDWcLvg3894S zT4U94Ml9drHKkxd2PUz1bLoUv7XB5+HCPIgfU4tfJvuBfo6BiuyQB9pP calT50A4ByWy0Oug73Aj1B3uWy6V66nKeBNqHXSda921QB9mHfOS+ZiXP MrJK1GvdHyd/d56/0QXoK8LjqddHl+j0cUMR1hfA4rjUJiWAykNvsm43n 6Syr4WzR7uTqInDi5+7kCaq7tIFy0Ly5R8qJj4QSKVQA8/COuw4CSV3fq w==; X-CSE-ConnectionGUID: R5B6jnU1TTWc0t0C0FxLpw== X-CSE-MsgGUID: /0jBs2k+TyeNd90/nzhilg== X-IronPort-AV: E=Sophos;i="6.11,263,1725346800"; d="scan'208";a="37447986" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 06 Nov 2024 12:17:47 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 6 Nov 2024 12:17:19 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 6 Nov 2024 12:17:16 -0700 From: Daniel Machon Date: Wed, 6 Nov 2024 20:16:44 +0100 Subject: [PATCH net-next 6/7] net: lan969x: add RGMII registers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241106-sparx5-lan969x-switch-driver-4-v1-6-f7f7316436bd@microchip.com> References: <20241106-sparx5-lan969x-switch-driver-4-v1-0-f7f7316436bd@microchip.com> In-Reply-To: <20241106-sparx5-lan969x-switch-driver-4-v1-0-f7f7316436bd@microchip.com> To: , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , "Lars Povlsen" , Steen Hegelund , Horatiu Vultur , Russell King , CC: , , X-Mailer: b4 0.14-dev Configuration of RGMII is done by configuring the GPIO and clock settings in the HSIOWRAP target, and configuring the RGMII port devices in the DEVRGMII target. Both targets contain registers replicated for the number of RGMII port devices, which is two. Add said targets and register macros required to configure RGMII. Reviewed-by: Steen Hegelund Reviewed-by: Horatiu Vultur Signed-off-by: Daniel Machon --- drivers/net/ethernet/microchip/lan969x/lan969x.c | 3 + .../ethernet/microchip/sparx5/sparx5_main_regs.h | 145 +++++++++++++++++= ++++ 2 files changed, 148 insertions(+) diff --git a/drivers/net/ethernet/microchip/lan969x/lan969x.c b/drivers/net= /ethernet/microchip/lan969x/lan969x.c index 8ac2652ef22c..cfd57eb42c04 100644 --- a/drivers/net/ethernet/microchip/lan969x/lan969x.c +++ b/drivers/net/ethernet/microchip/lan969x/lan969x.c @@ -90,9 +90,12 @@ static const struct sparx5_main_io_resource lan969x_main= _iomap[] =3D { { TARGET_DEV2G5 + 27, 0x30d8000, 1 }, /* 0xe30d8000 */ { TARGET_DEV10G + 9, 0x30dc000, 1 }, /* 0xe30dc000 */ { TARGET_PCS10G_BR + 9, 0x30e0000, 1 }, /* 0xe30e0000 */ + { TARGET_DEVRGMII, 0x30e4000, 1 }, /* 0xe30e4000 */ + { TARGET_DEVRGMII + 1, 0x30e8000, 1 }, /* 0xe30e8000 */ { TARGET_DSM, 0x30ec000, 1 }, /* 0xe30ec000 */ { TARGET_PORT_CONF, 0x30f0000, 1 }, /* 0xe30f0000 */ { TARGET_ASM, 0x3200000, 1 }, /* 0xe3200000 */ + { TARGET_HSIO_WRAP, 0x3408000, 1 }, /* 0xe3408000 */ }; =20 static struct sparx5_sdlb_group lan969x_sdlb_groups[LAN969X_SDLB_GRP_CNT] = =3D { diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h b/dri= vers/net/ethernet/microchip/sparx5/sparx5_main_regs.h index 561344f19062..d9ef4ef137b8 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h @@ -37,6 +37,7 @@ enum sparx5_target { TARGET_FDMA =3D 117, TARGET_GCB =3D 118, TARGET_HSCH =3D 119, + TARGET_HSIO_WRAP =3D 120, TARGET_LRN =3D 122, TARGET_PCEP =3D 129, TARGET_PCS10G_BR =3D 132, @@ -54,6 +55,7 @@ enum sparx5_target { TARGET_VCAP_SUPER =3D 326, TARGET_VOP =3D 327, TARGET_XQS =3D 331, + TARGET_DEVRGMII =3D 392, NUM_TARGETS =3D 517 }; =20 @@ -5367,6 +5369,69 @@ extern const struct sparx5_regs *regs; #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_GET(x)\ FIELD_GET(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, x) =20 +/* LAN969X ONLY */ +/* HSIOWRAP:XMII_CFG:XMII_CFG */ +#define HSIO_WRAP_XMII_CFG(g) = \ + __REG(TARGET_HSIO_WRAP, 0, 1, 116, g, 2, 20, 0, 0, 1, 4) + +#define HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG GENMASK(2, 1) +#define HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG_SET(x)\ + FIELD_PREP(HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG, x) +#define HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG_GET(x)\ + FIELD_GET(HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG, x) + +/* LAN969X ONLY */ +/* HSIOWRAP:XMII_CFG:RGMII_CFG */ +#define HSIO_WRAP_RGMII_CFG(g) = \ + __REG(TARGET_HSIO_WRAP, 0, 1, 116, g, 2, 20, 4, 0, 1, 4) + +#define HSIO_WRAP_RGMII_CFG_TX_CLK_CFG GENMASK(4, 2) +#define HSIO_WRAP_RGMII_CFG_TX_CLK_CFG_SET(x)\ + FIELD_PREP(HSIO_WRAP_RGMII_CFG_TX_CLK_CFG, x) +#define HSIO_WRAP_RGMII_CFG_TX_CLK_CFG_GET(x)\ + FIELD_GET(HSIO_WRAP_RGMII_CFG_TX_CLK_CFG, x) + +#define HSIO_WRAP_RGMII_CFG_RGMII_TX_RST BIT(1) +#define HSIO_WRAP_RGMII_CFG_RGMII_TX_RST_SET(x)\ + FIELD_PREP(HSIO_WRAP_RGMII_CFG_RGMII_TX_RST, x) +#define HSIO_WRAP_RGMII_CFG_RGMII_TX_RST_GET(x)\ + FIELD_GET(HSIO_WRAP_RGMII_CFG_RGMII_TX_RST, x) + +#define HSIO_WRAP_RGMII_CFG_RGMII_RX_RST BIT(0) +#define HSIO_WRAP_RGMII_CFG_RGMII_RX_RST_SET(x)\ + FIELD_PREP(HSIO_WRAP_RGMII_CFG_RGMII_RX_RST, x) +#define HSIO_WRAP_RGMII_CFG_RGMII_RX_RST_GET(x)\ + FIELD_GET(HSIO_WRAP_RGMII_CFG_RGMII_RX_RST, x) + +/* LAN969X ONLY */ +/* HSIOWRAP:XMII_CFG:DLL_CFG */ +#define HSIO_WRAP_DLL_CFG(g, r) = \ + __REG(TARGET_HSIO_WRAP, 0, 1, 116, g, 2, 20, 12, r, 2, 4) + +#define HSIO_WRAP_DLL_CFG_DLL_ENA BIT(19) +#define HSIO_WRAP_DLL_CFG_DLL_ENA_SET(x)\ + FIELD_PREP(HSIO_WRAP_DLL_CFG_DLL_ENA, x) +#define HSIO_WRAP_DLL_CFG_DLL_ENA_GET(x)\ + FIELD_GET(HSIO_WRAP_DLL_CFG_DLL_ENA, x) + +#define HSIO_WRAP_DLL_CFG_DLL_CLK_ENA BIT(18) +#define HSIO_WRAP_DLL_CFG_DLL_CLK_ENA_SET(x)\ + FIELD_PREP(HSIO_WRAP_DLL_CFG_DLL_CLK_ENA, x) +#define HSIO_WRAP_DLL_CFG_DLL_CLK_ENA_GET(x)\ + FIELD_GET(HSIO_WRAP_DLL_CFG_DLL_CLK_ENA, x) + +#define HSIO_WRAP_DLL_CFG_DLL_CLK_SEL GENMASK(17, 15) +#define HSIO_WRAP_DLL_CFG_DLL_CLK_SEL_SET(x)\ + FIELD_PREP(HSIO_WRAP_DLL_CFG_DLL_CLK_SEL, x) +#define HSIO_WRAP_DLL_CFG_DLL_CLK_SEL_GET(x)\ + FIELD_GET(HSIO_WRAP_DLL_CFG_DLL_CLK_SEL, x) + +#define HSIO_WRAP_DLL_CFG_DLL_RST BIT(0) +#define HSIO_WRAP_DLL_CFG_DLL_RST_SET(x)\ + FIELD_PREP(HSIO_WRAP_DLL_CFG_DLL_RST, x) +#define HSIO_WRAP_DLL_CFG_DLL_RST_GET(x)\ + FIELD_GET(HSIO_WRAP_DLL_CFG_DLL_RST, x) + /* LRN:COMMON:COMMON_ACCESS_CTRL */ #define LRN_COMMON_ACCESS_CTRL = \ __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 0, 0, 1, 4) @@ -8110,4 +8175,84 @@ extern const struct sparx5_regs *regs; #define XQS_CNT(g) = \ __REG(TARGET_XQS, 0, 1, 0, g, 1024, 4, 0, 0, 1, 4) =20 +/* LAN969X ONLY */ +/* DEV1G:DEV_CFG_STATUS:DEV_RST_CTRL */ +#define DEVRGMII_DEV_RST_CTRL(t) = \ + __REG(TARGET_DEVRGMII, t, 2, 0, 0, 1, 36, 0, 0, 1, 4) + +#define DEVRGMII_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20) +#define DEVRGMII_DEV_RST_CTRL_SPEED_SEL_SET(x)\ + FIELD_PREP(DEVRGMII_DEV_RST_CTRL_SPEED_SEL, x) +#define DEVRGMII_DEV_RST_CTRL_SPEED_SEL_GET(x)\ + FIELD_GET(DEVRGMII_DEV_RST_CTRL_SPEED_SEL, x) + +/* LAN969X ONLY */ +/* DEV1G:MAC_CFG_STATUS:MAC_ENA_CFG */ +#define DEVRGMII_MAC_ENA_CFG(t) = \ + __REG(TARGET_DEVRGMII, t, 2, 36, 0, 1, 36, 0, 0, 1, 4) + +#define DEVRGMII_MAC_ENA_CFG_RX_ENA BIT(4) +#define DEVRGMII_MAC_ENA_CFG_RX_ENA_SET(x)\ + FIELD_PREP(DEVRGMII_MAC_ENA_CFG_RX_ENA, x) +#define DEVRGMII_MAC_ENA_CFG_RX_ENA_GET(x)\ + FIELD_GET(DEVRGMII_MAC_ENA_CFG_RX_ENA, x) + +#define DEVRGMII_MAC_ENA_CFG_TX_ENA BIT(0) +#define DEVRGMII_MAC_ENA_CFG_TX_ENA_SET(x)\ + FIELD_PREP(DEVRGMII_MAC_ENA_CFG_TX_ENA, x) +#define DEVRGMII_MAC_ENA_CFG_TX_ENA_GET(x)\ + FIELD_GET(DEVRGMII_MAC_ENA_CFG_TX_ENA, x) + +/* LAN969X ONLY */ +/* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG */ +#define DEVRGMII_MAC_TAGS_CFG(t) = \ + __REG(TARGET_DEVRGMII, t, 2, 36, 0, 1, 36, 12, 0, 1, 4) + +#define DEVRGMII_MAC_TAGS_CFG_TAG_ID GENMASK(31, 16) +#define DEVRGMII_MAC_TAGS_CFG_TAG_ID_SET(x)\ + FIELD_PREP(DEVRGMII_MAC_TAGS_CFG_TAG_ID, x) +#define DEVRGMII_MAC_TAGS_CFG_TAG_ID_GET(x)\ + FIELD_GET(DEVRGMII_MAC_TAGS_CFG_TAG_ID, x) + +#define DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA BIT(3) +#define DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_SET(x)\ + FIELD_PREP(DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x) +#define DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_GET(x)\ + FIELD_GET(DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x) + +#define DEVRGMII_MAC_TAGS_CFG_PB_ENA GENMASK(2, 1) +#define DEVRGMII_MAC_TAGS_CFG_PB_ENA_SET(x)\ + FIELD_PREP(DEVRGMII_MAC_TAGS_CFG_PB_ENA, x) +#define DEVRGMII_MAC_TAGS_CFG_PB_ENA_GET(x)\ + FIELD_GET(DEVRGMII_MAC_TAGS_CFG_PB_ENA, x) + +#define DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA BIT(0) +#define DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\ + FIELD_PREP(DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA, x) +#define DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\ + FIELD_GET(DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA, x) + +/* LAN969X ONLY */ +/* DEV1G:MAC_CFG_STATUS:MAC_IFG_CFG */ +#define DEVRGMII_MAC_IFG_CFG(t) = \ + __REG(TARGET_DEVRGMII, t, 2, 36, 0, 1, 36, 24, 0, 1, 4) + +#define DEVRGMII_MAC_IFG_CFG_TX_IFG GENMASK(12, 8) +#define DEVRGMII_MAC_IFG_CFG_TX_IFG_SET(x)\ + FIELD_PREP(DEVRGMII_MAC_IFG_CFG_TX_IFG, x) +#define DEVRGMII_MAC_IFG_CFG_TX_IFG_GET(x)\ + FIELD_GET(DEVRGMII_MAC_IFG_CFG_TX_IFG, x) + +#define DEVRGMII_MAC_IFG_CFG_RX_IFG2 GENMASK(7, 4) +#define DEVRGMII_MAC_IFG_CFG_RX_IFG2_SET(x)\ + FIELD_PREP(DEVRGMII_MAC_IFG_CFG_RX_IFG2, x) +#define DEVRGMII_MAC_IFG_CFG_RX_IFG2_GET(x)\ + FIELD_GET(DEVRGMII_MAC_IFG_CFG_RX_IFG2, x) + +#define DEVRGMII_MAC_IFG_CFG_RX_IFG1 GENMASK(3, 0) +#define DEVRGMII_MAC_IFG_CFG_RX_IFG1_SET(x)\ + FIELD_PREP(DEVRGMII_MAC_IFG_CFG_RX_IFG1, x) +#define DEVRGMII_MAC_IFG_CFG_RX_IFG1_GET(x)\ + FIELD_GET(DEVRGMII_MAC_IFG_CFG_RX_IFG1, x) + #endif /* _SPARX5_MAIN_REGS_H_ */ --=20 2.34.1 From nobody Thu Nov 28 00:32:36 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 70553207A12; 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X-CSE-ConnectionGUID: R5B6jnU1TTWc0t0C0FxLpw== X-CSE-MsgGUID: PpcyY+1cRIa5I2fT9W4UDQ== X-IronPort-AV: E=Sophos;i="6.11,263,1725346800"; d="scan'208";a="37447987" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 06 Nov 2024 12:17:47 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 6 Nov 2024 12:17:23 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 6 Nov 2024 12:17:19 -0700 From: Daniel Machon Date: Wed, 6 Nov 2024 20:16:45 +0100 Subject: [PATCH net-next 7/7] net: lan969x: add function for configuring RGMII port devices Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241106-sparx5-lan969x-switch-driver-4-v1-7-f7f7316436bd@microchip.com> References: <20241106-sparx5-lan969x-switch-driver-4-v1-0-f7f7316436bd@microchip.com> In-Reply-To: <20241106-sparx5-lan969x-switch-driver-4-v1-0-f7f7316436bd@microchip.com> To: , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , "Lars Povlsen" , Steen Hegelund , Horatiu Vultur , Russell King , CC: , , X-Mailer: b4 0.14-dev The lan969x switch device includes two RGMII interfaces (port 28 and 29) supporting data speeds of 1 Gbps, 100 Mbps and 10 Mbps. Add new function: rgmii_config() to the match data ops, and use it to configure RGMII port devices when doing a port config. On Sparx5, the RGMII configuration will always be skipped, as the is_port_rgmii() will return false. Reviewed-by: Steen Hegelund Reviewed-by: Horatiu Vultur Signed-off-by: Daniel Machon --- drivers/net/ethernet/microchip/lan969x/lan969x.c | 105 +++++++++++++++++= ++++ .../net/ethernet/microchip/sparx5/sparx5_main.h | 2 + .../net/ethernet/microchip/sparx5/sparx5_port.c | 3 + 3 files changed, 110 insertions(+) diff --git a/drivers/net/ethernet/microchip/lan969x/lan969x.c b/drivers/net= /ethernet/microchip/lan969x/lan969x.c index cfd57eb42c04..0681913a05d4 100644 --- a/drivers/net/ethernet/microchip/lan969x/lan969x.c +++ b/drivers/net/ethernet/microchip/lan969x/lan969x.c @@ -9,6 +9,17 @@ #define LAN969X_SDLB_GRP_CNT 5 #define LAN969X_HSCH_LEAK_GRP_CNT 4 =20 +#define LAN969X_RGMII_TX_CLK_DISABLE 0 /* Disable TX clock generation*/ +#define LAN969X_RGMII_TX_CLK_125MHZ 1 /* 1000Mbps */ +#define LAN969X_RGMII_TX_CLK_25MHZ 2 /* 100Mbps */ +#define LAN969X_RGMII_TX_CLK_2M5MHZ 3 /* 10Mbps */ +#define LAN969X_RGMII_PORT_START_IDX 28 /* Index of the first RGMII port */ +#define LAN969X_RGMII_PORT_RATE 2 /* 1000Mbps */ +#define LAN969X_RGMII_SHIFT_90DEG 3 /* Phase shift 90deg. (2 ns @ 125M= Hz) */ +#define LAN969X_RGMII_IFG_TX 4 /* TX Inter Frame Gap value */ +#define LAN969X_RGMII_IFG_RX1 5 /* RX1 Inter Frame Gap value */ +#define LAN969X_RGMII_IFG_RX2 1 /* RX2 Inter Frame Gap value */ + static const struct sparx5_main_io_resource lan969x_main_iomap[] =3D { { TARGET_CPU, 0xc0000, 0 }, /* 0xe00c0000 */ { TARGET_FDMA, 0xc0400, 0 }, /* 0xe00c0400 */ @@ -293,6 +304,99 @@ static irqreturn_t lan969x_ptp_irq_handler(int irq, vo= id *args) return IRQ_HANDLED; } =20 +static int lan969x_port_config_rgmii(struct sparx5 *sparx5, + struct sparx5_port *port, + struct sparx5_port_config *conf) +{ + int tx_clk_freq, idx =3D port->portno - LAN969X_RGMII_PORT_START_IDX; + enum sparx5_port_max_tags max_tags =3D port->max_vlan_tags; + enum sparx5_vlan_port_type vlan_type =3D port->vlan_type; + bool dtag, dotag, tx_delay =3D false, rx_delay =3D false; + u32 etype; + + tx_clk_freq =3D (conf->speed =3D=3D SPEED_10 ? LAN969X_RGMII_TX_CLK_2M5MH= Z : + conf->speed =3D=3D SPEED_100 ? LAN969X_RGMII_TX_CLK_25MHZ : + LAN969X_RGMII_TX_CLK_125MHZ); + + etype =3D (vlan_type =3D=3D SPX5_VLAN_PORT_TYPE_S_CUSTOM ? + port->custom_etype : + vlan_type =3D=3D SPX5_VLAN_PORT_TYPE_C ? + SPX5_ETYPE_TAG_C : SPX5_ETYPE_TAG_S); + + dtag =3D max_tags =3D=3D SPX5_PORT_MAX_TAGS_TWO; + dotag =3D max_tags !=3D SPX5_PORT_MAX_TAGS_NONE; + + if (conf->phy_mode =3D=3D PHY_INTERFACE_MODE_RGMII || + conf->phy_mode =3D=3D PHY_INTERFACE_MODE_RGMII_TXID) + rx_delay =3D true; + + if (conf->phy_mode =3D=3D PHY_INTERFACE_MODE_RGMII || + conf->phy_mode =3D=3D PHY_INTERFACE_MODE_RGMII_RXID) + tx_delay =3D true; + + /* Take the RGMII clock domains out of reset and set tx clock + * frequency. + */ + spx5_rmw(HSIO_WRAP_RGMII_CFG_TX_CLK_CFG_SET(tx_clk_freq) | + HSIO_WRAP_RGMII_CFG_RGMII_TX_RST_SET(0) | + HSIO_WRAP_RGMII_CFG_RGMII_RX_RST_SET(0), + HSIO_WRAP_RGMII_CFG_TX_CLK_CFG | + HSIO_WRAP_RGMII_CFG_RGMII_TX_RST | + HSIO_WRAP_RGMII_CFG_RGMII_RX_RST, + sparx5, HSIO_WRAP_RGMII_CFG(idx)); + + /* Enable the RGMII0 on the GPIOs */ + spx5_wr(HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG_SET(1), + sparx5, HSIO_WRAP_XMII_CFG(!idx)); + + /* Configure rx delay, the signal is shifted 90 degrees. */ + spx5_rmw(HSIO_WRAP_DLL_CFG_DLL_RST_SET(0) | + HSIO_WRAP_DLL_CFG_DLL_ENA_SET(1) | + HSIO_WRAP_DLL_CFG_DLL_CLK_ENA_SET(rx_delay) | + HSIO_WRAP_DLL_CFG_DLL_CLK_SEL_SET(LAN969X_RGMII_SHIFT_90DEG), + HSIO_WRAP_DLL_CFG_DLL_RST | + HSIO_WRAP_DLL_CFG_DLL_ENA | + HSIO_WRAP_DLL_CFG_DLL_CLK_ENA | + HSIO_WRAP_DLL_CFG_DLL_CLK_SEL, + sparx5, HSIO_WRAP_DLL_CFG(idx, 0)); + + /* Configure tx delay, the signal is shifted 90 degrees. */ + spx5_rmw(HSIO_WRAP_DLL_CFG_DLL_RST_SET(0) | + HSIO_WRAP_DLL_CFG_DLL_ENA_SET(1) | + HSIO_WRAP_DLL_CFG_DLL_CLK_ENA_SET(tx_delay) | + HSIO_WRAP_DLL_CFG_DLL_CLK_SEL_SET(LAN969X_RGMII_SHIFT_90DEG), + HSIO_WRAP_DLL_CFG_DLL_RST | + HSIO_WRAP_DLL_CFG_DLL_ENA | + HSIO_WRAP_DLL_CFG_DLL_CLK_ENA | + HSIO_WRAP_DLL_CFG_DLL_CLK_SEL, + sparx5, HSIO_WRAP_DLL_CFG(idx, 1)); + + /* Configure the port now */ + spx5_wr(DEVRGMII_MAC_ENA_CFG_RX_ENA_SET(1) | + DEVRGMII_MAC_ENA_CFG_TX_ENA_SET(1), + sparx5, DEVRGMII_MAC_ENA_CFG(idx)); + + /* Configure the Inter Frame Gap */ + spx5_wr(DEVRGMII_MAC_IFG_CFG_TX_IFG_SET(LAN969X_RGMII_IFG_TX) | + DEVRGMII_MAC_IFG_CFG_RX_IFG1_SET(LAN969X_RGMII_IFG_RX1) | + DEVRGMII_MAC_IFG_CFG_RX_IFG2_SET(LAN969X_RGMII_IFG_RX2), + sparx5, DEVRGMII_MAC_IFG_CFG(idx)); + + /* Configure port data rate */ + spx5_wr(DEVRGMII_DEV_RST_CTRL_SPEED_SEL_SET(LAN969X_RGMII_PORT_RATE), + sparx5, DEVRGMII_DEV_RST_CTRL(idx)); + + /* Configure VLAN awareness */ + spx5_wr(DEVRGMII_MAC_TAGS_CFG_TAG_ID_SET(etype) | + DEVRGMII_MAC_TAGS_CFG_PB_ENA_SET(dtag) | + DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(dotag) | + DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_SET(dotag), + sparx5, + DEVRGMII_MAC_TAGS_CFG(idx)); + + return 0; +} + static const struct sparx5_regs lan969x_regs =3D { .tsize =3D lan969x_tsize, .gaddr =3D lan969x_gaddr, @@ -337,6 +441,7 @@ static const struct sparx5_ops lan969x_ops =3D { .set_port_mux =3D &lan969x_port_mux_set, .ptp_irq_handler =3D &lan969x_ptp_irq_handler, .dsm_calendar_calc =3D &lan969x_dsm_calendar_calc, + .rgmii_config =3D &lan969x_port_config_rgmii, }; =20 const struct sparx5_match_data lan969x_desc =3D { diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h b/drivers/= net/ethernet/microchip/sparx5/sparx5_main.h index a622c01930e7..763c827c01f3 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h @@ -324,6 +324,8 @@ struct sparx5_ops { irqreturn_t (*ptp_irq_handler)(int irq, void *args); int (*dsm_calendar_calc)(struct sparx5 *sparx5, u32 taxi, struct sparx5_calendar_data *data); + int (*rgmii_config)(struct sparx5 *sparx5, struct sparx5_port *port, + struct sparx5_port_config *conf); }; =20 struct sparx5_main_io_resource { diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c b/drivers/= net/ethernet/microchip/sparx5/sparx5_port.c index bd1fa5da47d7..ef61e8164e21 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c @@ -1009,6 +1009,9 @@ int sparx5_port_config(struct sparx5 *sparx5, if (err) return err; =20 + if (rgmii) + ops->rgmii_config(sparx5, port, conf); + /* high speed device is already configured */ if (!rgmii && !high_speed_dev) sparx5_port_config_low_set(sparx5, port, conf); --=20 2.34.1