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Wed, 06 Nov 2024 09:52:28 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4A69qSOG001561 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 6 Nov 2024 09:52:28 GMT Received: from hu-imrashai-hyd.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 6 Nov 2024 01:52:23 -0800 From: Imran Shaik Date: Wed, 6 Nov 2024 15:21:57 +0530 Subject: [PATCH v3 2/6] clk: qcom: Add support for GPU Clock Controller on QCS8300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241106-qcs8300-mm-patches-v3-2-f611a8f87f15@quicinc.com> References: <20241106-qcs8300-mm-patches-v3-0-f611a8f87f15@quicinc.com> In-Reply-To: <20241106-qcs8300-mm-patches-v3-0-f611a8f87f15@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Ajit Pandey , Taniya Das , Jagadeesh Kona , Satya Priya Kakitapalli , , , , , Imran Shaik , Dmitry Baryshkov X-Mailer: b4 0.14.1 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: fxp6vxlsOonFPlji-A7zgjmI8sVqVnup X-Proofpoint-ORIG-GUID: fxp6vxlsOonFPlji-A7zgjmI8sVqVnup X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 priorityscore=1501 impostorscore=0 mlxscore=0 bulkscore=0 spamscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411060080 Add support to the QCS8300 GPU clock controller by extending the SA8775P GPU clock controller, which is mostly identical but QCS8300 has few additional clocks and minor differences. Reviewed-by: Dmitry Baryshkov Signed-off-by: Imran Shaik --- drivers/clk/qcom/gpucc-sa8775p.c | 49 ++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 48 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gpucc-sa8775p.c b/drivers/clk/qcom/gpucc-sa87= 75p.c index f8a8ac343d70..78cad622cb5a 100644 --- a/drivers/clk/qcom/gpucc-sa8775p.c +++ b/drivers/clk/qcom/gpucc-sa8775p.c @@ -12,7 +12,7 @@ #include #include =20 -#include +#include =20 #include "clk-alpha-pll.h" #include "clk-branch.h" @@ -317,6 +317,24 @@ static struct clk_branch gpu_cc_crc_ahb_clk =3D { }, }; =20 +static struct clk_branch gpu_cc_cx_accu_shift_clk =3D { + .halt_reg =3D 0x95e8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x95e8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gpu_cc_cx_accu_shift_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gpu_cc_cx_ff_clk =3D { .halt_reg =3D 0x914c, .halt_check =3D BRANCH_HALT, @@ -420,6 +438,24 @@ static struct clk_branch gpu_cc_demet_clk =3D { }, }; =20 +static struct clk_branch gpu_cc_gx_accu_shift_clk =3D { + .halt_reg =3D 0x95e4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x95e4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gpu_cc_gx_accu_shift_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk =3D { .halt_reg =3D 0x7000, .halt_check =3D BRANCH_HALT_VOTED, @@ -499,6 +535,7 @@ static struct clk_regmap *gpu_cc_sa8775p_clocks[] =3D { [GPU_CC_AHB_CLK] =3D &gpu_cc_ahb_clk.clkr, [GPU_CC_CB_CLK] =3D &gpu_cc_cb_clk.clkr, [GPU_CC_CRC_AHB_CLK] =3D &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_ACCU_SHIFT_CLK] =3D NULL, [GPU_CC_CX_FF_CLK] =3D &gpu_cc_cx_ff_clk.clkr, [GPU_CC_CX_GMU_CLK] =3D &gpu_cc_cx_gmu_clk.clkr, [GPU_CC_CX_SNOC_DVM_CLK] =3D &gpu_cc_cx_snoc_dvm_clk.clkr, @@ -508,6 +545,7 @@ static struct clk_regmap *gpu_cc_sa8775p_clocks[] =3D { [GPU_CC_DEMET_DIV_CLK_SRC] =3D &gpu_cc_demet_div_clk_src.clkr, [GPU_CC_FF_CLK_SRC] =3D &gpu_cc_ff_clk_src.clkr, [GPU_CC_GMU_CLK_SRC] =3D &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GX_ACCU_SHIFT_CLK] =3D NULL, [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] =3D &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, [GPU_CC_HUB_AHB_DIV_CLK_SRC] =3D &gpu_cc_hub_ahb_div_clk_src.clkr, [GPU_CC_HUB_AON_CLK] =3D &gpu_cc_hub_aon_clk.clkr, @@ -583,6 +621,7 @@ static const struct qcom_cc_desc gpu_cc_sa8775p_desc = =3D { }; =20 static const struct of_device_id gpu_cc_sa8775p_match_table[] =3D { + { .compatible =3D "qcom,qcs8300-gpucc" }, { .compatible =3D "qcom,sa8775p-gpucc" }, { } }; @@ -596,6 +635,14 @@ static int gpu_cc_sa8775p_probe(struct platform_device= *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); =20 + if (of_device_is_compatible(pdev->dev.of_node, "qcom,qcs8300-gpucc")) { + gpu_cc_pll0_config.l =3D 0x31; + gpu_cc_pll0_config.alpha =3D 0xe555; + + gpu_cc_sa8775p_clocks[GPU_CC_CX_ACCU_SHIFT_CLK] =3D &gpu_cc_cx_accu_shif= t_clk.clkr; + gpu_cc_sa8775p_clocks[GPU_CC_GX_ACCU_SHIFT_CLK] =3D &gpu_cc_gx_accu_shif= t_clk.clkr; + } + clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); =20 --=20 2.25.1