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Wed, 06 Nov 2024 09:52:24 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4A69qNeB014056 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 6 Nov 2024 09:52:23 GMT Received: from hu-imrashai-hyd.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 6 Nov 2024 01:52:19 -0800 From: Imran Shaik Date: Wed, 6 Nov 2024 15:21:56 +0530 Subject: [PATCH v3 1/6] dt-bindings: clock: qcom: Add GPU clocks for QCS8300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241106-qcs8300-mm-patches-v3-1-f611a8f87f15@quicinc.com> References: <20241106-qcs8300-mm-patches-v3-0-f611a8f87f15@quicinc.com> In-Reply-To: <20241106-qcs8300-mm-patches-v3-0-f611a8f87f15@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Ajit Pandey , Taniya Das , Jagadeesh Kona , Satya Priya Kakitapalli , , , , , Imran Shaik X-Mailer: b4 0.14.1 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: nvLDwj0UjQqnB1L2DLBame2zWibVjBTb X-Proofpoint-GUID: nvLDwj0UjQqnB1L2DLBame2zWibVjBTb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=923 lowpriorityscore=0 priorityscore=1501 clxscore=1015 mlxscore=0 spamscore=0 suspectscore=0 bulkscore=0 phishscore=0 adultscore=0 impostorscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411060080 The QCS8300 GPU clock controller is mostly identical to SA8775P, but QCS8300 has few additional clocks and minor differences. Hence, reuse SA8775P gpucc bindings and add additional clocks required for QCS8300. Signed-off-by: Imran Shaik Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/clock/qcom,gpucc.yaml | 3 +++ include/dt-bindings/clock/qcom,qcs8300-gpucc.h | 17 +++++++++++++= ++++ 2 files changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Docu= mentation/devicetree/bindings/clock/qcom,gpucc.yaml index 0858fd635282..4cdff6161bf0 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml @@ -8,6 +8,7 @@ title: Qualcomm Graphics Clock & Reset Controller =20 maintainers: - Taniya Das + - Imran Shaik =20 description: | Qualcomm graphics clock control module provides the clocks, resets and p= ower @@ -23,10 +24,12 @@ description: | include/dt-bindings/clock/qcom,gpucc-sm8150.h include/dt-bindings/clock/qcom,gpucc-sm8250.h include/dt-bindings/clock/qcom,gpucc-sm8350.h + include/dt-bindings/clock/qcom,qcs8300-gpucc.h =20 properties: compatible: enum: + - qcom,qcs8300-gpucc - qcom,sdm845-gpucc - qcom,sa8775p-gpucc - qcom,sc7180-gpucc diff --git a/include/dt-bindings/clock/qcom,qcs8300-gpucc.h b/include/dt-bi= ndings/clock/qcom,qcs8300-gpucc.h new file mode 100644 index 000000000000..afa187467b4c --- /dev/null +++ b/include/dt-bindings/clock/qcom,qcs8300-gpucc.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPUCC_QCS8300_H +#define _DT_BINDINGS_CLK_QCOM_GPUCC_QCS8300_H + +#include "qcom,sa8775p-gpucc.h" + +/* QCS8300 introduces below new clocks compared to SA8775P */ + +/* GPU_CC clocks */ +#define GPU_CC_CX_ACCU_SHIFT_CLK 23 +#define GPU_CC_GX_ACCU_SHIFT_CLK 24 + +#endif --=20 2.25.1 From nobody Sun Nov 24 09:54:55 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 859CB1DD0E2; Wed, 6 Nov 2024 09:52:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730886754; cv=none; b=iK4lteFB6JVw+LRA3pnxKI+VBNZfraTQ1qMSdcxRRzybrjaNI1yxiETwPU0Wl8MMeLlQUUuwws3MbNRAC6mH4i8ONYMZ/UCOSyMULdADzfwyIV3SZ9vuLsVcAzpGAZolHQmaV5SZ6uzKS1N0apZKVwyd2CrCCXPTp06+pmTyI7M= ARC-Message-Signature: i=1; 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Reviewed-by: Dmitry Baryshkov Signed-off-by: Imran Shaik --- drivers/clk/qcom/gpucc-sa8775p.c | 49 ++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 48 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gpucc-sa8775p.c b/drivers/clk/qcom/gpucc-sa87= 75p.c index f8a8ac343d70..78cad622cb5a 100644 --- a/drivers/clk/qcom/gpucc-sa8775p.c +++ b/drivers/clk/qcom/gpucc-sa8775p.c @@ -12,7 +12,7 @@ #include #include =20 -#include +#include =20 #include "clk-alpha-pll.h" #include "clk-branch.h" @@ -317,6 +317,24 @@ static struct clk_branch gpu_cc_crc_ahb_clk =3D { }, }; =20 +static struct clk_branch gpu_cc_cx_accu_shift_clk =3D { + .halt_reg =3D 0x95e8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x95e8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gpu_cc_cx_accu_shift_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gpu_cc_cx_ff_clk =3D { .halt_reg =3D 0x914c, .halt_check =3D BRANCH_HALT, @@ -420,6 +438,24 @@ static struct clk_branch gpu_cc_demet_clk =3D { }, }; =20 +static struct clk_branch gpu_cc_gx_accu_shift_clk =3D { + .halt_reg =3D 0x95e4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x95e4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "gpu_cc_gx_accu_shift_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &gpu_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk =3D { .halt_reg =3D 0x7000, .halt_check =3D BRANCH_HALT_VOTED, @@ -499,6 +535,7 @@ static struct clk_regmap *gpu_cc_sa8775p_clocks[] =3D { [GPU_CC_AHB_CLK] =3D &gpu_cc_ahb_clk.clkr, [GPU_CC_CB_CLK] =3D &gpu_cc_cb_clk.clkr, [GPU_CC_CRC_AHB_CLK] =3D &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_ACCU_SHIFT_CLK] =3D NULL, [GPU_CC_CX_FF_CLK] =3D &gpu_cc_cx_ff_clk.clkr, [GPU_CC_CX_GMU_CLK] =3D &gpu_cc_cx_gmu_clk.clkr, [GPU_CC_CX_SNOC_DVM_CLK] =3D &gpu_cc_cx_snoc_dvm_clk.clkr, @@ -508,6 +545,7 @@ static struct clk_regmap *gpu_cc_sa8775p_clocks[] =3D { [GPU_CC_DEMET_DIV_CLK_SRC] =3D &gpu_cc_demet_div_clk_src.clkr, [GPU_CC_FF_CLK_SRC] =3D &gpu_cc_ff_clk_src.clkr, [GPU_CC_GMU_CLK_SRC] =3D &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GX_ACCU_SHIFT_CLK] =3D NULL, [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] =3D &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, [GPU_CC_HUB_AHB_DIV_CLK_SRC] =3D &gpu_cc_hub_ahb_div_clk_src.clkr, [GPU_CC_HUB_AON_CLK] =3D &gpu_cc_hub_aon_clk.clkr, @@ -583,6 +621,7 @@ static const struct qcom_cc_desc gpu_cc_sa8775p_desc = =3D { }; =20 static const struct of_device_id gpu_cc_sa8775p_match_table[] =3D { + { .compatible =3D "qcom,qcs8300-gpucc" }, { .compatible =3D "qcom,sa8775p-gpucc" }, { } }; @@ -596,6 +635,14 @@ static int gpu_cc_sa8775p_probe(struct platform_device= *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); =20 + if (of_device_is_compatible(pdev->dev.of_node, "qcom,qcs8300-gpucc")) { + gpu_cc_pll0_config.l =3D 0x31; + gpu_cc_pll0_config.alpha =3D 0xe555; + + gpu_cc_sa8775p_clocks[GPU_CC_CX_ACCU_SHIFT_CLK] =3D &gpu_cc_cx_accu_shif= t_clk.clkr; + gpu_cc_sa8775p_clocks[GPU_CC_GX_ACCU_SHIFT_CLK] =3D &gpu_cc_gx_accu_shif= t_clk.clkr; + } + clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); =20 --=20 2.25.1 From nobody Sun Nov 24 09:54:55 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 17B281DD552; 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Wed, 06 Nov 2024 09:52:32 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4A69qW02001651 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 6 Nov 2024 09:52:32 GMT Received: from hu-imrashai-hyd.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 6 Nov 2024 01:52:28 -0800 From: Imran Shaik Date: Wed, 6 Nov 2024 15:21:58 +0530 Subject: [PATCH v3 3/6] dt-bindings: clock: qcom: Add CAMCC clocks for QCS8300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241106-qcs8300-mm-patches-v3-3-f611a8f87f15@quicinc.com> References: <20241106-qcs8300-mm-patches-v3-0-f611a8f87f15@quicinc.com> In-Reply-To: <20241106-qcs8300-mm-patches-v3-0-f611a8f87f15@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Ajit Pandey , Taniya Das , Jagadeesh Kona , Satya Priya Kakitapalli , , , , , Imran Shaik X-Mailer: b4 0.14.1 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: GThQXOpjd1x2yeZ0WRyYNLR7a6x5Ag0x X-Proofpoint-ORIG-GUID: GThQXOpjd1x2yeZ0WRyYNLR7a6x5Ag0x X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 priorityscore=1501 impostorscore=0 mlxscore=0 bulkscore=0 spamscore=0 mlxlogscore=960 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411060080 The QCS8300 camera clock controller is mostly identical to SA8775P, but QCS8300 has one additional clock and minor differences. Hence, reuse the SA8775P camera bindings and add additional clock required for QCS8300. Signed-off-by: Imran Shaik Acked-by: Krzysztof Kozlowski Reviewed-by: Vladimir Zapolskiy --- .../devicetree/bindings/clock/qcom,sa8775p-camcc.yaml | 6 +++++- include/dt-bindings/clock/qcom,qcs8300-camcc.h | 16 ++++++++++++= ++++ 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yam= l b/Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml index 36a60d8f5ae3..81623f59d11d 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml @@ -8,16 +8,20 @@ title: Qualcomm Camera Clock & Reset Controller on SA8775P =20 maintainers: - Taniya Das + - Imran Shaik =20 description: | Qualcomm camera clock control module provides the clocks, resets and pow= er domains on SA8775p. =20 - See also: include/dt-bindings/clock/qcom,sa8775p-camcc.h + See also: + include/dt-bindings/clock/qcom,qcs8300-camcc.h + include/dt-bindings/clock/qcom,sa8775p-camcc.h =20 properties: compatible: enum: + - qcom,qcs8300-camcc - qcom,sa8775p-camcc =20 clocks: diff --git a/include/dt-bindings/clock/qcom,qcs8300-camcc.h b/include/dt-bi= ndings/clock/qcom,qcs8300-camcc.h new file mode 100644 index 000000000000..fc535c847859 --- /dev/null +++ b/include/dt-bindings/clock/qcom,qcs8300-camcc.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_QCS8300_CAM_CC_H +#define _DT_BINDINGS_CLK_QCOM_QCS8300_CAM_CC_H + +#include "qcom,sa8775p-camcc.h" + +/* QCS8300 introduces below new clocks compared to SA8775P */ + +/* CAM_CC clocks */ +#define CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK 86 + +#endif --=20 2.25.1 From nobody Sun Nov 24 09:54:55 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41E991DC07B; Wed, 6 Nov 2024 09:52:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730886762; cv=none; b=SAdMS/E4KoQ2POURgEP1HSojwvdyyMMzm7LWggv+ovse0RLQGk35Fqow6lHHF9aZHO64t/Yp6Jfu/ORKPBsjoRjkqioK6jc49DOURAo0prt7fjQjrRONeKrQydqcxqU6vJBJ0xaQjUg19alS9HTMvscmb0LqXrBeEd4A2v6AcSg= ARC-Message-Signature: i=1; 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Reviewed-by: Dmitry Baryshkov Signed-off-by: Imran Shaik --- drivers/clk/qcom/camcc-sa8775p.c | 101 +++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 96 insertions(+), 5 deletions(-) diff --git a/drivers/clk/qcom/camcc-sa8775p.c b/drivers/clk/qcom/camcc-sa87= 75p.c index c04801a5af35..bf0befb53a60 100644 --- a/drivers/clk/qcom/camcc-sa8775p.c +++ b/drivers/clk/qcom/camcc-sa8775p.c @@ -11,7 +11,7 @@ #include #include =20 -#include +#include =20 #include "clk-alpha-pll.h" #include "clk-branch.h" @@ -1682,6 +1682,24 @@ static struct clk_branch cam_cc_sm_obs_clk =3D { }, }; =20 +static struct clk_branch cam_cc_titan_top_accu_shift_clk =3D { + .halt_reg =3D 0x131f0, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x131f0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_titan_top_accu_shift_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + static struct gdsc cam_cc_titan_top_gdsc =3D { .gdscr =3D 0x131bc, .en_rest_wait_val =3D 0x2, @@ -1776,6 +1794,7 @@ static struct clk_regmap *cam_cc_sa8775p_clocks[] =3D= { [CAM_CC_SLEEP_CLK_SRC] =3D &cam_cc_sleep_clk_src.clkr, [CAM_CC_SLOW_AHB_CLK_SRC] =3D &cam_cc_slow_ahb_clk_src.clkr, [CAM_CC_SM_OBS_CLK] =3D &cam_cc_sm_obs_clk.clkr, + [CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK] =3D NULL, [CAM_CC_XO_CLK_SRC] =3D &cam_cc_xo_clk_src.clkr, [CAM_CC_QDSS_DEBUG_XO_CLK] =3D &cam_cc_qdss_debug_xo_clk.clkr, }; @@ -1812,6 +1831,7 @@ static struct qcom_cc_desc cam_cc_sa8775p_desc =3D { }; =20 static const struct of_device_id cam_cc_sa8775p_match_table[] =3D { + { .compatible =3D "qcom,qcs8300-camcc" }, { .compatible =3D "qcom,sa8775p-camcc" }, { } }; @@ -1842,10 +1862,81 @@ static int cam_cc_sa8775p_probe(struct platform_dev= ice *pdev) clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config); =20 - /* Keep some clocks always enabled */ - qcom_branch_set_clk_en(regmap, 0x13194); /* CAM_CC_CAMNOC_XO_CLK */ - qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_GDSC_CLK */ - qcom_branch_set_clk_en(regmap, 0x13208); /* CAM_CC_SLEEP_CLK */ + if (of_device_is_compatible(pdev->dev.of_node, "qcom,qcs8300-camcc")) { + cam_cc_camnoc_axi_clk_src.cmd_rcgr =3D 0x13154; + cam_cc_camnoc_axi_clk.halt_reg =3D 0x1316c; + cam_cc_camnoc_axi_clk.clkr.enable_reg =3D 0x1316c; + cam_cc_camnoc_dcd_xo_clk.halt_reg =3D 0x13174; + cam_cc_camnoc_dcd_xo_clk.clkr.enable_reg =3D 0x13174; + + cam_cc_csi0phytimer_clk_src.cmd_rcgr =3D 0x15054; + cam_cc_csi1phytimer_clk_src.cmd_rcgr =3D 0x15078; + cam_cc_csi2phytimer_clk_src.cmd_rcgr =3D 0x15098; + cam_cc_csid_clk_src.cmd_rcgr =3D 0x13134; + + cam_cc_mclk0_clk_src.cmd_rcgr =3D 0x15000; + cam_cc_mclk1_clk_src.cmd_rcgr =3D 0x1501c; + cam_cc_mclk2_clk_src.cmd_rcgr =3D 0x15038; + + cam_cc_fast_ahb_clk_src.cmd_rcgr =3D 0x13104; + cam_cc_slow_ahb_clk_src.cmd_rcgr =3D 0x1311c; + cam_cc_xo_clk_src.cmd_rcgr =3D 0x131b8; + cam_cc_sleep_clk_src.cmd_rcgr =3D 0x131d4; + + cam_cc_core_ahb_clk.halt_reg =3D 0x131b4; + cam_cc_core_ahb_clk.clkr.enable_reg =3D 0x131b4; + + cam_cc_cpas_ahb_clk.halt_reg =3D 0x130f4; + cam_cc_cpas_ahb_clk.clkr.enable_reg =3D 0x130f4; + cam_cc_cpas_fast_ahb_clk.halt_reg =3D 0x130fc; + cam_cc_cpas_fast_ahb_clk.clkr.enable_reg =3D 0x130fc; + + cam_cc_csi0phytimer_clk.halt_reg =3D 0x1506c; + cam_cc_csi0phytimer_clk.clkr.enable_reg =3D 0x1506c; + cam_cc_csi1phytimer_clk.halt_reg =3D 0x15090; + cam_cc_csi1phytimer_clk.clkr.enable_reg =3D 0x15090; + cam_cc_csi2phytimer_clk.halt_reg =3D 0x150b0; + cam_cc_csi2phytimer_clk.clkr.enable_reg =3D 0x150b0; + cam_cc_csid_clk.halt_reg =3D 0x1314c; + cam_cc_csid_clk.clkr.enable_reg =3D 0x1314c; + cam_cc_csid_csiphy_rx_clk.halt_reg =3D 0x15074; + cam_cc_csid_csiphy_rx_clk.clkr.enable_reg =3D 0x15074; + cam_cc_csiphy0_clk.halt_reg =3D 0x15070; + cam_cc_csiphy0_clk.clkr.enable_reg =3D 0x15070; + cam_cc_csiphy1_clk.halt_reg =3D 0x15094; + cam_cc_csiphy1_clk.clkr.enable_reg =3D 0x15094; + cam_cc_csiphy2_clk.halt_reg =3D 0x150b4; + cam_cc_csiphy2_clk.clkr.enable_reg =3D 0x150b4; + + cam_cc_mclk0_clk.halt_reg =3D 0x15018; + cam_cc_mclk0_clk.clkr.enable_reg =3D 0x15018; + cam_cc_mclk1_clk.halt_reg =3D 0x15034; + cam_cc_mclk1_clk.clkr.enable_reg =3D 0x15034; + cam_cc_mclk2_clk.halt_reg =3D 0x15050; + cam_cc_mclk2_clk.clkr.enable_reg =3D 0x15050; + + cam_cc_titan_top_gdsc.gdscr =3D 0x131a0; + + cam_cc_sa8775p_clocks[CAM_CC_CCI_3_CLK] =3D NULL; + cam_cc_sa8775p_clocks[CAM_CC_CCI_3_CLK_SRC] =3D NULL; + cam_cc_sa8775p_clocks[CAM_CC_CSI3PHYTIMER_CLK] =3D NULL; + cam_cc_sa8775p_clocks[CAM_CC_CSI3PHYTIMER_CLK_SRC] =3D NULL; + cam_cc_sa8775p_clocks[CAM_CC_CSIPHY3_CLK] =3D NULL; + cam_cc_sa8775p_clocks[CAM_CC_MCLK3_CLK] =3D NULL; + cam_cc_sa8775p_clocks[CAM_CC_MCLK3_CLK_SRC] =3D NULL; + cam_cc_sa8775p_clocks[CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK] =3D + &cam_cc_titan_top_accu_shift_clk.clkr; + + /* Keep some clocks always enabled */ + qcom_branch_set_clk_en(regmap, 0x13178); /* CAM_CC_CAMNOC_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x131d0); /* CAM_CC_GDSC_CLK */ + qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_SLEEP_CLK */ + } else { + /* Keep some clocks always enabled */ + qcom_branch_set_clk_en(regmap, 0x13194); /* CAM_CC_CAMNOC_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_GDSC_CLK */ + qcom_branch_set_clk_en(regmap, 0x13208); /* CAM_CC_SLEEP_CLK */ + } =20 ret =3D qcom_cc_really_probe(&pdev->dev, &cam_cc_sa8775p_desc, regmap); =20 --=20 2.25.1 From nobody Sun Nov 24 09:54:55 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49E751DDC1F; Wed, 6 Nov 2024 09:52:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730886766; cv=none; b=VOSkffZtgXdcLYCDebORVBCd5ATYrYqH4LC0Yx+Isd7quUhcLB6lrIsO9R0g1sL/TRlAFKx2GZcjZDjrXtv8MymLLmVOa3XFWkQiNoiPW5WtwtJGX9QQgmlsF+/te1PgLN5RtxDjI7RKaOq8I/EfzBLd81Odk7d3M+ThguTjTd0= ARC-Message-Signature: i=1; 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Hence, reuse the SA8775P videocc bindings for QCS8300 platform. Acked-by: Krzysztof Kozlowski Signed-off-by: Imran Shaik --- Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.y= aml b/Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml index 928131bff4c1..07e5d811d816 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sa8775p-videocc.yaml @@ -18,6 +18,7 @@ description: | properties: compatible: enum: + - qcom,qcs8300-videocc - qcom,sa8775p-videocc =20 clocks: --=20 2.25.1 From nobody Sun Nov 24 09:54:55 2024 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 359921DACAF; Wed, 6 Nov 2024 09:52:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Reviewed-by: Dmitry Baryshkov Signed-off-by: Imran Shaik --- drivers/clk/qcom/videocc-sa8775p.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/qcom/videocc-sa8775p.c b/drivers/clk/qcom/videocc-= sa8775p.c index bf5de411fd5d..db492984fd7d 100644 --- a/drivers/clk/qcom/videocc-sa8775p.c +++ b/drivers/clk/qcom/videocc-sa8775p.c @@ -523,6 +523,7 @@ static struct qcom_cc_desc video_cc_sa8775p_desc =3D { }; =20 static const struct of_device_id video_cc_sa8775p_match_table[] =3D { + { .compatible =3D "qcom,qcs8300-videocc" }, { .compatible =3D "qcom,sa8775p-videocc" }, { } }; @@ -550,6 +551,13 @@ static int video_cc_sa8775p_probe(struct platform_devi= ce *pdev) clk_lucid_evo_pll_configure(&video_pll0, regmap, &video_pll0_config); clk_lucid_evo_pll_configure(&video_pll1, regmap, &video_pll1_config); =20 + /* + * Set mvs0c clock divider to div-3 to make the mvs0 and + * mvs0c clocks to run at the same frequency on QCS8300 + */ + if (of_device_is_compatible(pdev->dev.of_node, "qcom,qcs8300-videocc")) + regmap_write(regmap, video_cc_mvs0c_div2_div_clk_src.reg, 2); + /* Keep some clocks always enabled */ qcom_branch_set_clk_en(regmap, 0x80ec); /* VIDEO_CC_AHB_CLK */ qcom_branch_set_clk_en(regmap, 0x8144); /* VIDEO_CC_SLEEP_CLK */ --=20 2.25.1