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Peter Anvin" CC: Subject: [PATCH v2 01/35] x86/bugs: Add X86_BUG_SPECTRE_V2_USER Date: Tue, 5 Nov 2024 15:54:21 -0600 Message-ID: <20241105215455.359471-2-david.kaplan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105215455.359471-1-david.kaplan@amd.com> References: <20241105215455.359471-1-david.kaplan@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B374:EE_|DM4PR12MB7720:EE_ X-MS-Office365-Filtering-Correlation-Id: 83145290-5e59-4674-dd5e-08dcfde48c3b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?v6IKaeVKyyvJojMAO0via17uEgvr08QvqxJmQTPWsP/O71BIaKoikc5Y7Jd6?= =?us-ascii?Q?FjUdqUZNHljYQ5oC+rLYu9025Ded+5miPMbRJcf1eFYQa7quqExyRPLiFwVp?= =?us-ascii?Q?Bo0yqEqzZ1CTdy/rmFTRT1G519PbvrQIlrqWIHBnWkXWxFjNWRBcNSdtAfiY?= =?us-ascii?Q?d0D4Va1d56o14ROLmdxFeE3TZ4whv0NSUPetRL77OOlwSbA23zjUKYS2GnnU?= =?us-ascii?Q?iXV6rZ9YnhXU+z4gVMqTWTjtwowbYRsNuhiQLuHcR4K0VptTlpWMQf4O7xYD?= =?us-ascii?Q?VT6ACK2tUyJ0eyPSsMI4XZnOE9EDtvszR+BlnVxxDG5h2fOkcB6rlefk2Bas?= =?us-ascii?Q?zNKISBR89I/rlOrMq42GfsqqMt8KpG8RMLn687PmHs5uOV3FlSRPWE2yZae9?= =?us-ascii?Q?W75BUwJLkzfhO+jN1duuRTRGmIBgQnTQbn3UWrk1D8hMyXN7p/x8QKnr9mLh?= =?us-ascii?Q?4bvj4dxOf5Gj/6WEvWjX0tq4xecFVBBsdfqdVJHVhWBTm+A/AVb28AVo29Nd?= =?us-ascii?Q?jEAKpP0b0EHqBuwYfin2wbyWi8GsU4dhQQNB+22cBN/tG3/mGZBSpMZvqBWC?= =?us-ascii?Q?vcrqv2dF1S7xEiG3zSSijTNcRNsvOk+j2zg7XdfhGpRBL+AOY8Z5FPYdKvuz?= =?us-ascii?Q?27OtoxKsfP3VpY3ppt6/uP2R7oEs1RZtbiUs8SkFGFfsiIM94YWFM+bVj6u+?= =?us-ascii?Q?/PPXMM06R4Bc8lI9RBhvPeBFq64AKJwi+quGtp1Cb8fy083eV4k6i4WP0DL6?= =?us-ascii?Q?z9+/3ic4Qmnp7bw0WGOjGlPL9p8AsQdI7c3BHIhVe9YYeMnBDtOnAVtC7w8I?= =?us-ascii?Q?OBDVDCd89c+OvGpUBg03Aq17+FVfnFBzZ1tQG62ShIQVsNVrsxcHlcfedAEt?= =?us-ascii?Q?ZEWsKCZtrEPcOqmlRsqlMdVDEhnMLL5/xxoRuCF10Z9C2jaN5FQMWeorFIXT?= =?us-ascii?Q?OeVEB6dnc7tkRMotuOjt+xuQ5SIWM/RTEPQVy46rcW5O3kpLMj5G6i2FHpIE?= =?us-ascii?Q?YgM8Dr6f+m87RN2fF51AHT9ET+jrsTmFZV/YTBFHZFcZUBxQv7YsqHRqUM0e?= =?us-ascii?Q?tWlHfJaYdz7OiSKoz5pH2vpdyo4+13G1kVj/A0AsrqB96n/Lkv5ErHPVKNIK?= =?us-ascii?Q?rQwZNHbe1gXDrJMgVmYomLboZBt3cxfGH40xg174ojFLVwUy9cJvKpkPTL6u?= =?us-ascii?Q?QCgiQjRP8+ZClbjvcWsCqSSY0TO4hZVbVxPh8RQc4Ug1Salgk+NUDkAFbNdz?= =?us-ascii?Q?lM+tEN7Xyx5NZX8pSm3fJ+Gi7NJPYOEMCN2P7a9uG07qZs8RER3O10PwC4C7?= =?us-ascii?Q?mxZqEbtoOw0xds2GVDBcsXS6IobfblG3uYMEn/w7bbsJT+Tk4PRfUnb7XHWX?= =?us-ascii?Q?jZBoRq263k50OsW/UPcSqo72hjjJd2YAw8ysWRr9jzLn1OGAFA=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 21:55:22.6247 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 83145290-5e59-4674-dd5e-08dcfde48c3b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B374.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7720 Content-Type: text/plain; charset="utf-8" All CPU vulnerabilities with command line options map to a single X86_BUG bit except for Spectre V2 where both the spectre_v2 and spectre_v2_user command line options are related to the same bug. The spectre_v2 command line options mostly relate to user->kernel and guest->host mitigations, while the spectre_v2_user command line options relate to user->user or guest->guest protections. Define a new X86_BUG bit for spectre_v2_user so each *_select_mitigation() function in bugs.c is related to a unique X86_BUG bit. Signed-off-by: David Kaplan --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/common.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 924f530129d7..0c4c974a616b 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -528,4 +528,5 @@ #define X86_BUG_RFDS X86_BUG(1*32 + 2) /* "rfds" CPU is vulnerable to Re= gister File Data Sampling */ #define X86_BUG_BHI X86_BUG(1*32 + 3) /* "bhi" CPU is affected by Branch= History Injection */ #define X86_BUG_IBPB_NO_RET X86_BUG(1*32 + 4) /* "ibpb_no_ret" IBPB om= its return target predictions */ +#define X86_BUG_SPECTRE_V2_USER X86_BUG(1*32 + 5) /* "spectre_v2_user" CP= U is affected by Spectre variant 2 attack between user processes */ #endif /* _ASM_X86_CPUFEATURES_H */ diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 8f41ab219cf1..a2bc1c1b31a9 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1332,8 +1332,10 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x= 86 *c) =20 setup_force_cpu_bug(X86_BUG_SPECTRE_V1); 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No functional change. Signed-off-by: David Kaplan --- arch/x86/kernel/cpu/bugs.c | 60 ++++++++++++++++++++------------------ 1 file changed, 31 insertions(+), 29 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 83b34a522dd7..3fd7a2ce11b5 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -243,6 +243,37 @@ static const char * const mds_strings[] =3D { [MDS_MITIGATION_VMWERV] =3D "Vulnerable: Clear CPU buffers attempted, no = microcode", }; =20 +enum taa_mitigations { + TAA_MITIGATION_OFF, + TAA_MITIGATION_UCODE_NEEDED, + TAA_MITIGATION_VERW, + TAA_MITIGATION_TSX_DISABLED, +}; + +/* Default mitigation for TAA-affected CPUs */ +static enum taa_mitigations taa_mitigation __ro_after_init =3D + IS_ENABLED(CONFIG_MITIGATION_TAA) ? TAA_MITIGATION_VERW : TAA_MITIGATION_= OFF; + +enum mmio_mitigations { + MMIO_MITIGATION_OFF, + MMIO_MITIGATION_UCODE_NEEDED, + MMIO_MITIGATION_VERW, +}; + +/* Default mitigation for Processor MMIO Stale Data vulnerabilities */ +static enum mmio_mitigations mmio_mitigation __ro_after_init =3D + IS_ENABLED(CONFIG_MITIGATION_MMIO_STALE_DATA) ? MMIO_MITIGATION_VERW : MM= IO_MITIGATION_OFF; + +enum rfds_mitigations { + RFDS_MITIGATION_OFF, + RFDS_MITIGATION_VERW, + RFDS_MITIGATION_UCODE_NEEDED, +}; + +/* Default mitigation for Register File Data Sampling */ +static enum rfds_mitigations rfds_mitigation __ro_after_init =3D + IS_ENABLED(CONFIG_MITIGATION_RFDS) ? RFDS_MITIGATION_VERW : RFDS_MITIGATI= ON_OFF; + static void __init mds_select_mitigation(void) { if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) { @@ -286,16 +317,6 @@ early_param("mds", mds_cmdline); #undef pr_fmt #define pr_fmt(fmt) "TAA: " fmt =20 -enum taa_mitigations { - TAA_MITIGATION_OFF, - TAA_MITIGATION_UCODE_NEEDED, - TAA_MITIGATION_VERW, - TAA_MITIGATION_TSX_DISABLED, -}; - -/* Default mitigation for TAA-affected CPUs */ -static enum taa_mitigations taa_mitigation __ro_after_init =3D - IS_ENABLED(CONFIG_MITIGATION_TAA) ? TAA_MITIGATION_VERW : TAA_MITIGATION_= OFF; static bool taa_nosmt __ro_after_init; =20 static const char * const taa_strings[] =3D { @@ -386,15 +407,6 @@ early_param("tsx_async_abort", tsx_async_abort_parse_c= mdline); #undef pr_fmt #define pr_fmt(fmt) "MMIO Stale Data: " fmt =20 -enum mmio_mitigations { - MMIO_MITIGATION_OFF, - MMIO_MITIGATION_UCODE_NEEDED, - MMIO_MITIGATION_VERW, -}; - -/* Default mitigation for Processor MMIO Stale Data vulnerabilities */ -static enum mmio_mitigations mmio_mitigation __ro_after_init =3D - IS_ENABLED(CONFIG_MITIGATION_MMIO_STALE_DATA) ? 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These AUTO mitigations will be turned into the appropriate default mitigations in the _select_mitigation() functions. In a later patch, these will be used with the new attack vector controls to help select appropriate mitigations. Signed-off-by: David Kaplan --- arch/x86/include/asm/processor.h | 1 + arch/x86/kernel/cpu/bugs.c | 20 ++++++++++++++++---- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/proces= sor.h index c0975815980c..ea4b87b44455 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -754,6 +754,7 @@ extern enum l1tf_mitigations l1tf_mitigation; =20 enum mds_mitigations { MDS_MITIGATION_OFF, + MDS_MITIGATION_AUTO, MDS_MITIGATION_FULL, MDS_MITIGATION_VMWERV, }; diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 3fd7a2ce11b5..34d55f368bff 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -234,7 +234,7 @@ static void x86_amd_ssb_disable(void) =20 /* Default mitigation for MDS-affected CPUs */ static enum mds_mitigations mds_mitigation __ro_after_init =3D - IS_ENABLED(CONFIG_MITIGATION_MDS) ? MDS_MITIGATION_FULL : MDS_MITIGATION_= OFF; + IS_ENABLED(CONFIG_MITIGATION_MDS) ? MDS_MITIGATION_AUTO : MDS_MITIGATION_= OFF; static bool mds_nosmt __ro_after_init =3D false; =20 static const char * const mds_strings[] =3D { @@ -245,6 +245,7 @@ static const char * const mds_strings[] =3D { =20 enum taa_mitigations { TAA_MITIGATION_OFF, + TAA_MITIGATION_AUTO, TAA_MITIGATION_UCODE_NEEDED, TAA_MITIGATION_VERW, TAA_MITIGATION_TSX_DISABLED, @@ -252,27 +253,29 @@ enum taa_mitigations { =20 /* Default mitigation for TAA-affected CPUs */ static enum taa_mitigations taa_mitigation __ro_after_init =3D - IS_ENABLED(CONFIG_MITIGATION_TAA) ? TAA_MITIGATION_VERW : TAA_MITIGATION_= OFF; + IS_ENABLED(CONFIG_MITIGATION_TAA) ? TAA_MITIGATION_AUTO : TAA_MITIGATION_= OFF; =20 enum mmio_mitigations { MMIO_MITIGATION_OFF, + MMIO_MITIGATION_AUTO, MMIO_MITIGATION_UCODE_NEEDED, MMIO_MITIGATION_VERW, }; =20 /* Default mitigation for Processor MMIO Stale Data vulnerabilities */ static enum mmio_mitigations mmio_mitigation __ro_after_init =3D - IS_ENABLED(CONFIG_MITIGATION_MMIO_STALE_DATA) ? MMIO_MITIGATION_VERW : MM= IO_MITIGATION_OFF; + IS_ENABLED(CONFIG_MITIGATION_MMIO_STALE_DATA) ? MMIO_MITIGATION_AUTO : MM= IO_MITIGATION_OFF; =20 enum rfds_mitigations { RFDS_MITIGATION_OFF, + RFDS_MITIGATION_AUTO, RFDS_MITIGATION_VERW, RFDS_MITIGATION_UCODE_NEEDED, }; =20 /* Default mitigation for Register File Data Sampling */ static enum rfds_mitigations rfds_mitigation __ro_after_init =3D - IS_ENABLED(CONFIG_MITIGATION_RFDS) ? RFDS_MITIGATION_VERW : RFDS_MITIGATI= ON_OFF; + IS_ENABLED(CONFIG_MITIGATION_RFDS) ? RFDS_MITIGATION_AUTO : RFDS_MITIGATI= ON_OFF; =20 static void __init mds_select_mitigation(void) { @@ -281,6 +284,9 @@ static void __init mds_select_mitigation(void) return; } =20 + if (mds_mitigation =3D=3D MDS_MITIGATION_AUTO) + mds_mitigation =3D MDS_MITIGATION_FULL; + if (mds_mitigation =3D=3D MDS_MITIGATION_FULL) { if (!boot_cpu_has(X86_FEATURE_MD_CLEAR)) mds_mitigation =3D MDS_MITIGATION_VMWERV; @@ -510,6 +516,9 @@ static void __init rfds_select_mitigation(void) if (rfds_mitigation =3D=3D RFDS_MITIGATION_OFF) return; =20 + if (rfds_mitigation =3D=3D RFDS_MITIGATION_AUTO) + rfds_mitigation =3D RFDS_MITIGATION_VERW; + if (x86_arch_cap_msr & ARCH_CAP_RFDS_CLEAR) setup_force_cpu_cap(X86_FEATURE_CLEAR_CPU_BUF); else @@ -1995,6 +2004,7 @@ void cpu_bugs_smt_update(void) update_mds_branch_idle(); break; case MDS_MITIGATION_OFF: + case MDS_MITIGATION_AUTO: break; } =20 @@ -2006,6 +2016,7 @@ void cpu_bugs_smt_update(void) break; case TAA_MITIGATION_TSX_DISABLED: case TAA_MITIGATION_OFF: + case TAA_MITIGATION_AUTO: break; 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Peter Anvin" CC: Subject: [PATCH v2 04/35] x86/bugs: Restructure mds mitigation Date: Tue, 5 Nov 2024 15:54:24 -0600 Message-ID: <20241105215455.359471-5-david.kaplan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105215455.359471-1-david.kaplan@amd.com> References: <20241105215455.359471-1-david.kaplan@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B374:EE_|SA1PR12MB8163:EE_ X-MS-Office365-Filtering-Correlation-Id: 5f3f5cce-8f43-41b9-6a5a-08dcfde48dad X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|7416014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?iTmN+iaWjiVg1iiVWPw/AeAntzztLIA5wchs2Jh32PsEpS8D3ju2XIJABkVg?= =?us-ascii?Q?SrUDPeeWotJDrZzL50qxBMfo5V72b5SU7pFZIqxmu7R3x8OUSNZ6GE0ZkITv?= =?us-ascii?Q?76KqkyzESNePrWHFOj2yZMlYFUFSubFYDJiD5wFCUzdvoBJ5BnpnjCM8e3oI?= =?us-ascii?Q?SLZDmdXcl05JO2rvBREdN3KNpq5NX/KQd4uZj1f2RXo/Wpu2Od6Q1QRDjEym?= =?us-ascii?Q?yl01dARlddQT3H84zMYG134QSbLUEQc7CblxMDXPt8X7I7+AgmAfkRGQwKyF?= =?us-ascii?Q?PfRdlKY9qzW7WoVqB9+bqnf6Btq/uFuLubbqbD/TpZCrc+NDevGi6MBOMWMa?= =?us-ascii?Q?OxKTB9/L014MzLwJEkPQNOlkU3w+7dnqfErdpM1B7ADEMpWvAoJOzePQiodU?= =?us-ascii?Q?+uTpVEM2JAbrHUCVCCX75pbgUp9YzK8ns1SJQaSB6JIS7vpYDGsFgl3h5FoY?= =?us-ascii?Q?jAEyi6oTtIP232/E7QEpkWdFTYbaS8KJ/VTvv1Q9okA0knwklv95OIL1EuRa?= =?us-ascii?Q?j6kUqYX9+SUbHd37+fqj2qZCYisRkAIe249cIEb/8RWu0KzJJuL8GdGl/iEM?= =?us-ascii?Q?1a9GLe7MLOUJ8jq2IhcmDMQSUEYHx/Cbvep5DkIlkfx9wCiroABAswmp+EVR?= =?us-ascii?Q?JI1+lujdPpGhUSEWUrCR+a+Po5yjNpx6g3vySgonUV98MgZYgOKXKiFqaOUB?= =?us-ascii?Q?1cQ5eZJzzS3n8bn4QjVRLCe0bF5wbRI91g+ugYxAQIArLiVoDjIwCt76hyuH?= =?us-ascii?Q?RnmeJWnRKAM44p/Ksrv2PvHxE3issL/FV0CdDzmuyWj/8CpX9SClEEZ/ggNb?= =?us-ascii?Q?JL0DkEXY2qaJCaLmUyhuvThaVg97P+WA/qYt/4M6GVnTlRVOCx+3xc75OEUO?= =?us-ascii?Q?ouX40o2BHf4HqCXsJo+XvyMdzoCNwyE/QLX4hYSUMegXmMiw8oGO7t+IJyX4?= =?us-ascii?Q?l3CEzmrgIuQ3xf+iAT1mddD7uZXeqV9h9RJUvphOxCwA6nuPb4Qs/2pSFbsM?= =?us-ascii?Q?jepfdIv9d9Rf4YKf9w3TcKuLyMQSS8XffH1Vd2G0Uf67xlf8gcyVghLhlxBM?= =?us-ascii?Q?nLgvy/vWwf2JHsTzG3TTvFxe2mtAftyQH6H1V6vBgQt5DGe+xUSojwWVqhgI?= =?us-ascii?Q?9/cHpXmib4XzsrAoSVdeSD8yA/ogE5M4dJQ+44oBj8kKkj3ZQMQ1CJ7HUItq?= =?us-ascii?Q?VxzjPnZsoMp+8eeUVAPT3MlNLia2X+arqz3lviZAClqD7zVhfqsFUBAUtsm9?= =?us-ascii?Q?PKrSxyqlaVinljwRn6RvgRxgW5aJKu5B9CFo5Va/6fpuaVqYRlrK6YiqUG9Z?= =?us-ascii?Q?bq+c9E8HihGDPe7DbkFdPzSW0VFx/yp1GFNaT8w8GTkKh+Kjt7IY79wdD63w?= =?us-ascii?Q?UEpUtZdYHPNleAdAyBzvCmjbx8gUxHspHHuWBjvVT4dwjF1MiA=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(7416014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 21:55:25.0465 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5f3f5cce-8f43-41b9-6a5a-08dcfde48dad X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B374.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8163 Content-Type: text/plain; charset="utf-8" Restructure mds mitigation selection to use select/update/apply functions to create consistent vulnerability handling. Signed-off-by: David Kaplan --- arch/x86/kernel/cpu/bugs.c | 69 +++++++++++++++++++++++++++++++++----- 1 file changed, 61 insertions(+), 8 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 34d55f368bff..4f35dcd9dee8 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -34,6 +34,25 @@ =20 #include "cpu.h" =20 +/* + * Speculation Vulnerability Handling + * + * Each vulnerability is handled with the following functions: + * _select_mitigation() -- Selects a mitigation to use. This shou= ld + * take into account all relevant command line + * options. + * _update_mitigation() -- This is called after all vulnerabilitie= s have + * selected a mitigation, in case the selection + * may want to change based on other choices + * made. This function is optional. + * _apply_mitigation() -- Enable the selected mitigation. + * + * The compile-time mitigation in all cases should be AUTO. An explicit + * command-line option can override AUTO. If no such option is + * provided, _select_mitigation() will override AUTO to the best + * mitigation option. + */ + static void __init spectre_v1_select_mitigation(void); static void __init spectre_v2_select_mitigation(void); static void __init retbleed_select_mitigation(void); @@ -41,6 +60,8 @@ static void __init spectre_v2_user_select_mitigation(void= ); static void __init ssb_select_mitigation(void); static void __init l1tf_select_mitigation(void); static void __init mds_select_mitigation(void); +static void __init mds_update_mitigation(void); +static void __init mds_apply_mitigation(void); static void __init md_clear_update_mitigation(void); static void __init md_clear_select_mitigation(void); static void __init taa_select_mitigation(void); @@ -165,6 +186,7 @@ void __init cpu_select_mitigations(void) spectre_v2_user_select_mitigation(); ssb_select_mitigation(); l1tf_select_mitigation(); + mds_select_mitigation(); md_clear_select_mitigation(); srbds_select_mitigation(); l1d_flush_select_mitigation(); @@ -175,6 +197,14 @@ void __init cpu_select_mitigations(void) */ srso_select_mitigation(); gds_select_mitigation(); + + /* + * After mitigations are selected, some may need to update their + * choices. + */ + mds_update_mitigation(); + + mds_apply_mitigation(); } =20 /* @@ -229,9 +259,6 @@ static void x86_amd_ssb_disable(void) wrmsrl(MSR_AMD64_LS_CFG, msrval); } =20 -#undef pr_fmt -#define pr_fmt(fmt) "MDS: " fmt - /* Default mitigation for MDS-affected CPUs */ static enum mds_mitigations mds_mitigation __ro_after_init =3D IS_ENABLED(CONFIG_MITIGATION_MDS) ? MDS_MITIGATION_AUTO : MDS_MITIGATION_= OFF; @@ -277,12 +304,19 @@ enum rfds_mitigations { static enum rfds_mitigations rfds_mitigation __ro_after_init =3D IS_ENABLED(CONFIG_MITIGATION_RFDS) ? RFDS_MITIGATION_AUTO : RFDS_MITIGATI= ON_OFF; =20 +/* Return TRUE if any VERW-based mitigation is enabled. */ +static bool __init mitigate_any_verw(void) +{ + return (mds_mitigation !=3D MDS_MITIGATION_OFF || + taa_mitigation !=3D TAA_MITIGATION_OFF || + mmio_mitigation !=3D MMIO_MITIGATION_OFF || + rfds_mitigation !=3D RFDS_MITIGATION_OFF); +} + static void __init mds_select_mitigation(void) { - if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) { + if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) mds_mitigation =3D MDS_MITIGATION_OFF; - return; - } =20 if (mds_mitigation =3D=3D MDS_MITIGATION_AUTO) mds_mitigation =3D MDS_MITIGATION_FULL; @@ -290,9 +324,29 @@ static void __init mds_select_mitigation(void) if (mds_mitigation =3D=3D MDS_MITIGATION_FULL) { if (!boot_cpu_has(X86_FEATURE_MD_CLEAR)) mds_mitigation =3D MDS_MITIGATION_VMWERV; + } +} =20 - setup_force_cpu_cap(X86_FEATURE_CLEAR_CPU_BUF); +static void __init mds_update_mitigation(void) +{ + if (!boot_cpu_has_bug(X86_BUG_MDS)) + return; + + /* If TAA, MMIO, or RFDS are being mitigated, MDS gets mitigated too. */ + if (mitigate_any_verw()) { + if (boot_cpu_has(X86_FEATURE_MD_CLEAR)) + mds_mitigation =3D MDS_MITIGATION_FULL; + else + mds_mitigation =3D MDS_MITIGATION_VMWERV; + } + + pr_info("MDS: %s\n", mds_strings[mds_mitigation]); +} =20 +static void __init mds_apply_mitigation(void) +{ + if (mds_mitigation =3D=3D MDS_MITIGATION_FULL) { + setup_force_cpu_cap(X86_FEATURE_CLEAR_CPU_BUF); if (!boot_cpu_has(X86_BUG_MSBDS_ONLY) && (mds_nosmt || cpu_mitigations_auto_nosmt())) cpu_smt_disable(false); @@ -595,7 +649,6 @@ static void __init md_clear_update_mitigation(void) =20 static void __init md_clear_select_mitigation(void) { - mds_select_mitigation(); taa_select_mitigation(); mmio_select_mitigation(); rfds_select_mitigation(); --=20 2.34.1 From nobody Sun Nov 24 11:56:51 2024 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2070.outbound.protection.outlook.com [40.107.220.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 360FA216A02 for ; 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Tue, 5 Nov 2024 15:55:23 -0600 From: David Kaplan To: Thomas Gleixner , Borislav Petkov , Peter Zijlstra , Josh Poimboeuf , Pawan Gupta , Ingo Molnar , Dave Hansen , , "H . Peter Anvin" CC: Subject: [PATCH v2 05/35] x86/bugs: Restructure taa mitigation Date: Tue, 5 Nov 2024 15:54:25 -0600 Message-ID: <20241105215455.359471-6-david.kaplan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105215455.359471-1-david.kaplan@amd.com> References: <20241105215455.359471-1-david.kaplan@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B374:EE_|BL3PR12MB6522:EE_ X-MS-Office365-Filtering-Correlation-Id: 88da9bd6-d179-44b8-78ed-08dcfde48e1d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|36860700013|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?D44NXf/dnkpI9HMPBGXwKhyN918kMQe8joEbVJbj5yhWw48qx7RayWoulmx3?= =?us-ascii?Q?sDwWaZ7HJZF1CZCWsFbY6UETyAn5rDSjFoRRHyKMaiC9bYznznAZROdKWCsg?= =?us-ascii?Q?haXa35AZIuKY7YLTm/JoP1j1dbVR5/LUgDwpd4hhLIbF1i/1g7EAhHUeNONG?= =?us-ascii?Q?YaQg+j6YJVLmkLEnuZskJv0+glVce2pf4qrGhwLugYXD+UsJyuSo2tHDpLZV?= =?us-ascii?Q?VOzBhGOWo89mSH97rexcdsL/bdmV6z9tPZzz/o1ob3qWb921Qe5VrWgUcQRs?= =?us-ascii?Q?yIyY8S6rIeotlgxi2UHT9znmyb2b/mWLAyzpYLamAhzeHp+jV567xD0kkPA9?= =?us-ascii?Q?zUpKsLlp2qs6lq0g7EJOJQbE3jydGVwjqf4/Zqz9HmO+HHyzRxutP2W8f/xd?= =?us-ascii?Q?tzgnLxmBIDf3YHU9SQZbAq175LOluEU5dokFsZS5pKY+BVdmuLQKFVdkEm4o?= =?us-ascii?Q?XWHo5LwbO39QfKiTZtOOojWUUv2RXCmk8jaFwgGXraKbbl2280XAwe7V6Oj8?= =?us-ascii?Q?Nz7UMWVLqQ8/tbvIjWMrP+Lr078qhCA7NfPy5ofEf6955Vpot5assG6UW7p/?= =?us-ascii?Q?wpkVGPDtGRNouU4Qv5mwZlRmKMgD48LoJOWhLwoYcfp0dpe9xC4Z+WT4iDkZ?= =?us-ascii?Q?PYKSO0Sib2B56PsZbQDZnKdEXqddnwoA0PeYQUqQfENTD4hYv29xrztCYch7?= =?us-ascii?Q?UR+UoFXZMmAoRDs6OeC3EAH69MPS+BE7I7+gRldAIQFBxryInOdsdMEbujxh?= =?us-ascii?Q?gOZG5tJaQlkbJORbvVB54r0OfC6Nm1zWul7BMmbAnax/aVeCZDz0oqh5yFxe?= =?us-ascii?Q?a2XWVrOyF04xCCULhI0IYZMx7kb2zYfyDwhXqmrXbiVwn4oYbIUC0sKMOyUL?= =?us-ascii?Q?yMp5OG5ECYDbktnGVICnDM6KboaQppjoKiwiGQymhonbG8l7HnyifHub5Zs0?= =?us-ascii?Q?od+Y8DOdPiWgp+LD3LSMcAdQNhwvKEetp0+qRd746CXPP0JN5acxLRbvZPZ5?= =?us-ascii?Q?SLPmSiRiJQRCGWUKpDdrgZo4JPijXUp+6e1pZnrXG+NjFnUi/4Oy+85gVp7v?= =?us-ascii?Q?ZCu/PMbyM+V4XLWLldoZlvl6JgHgwFuSDoqRV7n6hvs4FGRo8BLuT/rHvXWj?= =?us-ascii?Q?IOnc50xu4/IzUPaSTyuQEkXZuxoTraADWAKxzI2levULitX7VUd1/IURsNMw?= =?us-ascii?Q?szOAXn1IbG/YaTCy744SxqXnZAqlBhS0wwTiQUS3pulkt/4lQfb0WC/sRlrA?= =?us-ascii?Q?QNVucerefNv3w5SCX8Q4fitNGfs3E23ltuhv/PI5dIsJqZjn1lsuWijvWw0N?= =?us-ascii?Q?nXYDbrNBGe+XoQkozlU61x7Zdc+/zfWS3CWENCTtvLBOp8Ehaaml/Pj1qtWr?= =?us-ascii?Q?fNp2bvDFQDqr0o1NpFQgxq8fijeRsKN05pIcjSm7bVN3KkvR6A=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(7416014)(36860700013)(376014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 21:55:25.7809 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 88da9bd6-d179-44b8-78ed-08dcfde48e1d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B374.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6522 Content-Type: text/plain; charset="utf-8" Restructure taa mitigation to use select/update/apply functions to create consistent vulnerability handling. Signed-off-by: David Kaplan --- arch/x86/kernel/cpu/bugs.c | 58 +++++++++++++++++++++++++------------- 1 file changed, 39 insertions(+), 19 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 4f35dcd9dee8..c676804dfd84 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -65,6 +65,8 @@ static void __init mds_apply_mitigation(void); static void __init md_clear_update_mitigation(void); static void __init md_clear_select_mitigation(void); static void __init taa_select_mitigation(void); +static void __init taa_update_mitigation(void); +static void __init taa_apply_mitigation(void); static void __init mmio_select_mitigation(void); static void __init srbds_select_mitigation(void); static void __init l1d_flush_select_mitigation(void); @@ -187,6 +189,7 @@ void __init cpu_select_mitigations(void) ssb_select_mitigation(); l1tf_select_mitigation(); mds_select_mitigation(); + taa_select_mitigation(); md_clear_select_mitigation(); srbds_select_mitigation(); l1d_flush_select_mitigation(); @@ -203,8 +206,10 @@ void __init cpu_select_mitigations(void) * choices. */ mds_update_mitigation(); + taa_update_mitigation(); =20 mds_apply_mitigation(); + taa_apply_mitigation(); } =20 /* @@ -374,9 +379,6 @@ static int __init mds_cmdline(char *str) } early_param("mds", mds_cmdline); =20 -#undef pr_fmt -#define pr_fmt(fmt) "TAA: " fmt - static bool taa_nosmt __ro_after_init; =20 static const char * const taa_strings[] =3D { @@ -399,19 +401,19 @@ static void __init taa_select_mitigation(void) return; } =20 - if (cpu_mitigations_off()) { + if (cpu_mitigations_off()) taa_mitigation =3D TAA_MITIGATION_OFF; - return; - } =20 /* * TAA mitigation via VERW is turned off if both * tsx_async_abort=3Doff and mds=3Doff are specified. + * + * MDS mitigation will be checked in taa_update_mitigation(). */ - if (taa_mitigation =3D=3D TAA_MITIGATION_OFF && - mds_mitigation =3D=3D MDS_MITIGATION_OFF) + if (taa_mitigation =3D=3D TAA_MITIGATION_OFF) return; =20 + /* This handles the AUTO case. */ if (boot_cpu_has(X86_FEATURE_MD_CLEAR)) taa_mitigation =3D TAA_MITIGATION_VERW; else @@ -430,17 +432,36 @@ static void __init taa_select_mitigation(void) !(x86_arch_cap_msr & ARCH_CAP_TSX_CTRL_MSR)) taa_mitigation =3D TAA_MITIGATION_UCODE_NEEDED; =20 - /* - * TSX is enabled, select alternate mitigation for TAA which is - * the same as MDS. Enable MDS static branch to clear CPU buffers. - * - * For guests that can't determine whether the correct microcode is - * present on host, enable the mitigation for UCODE_NEEDED as well. - */ - setup_force_cpu_cap(X86_FEATURE_CLEAR_CPU_BUF); +} + +static void __init taa_update_mitigation(void) +{ + if (!boot_cpu_has_bug(X86_BUG_TAA)) + return; + + if (mitigate_any_verw()) + taa_mitigation =3D TAA_MITIGATION_VERW; + + pr_info("TAA: %s\n", taa_strings[taa_mitigation]); +} + +static void __init taa_apply_mitigation(void) +{ + if (taa_mitigation =3D=3D TAA_MITIGATION_VERW || + taa_mitigation =3D=3D TAA_MITIGATION_UCODE_NEEDED) { + /* + * TSX is enabled, select alternate mitigation for TAA which is + * the same as MDS. Enable MDS static branch to clear CPU buffers. + * + * For guests that can't determine whether the correct microcode is + * present on host, enable the mitigation for UCODE_NEEDED as well. + */ + setup_force_cpu_cap(X86_FEATURE_CLEAR_CPU_BUF); + + if (taa_nosmt || cpu_mitigations_auto_nosmt()) + cpu_smt_disable(false); + } =20 - if (taa_nosmt || cpu_mitigations_auto_nosmt()) - cpu_smt_disable(false); } =20 static int __init tsx_async_abort_parse_cmdline(char *str) @@ -649,7 +670,6 @@ static void __init md_clear_update_mitigation(void) =20 static void __init md_clear_select_mitigation(void) { - taa_select_mitigation(); mmio_select_mitigation(); rfds_select_mitigation(); =20 --=20 2.34.1 From nobody Sun Nov 24 11:56:51 2024 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2082.outbound.protection.outlook.com [40.107.220.82]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD02B216427 for ; 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Tue, 5 Nov 2024 15:55:24 -0600 From: David Kaplan To: Thomas Gleixner , Borislav Petkov , Peter Zijlstra , Josh Poimboeuf , Pawan Gupta , Ingo Molnar , Dave Hansen , , "H . Peter Anvin" CC: Subject: [PATCH v2 06/35] x86/bugs: Restructure mmio mitigation Date: Tue, 5 Nov 2024 15:54:26 -0600 Message-ID: <20241105215455.359471-7-david.kaplan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105215455.359471-1-david.kaplan@amd.com> References: <20241105215455.359471-1-david.kaplan@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B374:EE_|MW4PR12MB7013:EE_ X-MS-Office365-Filtering-Correlation-Id: fb6e32b1-fce0-4c75-2800-08dcfde48e4d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|1800799024|7416014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?UI6Ti2silt1yimYLzrCCSwyU1VFEG2JF/rMARgvqVR4QOIQUWYn6S/MOcuyf?= =?us-ascii?Q?F4+uWuwXHISIxC0P8VpnKeIw7Xq5nqKdQcf/cmtAaqq2m9kn1mH2RGOVT+CW?= =?us-ascii?Q?ky4at5dot+wUmBGsd5td6FbPrew5ckBUg/J7TLsGkM1etxQtxtMGtMKQq0Wh?= =?us-ascii?Q?BNXn0StzyWK4HaykO4dDecFL0qYPRYRfDxuQvo6k6XGGrT9gKwVcc5+7KrIS?= =?us-ascii?Q?bWQt8JdezzztdszW9h3A2w37QvUOjFTbXpMecZeTsxxC/K0zdBTnpVnJBJ2o?= =?us-ascii?Q?XJ4Htx3cQvLavrBlcVqV4MRfcp/ajpLxjdACkIt07eOfRUlR4nBf/RB8nh8l?= =?us-ascii?Q?BpiV3gffv0a46M7/WxMClIyb7jawnIB8+5Z8qtt7DRfJT5a1BKADfoaKhOBw?= =?us-ascii?Q?uTAeZfmkHoH4JzZOpUeaN82I5gqSO+t5aL1mKmo90GKh+NGUy8CoEXLcxzJB?= =?us-ascii?Q?SQtLc9XKKRwLoZ8k/feTPWN7s/z97M7twnzWPqQjNohtorAn3b4EVbb96sCq?= =?us-ascii?Q?X7SAFQDKBwShicOW370itt22Uu2OmzzJRY2/ukIQdlXvJCnGArfAczCVAq6A?= =?us-ascii?Q?vuXJrEPmYhNhkhvXu74SaavP1rIExfLv2Mvf2LgRY0arGmGOqiVUoxBpEbeu?= =?us-ascii?Q?x/HWe3s8HT+dACVUfF2U5zspl/mskNIRLnGQDiNDSs38GiD1vZdj32zk0MpW?= =?us-ascii?Q?IuCv6L3/15U3Rn6S2qU2e+nPWoNQRh7CdmDXrGyPUz0Dt7nQaa/j9P1B+Dfx?= =?us-ascii?Q?wL0qtuFkGjZwhdFx4TSC6SiSxbtIkiA55Dro5X2ahEJS+aieDTf8KCwdWQfu?= =?us-ascii?Q?2pVZw8U+XrYZ3Ik7fr1iaZsualwjEtf2WU3xkz3F5gM+rgLxcPrwyAANGZCL?= =?us-ascii?Q?GB5os+aTOH8s6IxAboe/H6KvC1IF1obz5qKi12/9GzwXFkK1zwQll+iNagk9?= =?us-ascii?Q?gLLspyLSEDIajHmU38SegjL51ndCY2sFkEY0u5o2gwK0n9lbYAXtZBkNcyh+?= =?us-ascii?Q?J0KtAQpY+sNSZFg0X5VoUifkR0hIH9G0pc7njwUndAV/eeiPTiwQrrUksgns?= =?us-ascii?Q?ZcVlMARAuQhcjPCMxy0/giYoYP3DvJyaoqyLlE0SX7vJJxqhSEWIXgkczrj8?= =?us-ascii?Q?bVxJgR3CYngNoec1aAqjWOLHWNy8id57fqGiFz1S/hJHXRT7mZqv+kk0iFtL?= =?us-ascii?Q?X+o2dG9lGs+yUs+gdR9kYQ0ty/2hc563bRsEkEihh4TF+Yebnb/cz7QUYOQW?= =?us-ascii?Q?vjR2JzZn5MdjpQ0AEII8/IcCaHhz2XceDP1nJU4MsQnLa59EVqH/vGT1nELy?= =?us-ascii?Q?37KFg3x8rkJB/EgKUDJVtZTjzioDwls9AcmzsQGOLcOzQL7c+aC/PUwGyvnX?= =?us-ascii?Q?h0H1nR+AmBI6R0VHPI8CXosBciGXUAiFx+MoQrJqlxoZwJxoUw=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(36860700013)(1800799024)(7416014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 21:55:26.0934 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fb6e32b1-fce0-4c75-2800-08dcfde48e4d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B374.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7013 Content-Type: text/plain; charset="utf-8" Restructure mmio mitigation to use select/update/apply functions to create consistent vulnerability handling. Signed-off-by: David Kaplan --- arch/x86/kernel/cpu/bugs.c | 55 +++++++++++++++++++++++++++----------- 1 file changed, 39 insertions(+), 16 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index c676804dfd84..1332b70e48f8 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -68,6 +68,8 @@ static void __init taa_select_mitigation(void); static void __init taa_update_mitigation(void); static void __init taa_apply_mitigation(void); static void __init mmio_select_mitigation(void); +static void __init mmio_update_mitigation(void); +static void __init mmio_apply_mitigation(void); static void __init srbds_select_mitigation(void); static void __init l1d_flush_select_mitigation(void); static void __init srso_select_mitigation(void); @@ -190,6 +192,7 @@ void __init cpu_select_mitigations(void) l1tf_select_mitigation(); mds_select_mitigation(); taa_select_mitigation(); + mmio_select_mitigation(); md_clear_select_mitigation(); srbds_select_mitigation(); l1d_flush_select_mitigation(); @@ -207,9 +210,11 @@ void __init cpu_select_mitigations(void) */ mds_update_mitigation(); taa_update_mitigation(); + mmio_update_mitigation(); =20 mds_apply_mitigation(); taa_apply_mitigation(); + mmio_apply_mitigation(); } =20 /* @@ -505,6 +510,40 @@ static void __init mmio_select_mitigation(void) return; } =20 + if (mmio_mitigation =3D=3D MMIO_MITIGATION_OFF) + return; + + /* + * Check if the system has the right microcode. + * + * CPU Fill buffer clear mitigation is enumerated by either an explicit + * FB_CLEAR or by the presence of both MD_CLEAR and L1D_FLUSH on MDS + * affected systems. + */ + if ((x86_arch_cap_msr & ARCH_CAP_FB_CLEAR) || + (boot_cpu_has(X86_FEATURE_MD_CLEAR) && + boot_cpu_has(X86_FEATURE_FLUSH_L1D) && + !(x86_arch_cap_msr & ARCH_CAP_MDS_NO))) + mmio_mitigation =3D MMIO_MITIGATION_VERW; + else + mmio_mitigation =3D MMIO_MITIGATION_UCODE_NEEDED; +} + +static void __init mmio_update_mitigation(void) +{ + if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) + return; + + if (mitigate_any_verw()) + mmio_mitigation =3D MMIO_MITIGATION_VERW; + + pr_info("%s\n", mmio_strings[mmio_mitigation]); + if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN)) + pr_info("Unknown: No mitigations\n"); +} + +static void __init mmio_apply_mitigation(void) +{ if (mmio_mitigation =3D=3D MMIO_MITIGATION_OFF) return; =20 @@ -533,21 +572,6 @@ static void __init mmio_select_mitigation(void) if (!(x86_arch_cap_msr & ARCH_CAP_FBSDP_NO)) static_branch_enable(&mds_idle_clear); =20 - /* - * Check if the system has the right microcode. - * - * CPU Fill buffer clear mitigation is enumerated by either an explicit - * FB_CLEAR or by the presence of both MD_CLEAR and L1D_FLUSH on MDS - * affected systems. - */ - if ((x86_arch_cap_msr & ARCH_CAP_FB_CLEAR) || - (boot_cpu_has(X86_FEATURE_MD_CLEAR) && - boot_cpu_has(X86_FEATURE_FLUSH_L1D) && - !(x86_arch_cap_msr & ARCH_CAP_MDS_NO))) - mmio_mitigation =3D MMIO_MITIGATION_VERW; - else - mmio_mitigation =3D MMIO_MITIGATION_UCODE_NEEDED; - if (mmio_nosmt || cpu_mitigations_auto_nosmt()) cpu_smt_disable(false); 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Peter Anvin" CC: Subject: [PATCH v2 07/35] x86/bugs: Restructure rfds mitigation Date: Tue, 5 Nov 2024 15:54:27 -0600 Message-ID: <20241105215455.359471-8-david.kaplan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105215455.359471-1-david.kaplan@amd.com> References: <20241105215455.359471-1-david.kaplan@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B374:EE_|DS7PR12MB8323:EE_ X-MS-Office365-Filtering-Correlation-Id: 65a08019-73c9-4750-2135-08dcfde48ee8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|7416014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?19myPaHI/MHXrlPsfTZaZClTE9w0SSSVm2cTzLJ/ZGRBGO6V/u2AKZIOg7XK?= =?us-ascii?Q?hLACbx4Ahe6PoggL4B1T+RQFBT/U9lLpPFhe17HvrAU3gmdKxjilosNMewpg?= =?us-ascii?Q?xRXR87kMQdDWr+davu2D4vh20QLcwCHO4imtSd/c5/a60VeCviax/olCSLRN?= =?us-ascii?Q?7qFVRrhhy4YaUxkPhmYFhaXYR0lVkMGSNuPkl6bY/PKLRwA3TijGvoa1Wc4m?= =?us-ascii?Q?hUp4+0tJPfEr2vcABf0yaWz/PbZuWc6wX+sfQGYVFGtj0wEXmNgOX84Nm7In?= =?us-ascii?Q?FIA8DGDp4AGXMb3E1+4PlHgHpkkV+TkSpifWFC4ZVrCx90h8jIz7J28OTahF?= =?us-ascii?Q?sXKpA79T/xZjis8e/IqLOVEzRsfWKBM2xz3Xyw+WcNTKw+851RldALh++8Xn?= =?us-ascii?Q?tDGKbuBvVkDr1J4gZle3V1ln+tqYFkGAkkAjAGWEMoMRQumRwCblOBcwpwyq?= =?us-ascii?Q?5f1oOpHjyqxtpXPD3NszzgYwcc+zvoSP6Q7KK1JeAgjNN5UsRDIuOSCnV+vy?= =?us-ascii?Q?VpI853NybYksWEra9Hua58dyThEr7erT8j2A8WTepnkfl5p9ZQLv4kKnug2S?= =?us-ascii?Q?8QVi7YPVQLkQU8eMQFmtPK6vLE7lebqdUZklL5OCpFQIGN5TTDCLBk0kozT+?= =?us-ascii?Q?noRKr6ahWahhvZWfEOHfjiaP2MYdyUriZG5r/yrKcfokk7t1KAaWCokreM2a?= =?us-ascii?Q?SZnafi+4Tq8o/+H1WElSM5llwBHKscAEMLXPRIxH1YPLHip83HlZ7QHWUsan?= =?us-ascii?Q?tR/ZEw+/dJg6Wvnq1e2nVo2iM1/Z5IJUoKxYpw/iiRuUnXaiVGFRrAhE24eH?= =?us-ascii?Q?BchmidXnXtVIqABtRCYWIWRkJaCalG9K32rdr9LoUc4+aDfE6pFW9sJsT3gZ?= =?us-ascii?Q?vdu6TKUf+ot+SK944bkdw3mzfrWaQYcItnbn40V8FalFxDDmA+ZUm+Fh+ZS6?= =?us-ascii?Q?4SKnB+KnJeM36/5b2EOnbYvjFVYNHBNkOEDAACZWXAQnvYFDWvInwnNPe19o?= =?us-ascii?Q?WScvreSPKvIUD7C2q7+3BuT7xaKDdcRx7LuNCSsNN6SQLBkAjTSA+rZCcLAT?= =?us-ascii?Q?fDaoZ5n9u6jzi6DBxgxuxNlcsxNaz/jQ4TQX6X4AvXhZM+b0fRgqcVlevrFq?= =?us-ascii?Q?H5np4NjOGFNJMkW0EdvivU//v2ia6OygqTf5qm5NuNEqitGxKWDt58f01o9/?= =?us-ascii?Q?S2XHUSPphJ1y1o77h+MiFHupWdg/O19duxnqodpHdOAOJY6085TD5oPHT0pq?= =?us-ascii?Q?Y8gKaT03yPptM++ZDPtPLhvrPLjltgGN98fL3lWsyUoyMURpp7cWCJyUt95f?= =?us-ascii?Q?2pG20fXzcM0Pw5j+UbeePFD2Y0Aa9hi16zflNdIqp+U3xRIsDgknuZ7/myXs?= =?us-ascii?Q?yTHH7a4KocakRn8PP9MAS9BbXZCJdDNcOWj7/8XpFyEXx7nd3A=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(7416014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 21:55:27.1091 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 65a08019-73c9-4750-2135-08dcfde48ee8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B374.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8323 Content-Type: text/plain; charset="utf-8" Restructure rfds mitigation to use select/update/apply functions to create consistent vulnerability handling. Signed-off-by: David Kaplan --- arch/x86/kernel/cpu/bugs.c | 33 ++++++++++++++++++++++++++------- 1 file changed, 26 insertions(+), 7 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 1332b70e48f8..c3a2d3b8d153 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -70,6 +70,9 @@ static void __init taa_apply_mitigation(void); static void __init mmio_select_mitigation(void); static void __init mmio_update_mitigation(void); static void __init mmio_apply_mitigation(void); +static void __init rfds_select_mitigation(void); +static void __init rfds_update_mitigation(void); +static void __init rfds_apply_mitigation(void); static void __init srbds_select_mitigation(void); static void __init l1d_flush_select_mitigation(void); static void __init srso_select_mitigation(void); @@ -193,6 +196,7 @@ void __init cpu_select_mitigations(void) mds_select_mitigation(); taa_select_mitigation(); mmio_select_mitigation(); + rfds_select_mitigation(); md_clear_select_mitigation(); srbds_select_mitigation(); l1d_flush_select_mitigation(); @@ -211,10 +215,12 @@ void __init cpu_select_mitigations(void) mds_update_mitigation(); taa_update_mitigation(); mmio_update_mitigation(); + rfds_update_mitigation(); =20 mds_apply_mitigation(); taa_apply_mitigation(); mmio_apply_mitigation(); + rfds_apply_mitigation(); } =20 /* @@ -597,9 +603,6 @@ static int __init mmio_stale_data_parse_cmdline(char *s= tr) } early_param("mmio_stale_data", mmio_stale_data_parse_cmdline); =20 -#undef pr_fmt -#define pr_fmt(fmt) "Register File Data Sampling: " fmt - static const char * const rfds_strings[] =3D { [RFDS_MITIGATION_OFF] =3D "Vulnerable", [RFDS_MITIGATION_VERW] =3D "Mitigation: Clear Register File", @@ -618,12 +621,29 @@ static void __init rfds_select_mitigation(void) if (rfds_mitigation =3D=3D RFDS_MITIGATION_AUTO) rfds_mitigation =3D RFDS_MITIGATION_VERW; =20 - if (x86_arch_cap_msr & ARCH_CAP_RFDS_CLEAR) - setup_force_cpu_cap(X86_FEATURE_CLEAR_CPU_BUF); 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Tue, 5 Nov 2024 15:55:25 -0600 From: David Kaplan To: Thomas Gleixner , Borislav Petkov , Peter Zijlstra , Josh Poimboeuf , Pawan Gupta , Ingo Molnar , Dave Hansen , , "H . Peter Anvin" CC: Subject: [PATCH v2 08/35] x86/bugs: Remove md_clear_*_mitigation() Date: Tue, 5 Nov 2024 15:54:28 -0600 Message-ID: <20241105215455.359471-9-david.kaplan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105215455.359471-1-david.kaplan@amd.com> References: <20241105215455.359471-1-david.kaplan@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B374:EE_|CH3PR12MB7666:EE_ X-MS-Office365-Filtering-Correlation-Id: 3d7c1ae7-3e59-4df0-a788-08dcfde48f2f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|7416014|376014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?g0M4MSltHeiVyBhzTxcFi3iW6nRkHvZxi/oAWBlifHNTkEA1V8imb83T85pC?= =?us-ascii?Q?tO9Rc2XKRJxaord0y+MG9wBhhjL0SVAQEluPtAfwTGBm8NfBk78MnJh+nf+k?= =?us-ascii?Q?8cokzwl4kt8uKHVqEQLH56tZKzlZopaWIn3QmEzQnm8U5H7B7mM1qg/6WZ2c?= =?us-ascii?Q?2yZc1DKZ63PwQvcWAizsRcLKyjd3QC0j/alg4ToBPBp3Q5Lb27kn3v75hpB6?= =?us-ascii?Q?guF5ukUEbQUIKsKu4J49yeCTWGqS9q5blkTm0QBj9wRQv/+I3Rbms1RoriWu?= =?us-ascii?Q?Zjotx4MrShGBjLccirYQyUtkfUX4p4u7TID23+oyLwFd7KutwFrPDLrXbShp?= =?us-ascii?Q?uRkNpHTJ8ycO9J3EiEJdLbB7Q5v5LlUGOOa8+shj9hgeTKL1/tSMGaN6qP5A?= =?us-ascii?Q?HM8GF0bcq9ch4o/CvKzcnyElOpvOifPpLHvTNWzMRXjceDaV+JDOvcC/8guU?= =?us-ascii?Q?2+pOjS9ovFMFRxzo9RsF9MOu9w/OXFmdwSz7OcRw7NZnxQisXSHremm9BAp5?= =?us-ascii?Q?CUGS5ZOAVsqMI3H7PXIm7yDATKePeMFsYddJuVW9xNe/kxuCRofGaK/vAzOw?= =?us-ascii?Q?1Wm/ZacNRNKnQtpY/V1/D+NsdVsFrbvFtVycLWVWE7k9G8Tv6XL/40+TjHWt?= =?us-ascii?Q?fdo5c+xio7a/cLlrEDtEMMNNq2gjzAIbIoN6XTFPKQ/Ut/vETH0dYlYShS8s?= =?us-ascii?Q?Xw0MyLNMusID0EMtlfml4FVLhB1nCOT0i0AyH/SVOfZhME5rZb33y/BdLCGj?= =?us-ascii?Q?w8D5TwNhSPuPaqT1tcwdJlOM81I+P/HqPoNtI4H0Ax5xaWjdp740Q9tbZuK2?= =?us-ascii?Q?iOuXarT0PXkPBjr4L62mveNNoCKCO+7UMbTCldFIdG0QUbrpgbOizv8MHXvf?= =?us-ascii?Q?flQ5+Y74Etla3pV1rBN0XMZyjirxNT4mzQ0xNWYQxgZlv/4I0Xj1uP0GR5Hb?= =?us-ascii?Q?sm3lU9Iga0kAl6x51wPHeg+y0aunZHNeCq5AflRqUn0OWlZ99ZDt8oMb/9/h?= =?us-ascii?Q?WSUJNZZWdkEUty10s19wf2QfCg8toMtYVCDPzSkwOZcqtsNLspbwgxXMjwEh?= =?us-ascii?Q?cDLkdJXE6smKApjWavm2pBu3Zr4jtj0ZREPEOLqgtaOTbKVtFMJK5fAtwcF5?= =?us-ascii?Q?cGjFoxc6BtJPWQeZDBTJt4NMIRzDJMhw7RD4GgwhiMadx+PcqizOPxt7V+P/?= =?us-ascii?Q?paOtglZEmvrYO4fTZ7A35uQsVvGP7U/Q/uLGRARV0Ms4Jkvx9ZLfkONWu/DQ?= =?us-ascii?Q?zYFQn7EXz3jfcvhZRbukiOnmv7MArVPatd0Yc3eIspKWvmNPCd/8BvdwndAv?= =?us-ascii?Q?W/sGPI2Qwm8mQr9OX6U2JMqU75VwfQsYytReic77nox5r3YBOpoWZgq+fX/7?= =?us-ascii?Q?ZgfFqAtLGmv+G9Hy3Y9CoH0bQYS8By7aszx4au91s9+YMY/rGg=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(7416014)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 21:55:27.5778 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3d7c1ae7-3e59-4df0-a788-08dcfde48f2f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B374.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7666 Content-Type: text/plain; charset="utf-8" The functionality in md_clear_update_mitigation() and md_clear_select_mitigation() is now integrated into the select/update functions for the MDS, TAA, MMIO, and RFDS vulnerabilities. Signed-off-by: David Kaplan --- arch/x86/kernel/cpu/bugs.c | 65 -------------------------------------- 1 file changed, 65 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index c3a2d3b8d153..5ad989e8eea3 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -62,8 +62,6 @@ static void __init l1tf_select_mitigation(void); static void __init mds_select_mitigation(void); static void __init mds_update_mitigation(void); static void __init mds_apply_mitigation(void); -static void __init md_clear_update_mitigation(void); -static void __init md_clear_select_mitigation(void); static void __init taa_select_mitigation(void); static void __init taa_update_mitigation(void); static void __init taa_apply_mitigation(void); @@ -197,7 +195,6 @@ void __init cpu_select_mitigations(void) taa_select_mitigation(); mmio_select_mitigation(); rfds_select_mitigation(); - md_clear_select_mitigation(); srbds_select_mitigation(); l1d_flush_select_mitigation(); =20 @@ -661,68 +658,6 @@ static __init int rfds_parse_cmdline(char *str) } early_param("reg_file_data_sampling", rfds_parse_cmdline); =20 -#undef pr_fmt -#define pr_fmt(fmt) "" fmt - -static void __init md_clear_update_mitigation(void) -{ - if (cpu_mitigations_off()) - return; - - if (!boot_cpu_has(X86_FEATURE_CLEAR_CPU_BUF)) - goto out; - - /* - * X86_FEATURE_CLEAR_CPU_BUF is now enabled. Update MDS, TAA and MMIO - * Stale Data mitigation, if necessary. - */ - if (mds_mitigation =3D=3D MDS_MITIGATION_OFF && - boot_cpu_has_bug(X86_BUG_MDS)) { - mds_mitigation =3D MDS_MITIGATION_FULL; - mds_select_mitigation(); - } - if (taa_mitigation =3D=3D TAA_MITIGATION_OFF && - boot_cpu_has_bug(X86_BUG_TAA)) { - taa_mitigation =3D TAA_MITIGATION_VERW; - taa_select_mitigation(); - } - /* - * MMIO_MITIGATION_OFF is not checked here so that mmio_stale_data_clear - * gets updated correctly as per X86_FEATURE_CLEAR_CPU_BUF state. - */ - if (boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) { - mmio_mitigation =3D MMIO_MITIGATION_VERW; - mmio_select_mitigation(); - } - if (rfds_mitigation =3D=3D RFDS_MITIGATION_OFF && - boot_cpu_has_bug(X86_BUG_RFDS)) { - rfds_mitigation =3D RFDS_MITIGATION_VERW; - rfds_select_mitigation(); - } -out: - if (boot_cpu_has_bug(X86_BUG_MDS)) - pr_info("MDS: %s\n", mds_strings[mds_mitigation]); - if (boot_cpu_has_bug(X86_BUG_TAA)) - pr_info("TAA: %s\n", taa_strings[taa_mitigation]); - if (boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) - pr_info("MMIO Stale Data: %s\n", mmio_strings[mmio_mitigation]); - else if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN)) - pr_info("MMIO Stale Data: Unknown: No mitigations\n"); - if (boot_cpu_has_bug(X86_BUG_RFDS)) - pr_info("Register File Data Sampling: %s\n", rfds_strings[rfds_mitigatio= n]); -} - -static void __init md_clear_select_mitigation(void) -{ - - /* - * As these mitigations are inter-related and rely on VERW instruction - * to clear the microarchitural buffers, update and print their status - * after mitigation selection is done for each of these vulnerabilities. - */ - md_clear_update_mitigation(); -} - #undef pr_fmt #define pr_fmt(fmt) "SRBDS: " fmt =20 --=20 2.34.1 From nobody Sun Nov 24 11:56:51 2024 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2087.outbound.protection.outlook.com [40.107.236.87]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 98E63216A2E for ; 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Tue, 5 Nov 2024 15:55:25 -0600 From: David Kaplan To: Thomas Gleixner , Borislav Petkov , Peter Zijlstra , Josh Poimboeuf , Pawan Gupta , Ingo Molnar , Dave Hansen , , "H . Peter Anvin" CC: Subject: [PATCH v2 09/35] x86/bugs: Restructure srbds mitigation Date: Tue, 5 Nov 2024 15:54:29 -0600 Message-ID: <20241105215455.359471-10-david.kaplan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105215455.359471-1-david.kaplan@amd.com> References: <20241105215455.359471-1-david.kaplan@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B374:EE_|DM4PR12MB6182:EE_ X-MS-Office365-Filtering-Correlation-Id: eac9e547-1cb2-4234-a36d-08dcfde48f8c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|7416014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?t/QgjHZ/tWDJ+17Px+IFX9Tmuih/j02/MP3Mf7a4UTgojyUGuy4e5mfjEKbv?= =?us-ascii?Q?9btVY2Vu6R03r8cp+mWRzvlvthlkr07N9E/ZhwSW8egeJqDTJPaM8q0FWqnz?= =?us-ascii?Q?aZ7qlx7OKtjhsDGo6WWiFsXf6jqpowbOZxyzmCq1V0u2ml/okM3RUBw/as8L?= =?us-ascii?Q?uPDmI6UqTF0xsdhDVpBkkM7eSC/BzQvMvX305KIrmzQXex3P3ppTOecFYfIR?= =?us-ascii?Q?ghEi7+gIZd01AGYbcFyiV1L9vuEAZmSjV64/E4DcZGdof1a4+Tdo3iwqrJ4W?= =?us-ascii?Q?hocMJkU/zqxE4a26BQt9kbzNVphVbObcj1wO9RWUWqkHKKxB+OElsRh4u3Jf?= =?us-ascii?Q?useOCDUwyyUxoz5xRqBL3iZh1q8R5vy0Q9LOPp/M4c9ZFaJlGKFszDQK5nP2?= =?us-ascii?Q?siEJTT3tgg1E7LinXIxIqhoBkVqcu4ZgZauJwUAPoEXKM54yLThFTwGVfHpF?= =?us-ascii?Q?IlLbPxztZ26K+evPJEdYjZFseACeLfxcooJGuXTzM+2x45BPdyZhPihF36//?= =?us-ascii?Q?ENyzxuSS9mPFlgO4znBJg4ybG18EOzi22Hg0GWKdukuyt2Pdh5PD5KOZ87IR?= =?us-ascii?Q?lkS00Sftqwpvz+ABU2eRcC2AdC7WmHbHwBAa3fa1cBsWpMH2axBJ7FlH1nEc?= =?us-ascii?Q?x1eB1D+m89CKrkcZGRRBHVRY7fHsPPqIgf7EsSrjEsENmxio1W6R/SHJ5Cwc?= =?us-ascii?Q?gbo2OSOpyCPyzWQny+OOPEkdl+za4UFLjaQVWn2kw5YsA7Kb0NuvwU3EEQk8?= =?us-ascii?Q?iRu7flpeE2+mIwA3fHeFhnQ9n7uuDZKBXrUU3iarMCYwh74OL3svHckTcfM+?= =?us-ascii?Q?o/ipYIUAFxfypohyz6jLbeLjIGj8NDDEBlxHFgCp27sqSzt3YRnp0IrBC2iM?= =?us-ascii?Q?IZwwbnsL+Y7IPOG+qApITxuO+Go8PggyJZwt2tGNQveRC3RSYiDUnVjltqfN?= =?us-ascii?Q?fV6O8nsiqGrHS+UXuTRf4sSFWoYL9GJSnHCDs27ZMca3U/9Vz3+J06KSGyA8?= =?us-ascii?Q?D3FMft0mofphbK08oT0E27E2AcNSAdToFN1hRWUcSlAaLf4HkF0dYephbq7m?= =?us-ascii?Q?XozMke4VhDCUJXXx97kN56Pd8+vRl8nsWf2l2qxmb5cxengpu4r9Ws6OW1QT?= =?us-ascii?Q?cMthvgw/G+GveIDmKQVa6wZ2iS6klFYY31xYqxqzxFTrWP9xI7BYotYd30Il?= =?us-ascii?Q?/g4RI3JhDguVhuq7XUwA6gXb6ag6AElpNSZSPL+mTNe5M0iFcPDcthdllu+f?= =?us-ascii?Q?gMH2tsyG47Q7/PFtGX3F3h9Uu7Be09/0xnlqCUX3pqzqlAxMTroCl1WCv5ZR?= =?us-ascii?Q?U9/8myLoqqZG18NRIUdfanqfH7KMIMjF4hHuh/g9f7ULIkPi7fePAtbDP/k5?= =?us-ascii?Q?YwmNlS1JS3Jub+p4mBCUtc4JIIVOhW3V4nNRyXCL3Uotu21vLQ=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(7416014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 21:55:28.1872 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eac9e547-1cb2-4234-a36d-08dcfde48f8c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B374.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6182 Content-Type: text/plain; charset="utf-8" Restructure srbds to use select/apply functions to create consistent vulnerability handling. Define new AUTO mitigation for SRBDS. Signed-off-by: David Kaplan --- arch/x86/kernel/cpu/bugs.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 5ad989e8eea3..452aa5994aac 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -72,6 +72,7 @@ static void __init rfds_select_mitigation(void); static void __init rfds_update_mitigation(void); static void __init rfds_apply_mitigation(void); static void __init srbds_select_mitigation(void); +static void __init srbds_apply_mitigation(void); static void __init l1d_flush_select_mitigation(void); static void __init srso_select_mitigation(void); static void __init gds_select_mitigation(void); @@ -218,6 +219,7 @@ void __init cpu_select_mitigations(void) taa_apply_mitigation(); mmio_apply_mitigation(); rfds_apply_mitigation(); + srbds_apply_mitigation(); } =20 /* @@ -663,6 +665,7 @@ early_param("reg_file_data_sampling", rfds_parse_cmdlin= e); =20 enum srbds_mitigations { SRBDS_MITIGATION_OFF, + SRBDS_MITIGATION_AUTO, SRBDS_MITIGATION_UCODE_NEEDED, SRBDS_MITIGATION_FULL, SRBDS_MITIGATION_TSX_OFF, @@ -670,7 +673,7 @@ enum srbds_mitigations { }; =20 static enum srbds_mitigations srbds_mitigation __ro_after_init =3D - IS_ENABLED(CONFIG_MITIGATION_SRBDS) ? SRBDS_MITIGATION_FULL : SRBDS_MITIG= ATION_OFF; + IS_ENABLED(CONFIG_MITIGATION_SRBDS) ? SRBDS_MITIGATION_AUTO : SRBDS_MITIG= ATION_OFF; =20 static const char * const srbds_strings[] =3D { [SRBDS_MITIGATION_OFF] =3D "Vulnerable", @@ -724,6 +727,9 @@ static void __init srbds_select_mitigation(void) if (!boot_cpu_has_bug(X86_BUG_SRBDS)) return; =20 + if (srbds_mitigation =3D=3D SRBDS_MITIGATION_AUTO) + srbds_mitigation =3D SRBDS_MITIGATION_FULL; + /* * Check to see if this is one of the MDS_NO systems supporting TSX that * are only exposed to SRBDS when TSX is enabled or when CPU is affected @@ -738,6 +744,12 @@ static void __init srbds_select_mitigation(void) srbds_mitigation =3D SRBDS_MITIGATION_UCODE_NEEDED; else if (cpu_mitigations_off() || srbds_off) srbds_mitigation =3D SRBDS_MITIGATION_OFF; +} + +static void __init srbds_apply_mitigation(void) +{ + if (!boot_cpu_has_bug(X86_BUG_SRBDS)) + return; =20 update_srbds_msr(); pr_info("%s\n", srbds_strings[srbds_mitigation]); --=20 2.34.1 From nobody Sun Nov 24 11:56:51 2024 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2055.outbound.protection.outlook.com [40.107.236.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D0C22170CE for ; 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Tue, 5 Nov 2024 15:55:26 -0600 From: David Kaplan To: Thomas Gleixner , Borislav Petkov , Peter Zijlstra , Josh Poimboeuf , Pawan Gupta , Ingo Molnar , Dave Hansen , , "H . Peter Anvin" CC: Subject: [PATCH v2 10/35] x86/bugs: Restructure gds mitigation Date: Tue, 5 Nov 2024 15:54:30 -0600 Message-ID: <20241105215455.359471-11-david.kaplan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105215455.359471-1-david.kaplan@amd.com> References: <20241105215455.359471-1-david.kaplan@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B374:EE_|PH7PR12MB7353:EE_ X-MS-Office365-Filtering-Correlation-Id: 5a0b8c4b-f3ba-418f-8c4b-08dcfde48fd6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?R2XfvSXDOfDqc44gJheeVWVUuZVhWhRNtDBzwuyyuKT/Tk22kYLZI7la7do/?= =?us-ascii?Q?msT9JplnPbCF4qSnwxsmbbxkMCdNUw+lUPHYBkFfVx4BUwCVlBIBRuP7exaX?= =?us-ascii?Q?DuFJeFLkVlGq8BtxZZ5ABPEa+ukpn/kRaviVFwILN2TmUcZUVZVXZX7urNiw?= =?us-ascii?Q?tZtD1M8/0QA8c5/fO+pNkmUf+Hpv25f2CYzcrt2aDxyHWqU2of+3orBWlPoo?= =?us-ascii?Q?I6P5dtC/GAUQzufKBSTndH+93ipLDI5w2kFVfWtKf3qgoxulAmjMthoILzGq?= =?us-ascii?Q?5NgLAfcLg9QX5xx5V2uWkSdNHBv/Bh8CYAqCRaS3bljzl3LemGwSgRU9s0LT?= =?us-ascii?Q?AekLkTnq5pGWFor7CjipghDM8qJZ6JlLmvgNeBr2UI7AF0iot1LTd9lfDlsp?= =?us-ascii?Q?CiE8SAd6Mb4mCWq8A8Msj0DUfcY9GKIC51lkoXyHDfb6DUkamVagpv1upVUQ?= =?us-ascii?Q?vN3H0VttLeaIwTVeC4J8kiGhYmNcLuoqmpCKxksWXZn7ASxnWekNXrzu5EeJ?= =?us-ascii?Q?6DBmpXZdJKvUdoW25VvnfBN+5Kpw6vIuNEbHMbS3GFidNtjg0WCfUwlwUfkV?= =?us-ascii?Q?4O7I1+IwE6RrFM+jJCw9c/gXew9ChLBrIorg0LyI5Dy+BdvNDYk1JcSK80Ab?= =?us-ascii?Q?c9ROB8Wr/Mufs/zd+xCU+0D/vKYarc4CqLxJeUcc6eij+AD1V6+/6SiWwm92?= =?us-ascii?Q?e89eGY3RxOCtNUWgJLFshVo+beXZzUejbIMtyB26R+l/GmPFYjBIteVzubSu?= =?us-ascii?Q?IfdRx3EAlg2yCD3C1/pBLXaTkL+tngQ6Reb08y26XJfMLuOeXQTV0CkSyOAj?= =?us-ascii?Q?XFNabBg36rT13dGaYlShXtf2x7CvEeYy2LZmB1NPt0KNfoiGop8kKajS2aOo?= =?us-ascii?Q?0OjcPQy9KJ3US8KOw1E/GpTwFYGRsfGK7kBjyUPIOnu6b4CX47qNGd0qrzKc?= =?us-ascii?Q?V703bW506h37sPTnwwpTMJEZ75Gd7LiNS/ubEozauL1szz0QP8Jh+s2COlDp?= =?us-ascii?Q?vIyXMktnmJ2y8nBUpXgWKT1ZVcOYBmCt3dPSc4JaH015NGlsp1hjRAq2h1df?= =?us-ascii?Q?wlQwKMICPCC0xLatYpRXZVyla5PDnuIAKS3dmxK4pEgpfdPD/fswQrXmqdud?= =?us-ascii?Q?JRQWE2TF6WfbeEk0vS+2GzVPbAwCqkcpxiTO65G09LB7p1Fgdr7uxL7laKMA?= =?us-ascii?Q?ICEdmyQUK6UV1x3T8vijQTQArxPiAUIRLGd6ZbGOTXTZuvKiIgOficpyQmFL?= =?us-ascii?Q?7rz+fDAtt0LejxAhXeiBONTK4+PuAnBJDxxY/19SrPl0gR49yIUPdVcAysnG?= =?us-ascii?Q?Sc5DGDNBuzql9PQdK/nC4hZ015keRFCgACuN1EW5t3ZTLLPAS1op0zFx2uzU?= =?us-ascii?Q?XU6NOPTZuUqClhx+XCFP9A+Lnd/sM9XHM+4lS6+xok3Tuebjdg=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 21:55:28.6716 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5a0b8c4b-f3ba-418f-8c4b-08dcfde48fd6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B374.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7353 Content-Type: text/plain; charset="utf-8" Restructure gds mitigation to use select/apply functions to create consistent vulnerability handling. Define new AUTO mitigation for gds. Signed-off-by: David Kaplan --- arch/x86/kernel/cpu/bugs.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 452aa5994aac..37056bdd3a9b 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -76,6 +76,7 @@ static void __init srbds_apply_mitigation(void); static void __init l1d_flush_select_mitigation(void); static void __init srso_select_mitigation(void); static void __init gds_select_mitigation(void); +static void __init gds_apply_mitigation(void); =20 /* The base value of the SPEC_CTRL MSR without task-specific bits set */ u64 x86_spec_ctrl_base; @@ -220,6 +221,7 @@ void __init cpu_select_mitigations(void) mmio_apply_mitigation(); rfds_apply_mitigation(); srbds_apply_mitigation(); + gds_apply_mitigation(); } =20 /* @@ -801,6 +803,7 @@ early_param("l1d_flush", l1d_flush_parse_cmdline); =20 enum gds_mitigations { GDS_MITIGATION_OFF, + GDS_MITIGATION_AUTO, GDS_MITIGATION_UCODE_NEEDED, GDS_MITIGATION_FORCE, GDS_MITIGATION_FULL, @@ -809,7 +812,7 @@ enum gds_mitigations { }; =20 static enum gds_mitigations gds_mitigation __ro_after_init =3D - IS_ENABLED(CONFIG_MITIGATION_GDS) ? GDS_MITIGATION_FULL : GDS_MITIGATION_= OFF; + IS_ENABLED(CONFIG_MITIGATION_GDS) ? GDS_MITIGATION_AUTO : GDS_MITIGATION_= OFF; =20 static const char * const gds_strings[] =3D { [GDS_MITIGATION_OFF] =3D "Vulnerable", @@ -850,6 +853,7 @@ void update_gds_msr(void) case GDS_MITIGATION_FORCE: case GDS_MITIGATION_UCODE_NEEDED: case GDS_MITIGATION_HYPERVISOR: + case GDS_MITIGATION_AUTO: return; } =20 @@ -873,13 +877,16 @@ static void __init gds_select_mitigation(void) =20 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { gds_mitigation =3D GDS_MITIGATION_HYPERVISOR; - goto out; + return; } =20 if (cpu_mitigations_off()) gds_mitigation =3D GDS_MITIGATION_OFF; /* Will verify below that mitigation _can_ be disabled */ =20 + if (gds_mitigation =3D=3D GDS_MITIGATION_AUTO) + gds_mitigation =3D GDS_MITIGATION_FULL; + /* No microcode */ if (!(x86_arch_cap_msr & ARCH_CAP_GDS_CTRL)) { if (gds_mitigation =3D=3D GDS_MITIGATION_FORCE) { @@ -892,7 +899,7 @@ static void __init gds_select_mitigation(void) } else { gds_mitigation =3D GDS_MITIGATION_UCODE_NEEDED; } - goto out; + return; } =20 /* Microcode has mitigation, use it */ @@ -914,8 +921,14 @@ static void __init gds_select_mitigation(void) gds_mitigation =3D GDS_MITIGATION_FULL_LOCKED; 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Signed-off-by: David Kaplan --- arch/x86/kernel/cpu/bugs.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 37056bdd3a9b..ea50c77ccb70 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -54,6 +54,7 @@ */ =20 static void __init spectre_v1_select_mitigation(void); +static void __init spectre_v1_apply_mitigation(void); static void __init spectre_v2_select_mitigation(void); static void __init retbleed_select_mitigation(void); static void __init spectre_v2_user_select_mitigation(void); @@ -216,6 +217,7 @@ void __init cpu_select_mitigations(void) mmio_update_mitigation(); rfds_update_mitigation(); =20 + spectre_v1_apply_mitigation(); mds_apply_mitigation(); taa_apply_mitigation(); mmio_apply_mitigation(); @@ -989,10 +991,14 @@ static bool smap_works_speculatively(void) =20 static void __init spectre_v1_select_mitigation(void) { - if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) { + if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) spectre_v1_mitigation =3D SPECTRE_V1_MITIGATION_NONE; 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The retbleed_update_mitigation() simplifies the dependency between spectre_v2 and retbleed. The command line options now directly select a preferred mitigation which simplifies the logic. Signed-off-by: David Kaplan --- arch/x86/kernel/cpu/bugs.c | 168 +++++++++++++++++-------------------- 1 file changed, 75 insertions(+), 93 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index ea50c77ccb70..36657bd7143b 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -57,6 +57,8 @@ static void __init spectre_v1_select_mitigation(void); static void __init spectre_v1_apply_mitigation(void); static void __init spectre_v2_select_mitigation(void); static void __init retbleed_select_mitigation(void); +static void __init retbleed_update_mitigation(void); +static void __init retbleed_apply_mitigation(void); static void __init spectre_v2_user_select_mitigation(void); static void __init ssb_select_mitigation(void); static void __init l1tf_select_mitigation(void); @@ -180,11 +182,6 @@ void __init cpu_select_mitigations(void) /* Select the proper CPU mitigations before patching alternatives: */ spectre_v1_select_mitigation(); spectre_v2_select_mitigation(); - /* - * retbleed_select_mitigation() relies on the state set by - * spectre_v2_select_mitigation(); specifically it wants to know about - * spectre_v2=3Dibrs. - */ retbleed_select_mitigation(); /* * spectre_v2_user_select_mitigation() relies on the state set by @@ -212,12 +209,14 @@ void __init cpu_select_mitigations(void) * After mitigations are selected, some may need to update their * choices. */ + retbleed_update_mitigation(); mds_update_mitigation(); taa_update_mitigation(); mmio_update_mitigation(); rfds_update_mitigation(); =20 spectre_v1_apply_mitigation(); + retbleed_apply_mitigation(); mds_apply_mitigation(); taa_apply_mitigation(); mmio_apply_mitigation(); @@ -1053,6 +1052,7 @@ enum spectre_v2_mitigation spectre_v2_enabled __ro_af= ter_init =3D SPECTRE_V2_NONE; =20 enum retbleed_mitigation { RETBLEED_MITIGATION_NONE, + RETBLEED_MITIGATION_AUTO, RETBLEED_MITIGATION_UNRET, RETBLEED_MITIGATION_IBPB, RETBLEED_MITIGATION_IBRS, @@ -1060,14 +1060,6 @@ enum retbleed_mitigation { RETBLEED_MITIGATION_STUFF, }; =20 -enum retbleed_mitigation_cmd { - RETBLEED_CMD_OFF, - RETBLEED_CMD_AUTO, - RETBLEED_CMD_UNRET, - RETBLEED_CMD_IBPB, - RETBLEED_CMD_STUFF, -}; - static const char * const retbleed_strings[] =3D { [RETBLEED_MITIGATION_NONE] =3D "Vulnerable", [RETBLEED_MITIGATION_UNRET] =3D "Mitigation: untrained return thunk", @@ -1078,9 +1070,7 @@ static const char * const retbleed_strings[] =3D { }; =20 static enum retbleed_mitigation retbleed_mitigation __ro_after_init =3D - RETBLEED_MITIGATION_NONE; -static enum retbleed_mitigation_cmd retbleed_cmd __ro_after_init =3D - IS_ENABLED(CONFIG_MITIGATION_RETBLEED) ? RETBLEED_CMD_AUTO : RETBLEED_CMD= _OFF; + IS_ENABLED(CONFIG_MITIGATION_RETBLEED) ? RETBLEED_MITIGATION_AUTO : RETBL= EED_MITIGATION_NONE; =20 static int __ro_after_init retbleed_nosmt =3D false; =20 @@ -1097,15 +1087,15 @@ static int __init retbleed_parse_cmdline(char *str) } =20 if (!strcmp(str, "off")) { - retbleed_cmd =3D RETBLEED_CMD_OFF; + retbleed_mitigation =3D RETBLEED_MITIGATION_NONE; } else if (!strcmp(str, "auto")) { - retbleed_cmd =3D RETBLEED_CMD_AUTO; + retbleed_mitigation =3D RETBLEED_MITIGATION_AUTO; } else if (!strcmp(str, "unret")) { - retbleed_cmd =3D RETBLEED_CMD_UNRET; + retbleed_mitigation =3D RETBLEED_MITIGATION_UNRET; } else if (!strcmp(str, "ibpb")) { - retbleed_cmd =3D RETBLEED_CMD_IBPB; + retbleed_mitigation =3D RETBLEED_MITIGATION_IBPB; } else if (!strcmp(str, "stuff")) { - retbleed_cmd =3D RETBLEED_CMD_STUFF; + retbleed_mitigation =3D RETBLEED_MITIGATION_STUFF; } else if (!strcmp(str, "nosmt")) { retbleed_nosmt =3D true; } else if (!strcmp(str, "force")) { @@ -1126,53 +1116,38 @@ early_param("retbleed", retbleed_parse_cmdline); =20 static void __init retbleed_select_mitigation(void) { - bool mitigate_smt =3D false; - - if (!boot_cpu_has_bug(X86_BUG_RETBLEED) || cpu_mitigations_off()) - return; - - switch (retbleed_cmd) { - case RETBLEED_CMD_OFF: + if (!boot_cpu_has_bug(X86_BUG_RETBLEED) || cpu_mitigations_off()) { + retbleed_mitigation =3D RETBLEED_MITIGATION_NONE; return; + } =20 - case RETBLEED_CMD_UNRET: - if (IS_ENABLED(CONFIG_MITIGATION_UNRET_ENTRY)) { - retbleed_mitigation =3D RETBLEED_MITIGATION_UNRET; - } else { + switch (retbleed_mitigation) { + case RETBLEED_MITIGATION_UNRET: + if (!IS_ENABLED(CONFIG_MITIGATION_UNRET_ENTRY)) { + retbleed_mitigation =3D RETBLEED_MITIGATION_AUTO; pr_err("WARNING: kernel not compiled with MITIGATION_UNRET_ENTRY.\n"); - goto do_cmd_auto; } break; - - case RETBLEED_CMD_IBPB: + case RETBLEED_MITIGATION_IBPB: if (!boot_cpu_has(X86_FEATURE_IBPB)) { pr_err("WARNING: CPU does not support IBPB.\n"); - goto do_cmd_auto; - } else if (IS_ENABLED(CONFIG_MITIGATION_IBPB_ENTRY)) { - retbleed_mitigation =3D RETBLEED_MITIGATION_IBPB; - } else { + retbleed_mitigation =3D RETBLEED_MITIGATION_AUTO; + } else if (!IS_ENABLED(CONFIG_MITIGATION_IBPB_ENTRY)) { pr_err("WARNING: kernel not compiled with MITIGATION_IBPB_ENTRY.\n"); - goto do_cmd_auto; + retbleed_mitigation =3D RETBLEED_MITIGATION_AUTO; } break; - - case RETBLEED_CMD_STUFF: - if (IS_ENABLED(CONFIG_MITIGATION_CALL_DEPTH_TRACKING) && - spectre_v2_enabled =3D=3D SPECTRE_V2_RETPOLINE) { - retbleed_mitigation =3D RETBLEED_MITIGATION_STUFF; - - } else { - if (IS_ENABLED(CONFIG_MITIGATION_CALL_DEPTH_TRACKING)) - pr_err("WARNING: retbleed=3Dstuff depends on spectre_v2=3Dretpoline\n"= ); - else - pr_err("WARNING: kernel not compiled with MITIGATION_CALL_DEPTH_TRACKI= NG.\n"); - - goto do_cmd_auto; + case RETBLEED_MITIGATION_STUFF: + if (!IS_ENABLED(CONFIG_MITIGATION_CALL_DEPTH_TRACKING)) { + pr_err("WARNING: kernel not compiled with MITIGATION_CALL_DEPTH_TRACKIN= G.\n"); + retbleed_mitigation =3D RETBLEED_MITIGATION_AUTO; } break; + default: + break; + } =20 -do_cmd_auto: - case RETBLEED_CMD_AUTO: + if (retbleed_mitigation =3D=3D RETBLEED_MITIGATION_AUTO) { if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD || boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_HYGON) { if (IS_ENABLED(CONFIG_MITIGATION_UNRET_ENTRY)) @@ -1181,17 +1156,55 @@ static void __init retbleed_select_mitigation(void) boot_cpu_has(X86_FEATURE_IBPB)) retbleed_mitigation =3D RETBLEED_MITIGATION_IBPB; } + } +} =20 - /* - * The Intel mitigation (IBRS or eIBRS) was already selected in - * spectre_v2_select_mitigation(). 'retbleed_mitigation' will - * be set accordingly below. - */ +static void __init retbleed_update_mitigation(void) +{ + if (!boot_cpu_has_bug(X86_BUG_RETBLEED) || + retbleed_mitigation =3D=3D RETBLEED_MITIGATION_NONE) + return; + /* + * Let IBRS trump all on Intel without affecting the effects of the + * retbleed=3D cmdline option except for call depth based stuffing + */ + if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL) { + switch (spectre_v2_enabled) { + case SPECTRE_V2_IBRS: + retbleed_mitigation =3D RETBLEED_MITIGATION_IBRS; + break; + case SPECTRE_V2_EIBRS: + case SPECTRE_V2_EIBRS_RETPOLINE: + case SPECTRE_V2_EIBRS_LFENCE: + retbleed_mitigation =3D RETBLEED_MITIGATION_EIBRS; + break; + default: + if (retbleed_mitigation !=3D RETBLEED_MITIGATION_STUFF) + pr_err(RETBLEED_INTEL_MSG); + } + } =20 - break; + if (retbleed_mitigation =3D=3D RETBLEED_MITIGATION_STUFF) { + if (spectre_v2_enabled !=3D SPECTRE_V2_RETPOLINE) { + pr_err("WARNING: retbleed=3Dstuff depends on spectre_v2=3Dretpoline\n"); + retbleed_mitigation =3D RETBLEED_MITIGATION_AUTO; + /* Try again */ + retbleed_select_mitigation(); + } } =20 + pr_info("%s\n", retbleed_strings[retbleed_mitigation]); +} + + +static void __init retbleed_apply_mitigation(void) +{ + bool mitigate_smt =3D false; + switch (retbleed_mitigation) { + case RETBLEED_MITIGATION_NONE: + return; + case RETBLEED_MITIGATION_UNRET: setup_force_cpu_cap(X86_FEATURE_RETHUNK); setup_force_cpu_cap(X86_FEATURE_UNRET); @@ -1243,27 +1256,6 @@ static void __init retbleed_select_mitigation(void) (retbleed_nosmt || cpu_mitigations_auto_nosmt())) cpu_smt_disable(false); =20 - /* - * Let IBRS trump all on Intel without affecting the effects of the - * retbleed=3D cmdline option except for call depth based stuffing - */ - if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL) { - switch (spectre_v2_enabled) { - case SPECTRE_V2_IBRS: - retbleed_mitigation =3D RETBLEED_MITIGATION_IBRS; - break; - case SPECTRE_V2_EIBRS: - case SPECTRE_V2_EIBRS_RETPOLINE: - case SPECTRE_V2_EIBRS_LFENCE: - retbleed_mitigation =3D RETBLEED_MITIGATION_EIBRS; - break; - default: - if (retbleed_mitigation !=3D RETBLEED_MITIGATION_STUFF) - pr_err(RETBLEED_INTEL_MSG); - } - } - - pr_info("%s\n", retbleed_strings[retbleed_mitigation]); } =20 #undef pr_fmt @@ -1816,16 +1808,6 @@ static void __init spectre_v2_select_mitigation(void) break; } =20 - if (IS_ENABLED(CONFIG_MITIGATION_IBRS_ENTRY) && - boot_cpu_has_bug(X86_BUG_RETBLEED) && - retbleed_cmd !=3D RETBLEED_CMD_OFF && - retbleed_cmd !=3D RETBLEED_CMD_STUFF && - boot_cpu_has(X86_FEATURE_IBRS) && - boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL) { - mode =3D SPECTRE_V2_IBRS; - break; - } - mode =3D spectre_v2_select_retpoline(); break; =20 @@ -1981,7 +1963,7 @@ static void __init spectre_v2_select_mitigation(void) (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD || boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_HYGON)) { =20 - if (retbleed_cmd !=3D RETBLEED_CMD_IBPB) { + if (retbleed_mitigation !=3D RETBLEED_MITIGATION_IBPB) { setup_force_cpu_cap(X86_FEATURE_USE_IBPB_FW); pr_info("Enabling Speculation Barrier for firmware calls\n"); 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Peter Anvin" CC: Subject: [PATCH v2 13/35] x86/bugs: Restructure spectre_v2_user mitigation Date: Tue, 5 Nov 2024 15:54:33 -0600 Message-ID: <20241105215455.359471-14-david.kaplan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105215455.359471-1-david.kaplan@amd.com> References: <20241105215455.359471-1-david.kaplan@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B374:EE_|PH0PR12MB7472:EE_ X-MS-Office365-Filtering-Correlation-Id: ab17a87a-a0cb-4f24-a416-08dcfde49132 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?fdjm8lStjcUurQUrAuqqHZdjUJl2WDitc7plZfMg6RjP7k1xA58f3FMwNpBd?= =?us-ascii?Q?Xp7Yz0/nZG4ee1Ae0ShtnI34acCnVRRvqHZcFfCS6G0pYf8t+m+8synvvj7t?= =?us-ascii?Q?7bylYmvrViuZEFAohHrvhKgawMjSUEXtTtD/UtCemjTv/DHTH/rn87EdLwGJ?= =?us-ascii?Q?b4ZSe6icUnCgjBEqfeFXleIh+k0wLUIX458X28OqobYBwPfsWzQ/lwK/rV1j?= =?us-ascii?Q?Oe38oeAYDlU8kL+Jbpl7v3lDCPcBlBhNdqFYTt+ROEr8CrxUMUVqZqLGJ8jk?= =?us-ascii?Q?xsB98cijAieJ/2H4CsxRDyvklDtWCNTe9A4cgSiUnf5SfC1MVWHZpC82G46C?= =?us-ascii?Q?8SwQA/85vwOqsan/EoXdvpWnn6UlU3uHWmwKDHloWjl4S+A1qamBNOMK6vur?= =?us-ascii?Q?cAOLuiDALLpEk4wrxG0N+/Ojv13nLlb9PeKlV3gxhlB/pOMLu7exVv5LdnRB?= =?us-ascii?Q?mS0/FmPsmK17JV62abyOP7ge0eMqQ+7HoZdPkCYct0UCnFLkUD4isasrL1JR?= =?us-ascii?Q?t/n0exp0aYuTOH3C1uZG0xpVFrOFGA0XY7ZFkIP9GCm5KUTWB9ZpwBF1u1cR?= =?us-ascii?Q?+w1j3JEPxlf0AJmTl94zYolTS1h6CnbLrIalJ5dm5dKUzeZNXcLNrIsVsNQQ?= =?us-ascii?Q?ST22W3choDxNw+iKypOzMhdD9g0wPyCRzRsJlKGfls/5wkBiSCCW0do67ll7?= =?us-ascii?Q?SYrkwC6zZ42WHH6EDcgGxY9u9iu0bOgq7au/XTBLZUIjQy7P2KehtHjRxcPU?= =?us-ascii?Q?OCGhQeNlDLQ6caDgC4OxzF+T27os1vtzcmrAeY19LQ14mlJVuK4QzdPFhLNB?= =?us-ascii?Q?GfYea+Q2Up+uKMte7W37I7R4EJ/TRmptpvhX0l9lxRmVkaLutVQEoPQuK8P1?= =?us-ascii?Q?3e2MRlzP9WLAnFVoM91YcefugyFxqm8Zc6kZQg36Qc7toVwrQvsI1jIfuCHH?= =?us-ascii?Q?sxSeYyIN44gvF3m9pO8Bcd12IFw5yD1AVcDSECENf0BWnl3n1YuiFp4EywcJ?= =?us-ascii?Q?WTk4kkpIT8rtDIr4aqmdhddDetbWPQnsCvgMpzwnK7g6wfaFZ79w9ctzCV+k?= =?us-ascii?Q?4iW9X1V+NbHl3MhhgskDUTrz+NT9Zj8hP02kkJLjSsfiGEjkEYeyc/46MjPx?= =?us-ascii?Q?ibpHugB4ow1c2YTc7Tm86nlo/3ZctULKRXoZJ9s9BwOC3Bnj29/SRcoaynl0?= =?us-ascii?Q?l8yUCu9At214ga9U9zlugZDL7KdBRa/vhy9n67+KHYl/6S9EiSj7qrkOjSup?= =?us-ascii?Q?VOPqa+0j1bIn3nqZDNTOUx+rW99uvN7v3PHqO98SK4piUXqAbky1hGWJSooN?= =?us-ascii?Q?Tkq+b3GhoGbarixGBbTtx1Lu88R/4Rkej8L7oGXaV8kwEE2je2n+fRFQf+y0?= =?us-ascii?Q?fGH0/9pNtKyCOEoKVkT8ORuZOp83ZL04NIWIWdj5MIm2nOq0Jg=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 21:55:30.9528 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ab17a87a-a0cb-4f24-a416-08dcfde49132 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B374.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7472 Content-Type: text/plain; charset="utf-8" Restructure spectre_v2_user to use select/update/apply functions to create consistent vulnerability handling. The ibpb/stibp choices are first decided based on the spectre_v2_user command line but can be modified by the spectre_v2 command line option as well. Signed-off-by: David Kaplan --- arch/x86/kernel/cpu/bugs.c | 147 ++++++++++++++++++++----------------- 1 file changed, 81 insertions(+), 66 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 36657bd7143b..9a41fd121b71 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -60,6 +60,8 @@ static void __init retbleed_select_mitigation(void); static void __init retbleed_update_mitigation(void); static void __init retbleed_apply_mitigation(void); static void __init spectre_v2_user_select_mitigation(void); +static void __init spectre_v2_user_update_mitigation(void); +static void __init spectre_v2_user_apply_mitigation(void); static void __init ssb_select_mitigation(void); static void __init l1tf_select_mitigation(void); static void __init mds_select_mitigation(void); @@ -183,11 +185,6 @@ void __init cpu_select_mitigations(void) spectre_v1_select_mitigation(); spectre_v2_select_mitigation(); retbleed_select_mitigation(); - /* - * spectre_v2_user_select_mitigation() relies on the state set by - * retbleed_select_mitigation(); specifically the STIBP selection is - * forced for UNRET or IBPB. - */ spectre_v2_user_select_mitigation(); ssb_select_mitigation(); l1tf_select_mitigation(); @@ -210,6 +207,7 @@ void __init cpu_select_mitigations(void) * choices. */ retbleed_update_mitigation(); + spectre_v2_user_update_mitigation(); mds_update_mitigation(); taa_update_mitigation(); mmio_update_mitigation(); @@ -217,6 +215,7 @@ void __init cpu_select_mitigations(void) =20 spectre_v1_apply_mitigation(); retbleed_apply_mitigation(); + spectre_v2_user_apply_mitigation(); mds_apply_mitigation(); taa_apply_mitigation(); mmio_apply_mitigation(); @@ -1335,6 +1334,8 @@ enum spectre_v2_mitigation_cmd { SPECTRE_V2_CMD_IBRS, }; =20 +enum spectre_v2_mitigation_cmd spectre_v2_cmd __ro_after_init =3D SPECTRE_= V2_CMD_AUTO; + enum spectre_v2_user_cmd { SPECTRE_V2_USER_CMD_NONE, SPECTRE_V2_USER_CMD_AUTO, @@ -1373,22 +1374,14 @@ static void __init spec_v2_user_print_cond(const ch= ar *reason, bool secure) pr_info("spectre_v2_user=3D%s forced on command line.\n", reason); } =20 -static __ro_after_init enum spectre_v2_mitigation_cmd spectre_v2_cmd; - static enum spectre_v2_user_cmd __init spectre_v2_parse_user_cmdline(void) { char arg[20]; int ret, i; =20 - switch (spectre_v2_cmd) { - case SPECTRE_V2_CMD_NONE: + if (cpu_mitigations_off()) return SPECTRE_V2_USER_CMD_NONE; - case SPECTRE_V2_CMD_FORCE: - return SPECTRE_V2_USER_CMD_FORCE; - default: - break; - } =20 ret =3D cmdline_find_option(boot_command_line, "spectre_v2_user", arg, sizeof(arg)); @@ -1412,65 +1405,70 @@ static inline bool spectre_v2_in_ibrs_mode(enum spe= ctre_v2_mitigation mode) return spectre_v2_in_eibrs_mode(mode) || mode =3D=3D SPECTRE_V2_IBRS; } =20 + static void __init spectre_v2_user_select_mitigation(void) { - enum spectre_v2_user_mitigation mode =3D SPECTRE_V2_USER_NONE; - bool smt_possible =3D IS_ENABLED(CONFIG_SMP); enum spectre_v2_user_cmd cmd; =20 if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP)) return; =20 - if (cpu_smt_control =3D=3D CPU_SMT_FORCE_DISABLED || - cpu_smt_control =3D=3D CPU_SMT_NOT_SUPPORTED) - smt_possible =3D false; - cmd =3D spectre_v2_parse_user_cmdline(); switch (cmd) { case SPECTRE_V2_USER_CMD_NONE: - goto set_mode; + return; case SPECTRE_V2_USER_CMD_FORCE: - mode =3D SPECTRE_V2_USER_STRICT; + spectre_v2_user_ibpb =3D SPECTRE_V2_USER_STRICT; + spectre_v2_user_stibp =3D SPECTRE_V2_USER_STRICT; break; case SPECTRE_V2_USER_CMD_AUTO: case SPECTRE_V2_USER_CMD_PRCTL: + spectre_v2_user_ibpb =3D SPECTRE_V2_USER_PRCTL; + spectre_v2_user_stibp =3D SPECTRE_V2_USER_PRCTL; + break; case SPECTRE_V2_USER_CMD_PRCTL_IBPB: - mode =3D SPECTRE_V2_USER_PRCTL; + spectre_v2_user_ibpb =3D SPECTRE_V2_USER_STRICT; + spectre_v2_user_stibp =3D SPECTRE_V2_USER_PRCTL; break; case SPECTRE_V2_USER_CMD_SECCOMP: - case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: if (IS_ENABLED(CONFIG_SECCOMP)) - mode =3D SPECTRE_V2_USER_SECCOMP; + spectre_v2_user_ibpb =3D SPECTRE_V2_USER_SECCOMP; else - mode =3D SPECTRE_V2_USER_PRCTL; + spectre_v2_user_ibpb =3D SPECTRE_V2_USER_PRCTL; + spectre_v2_user_stibp =3D spectre_v2_user_ibpb; + break; + case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: + spectre_v2_user_ibpb =3D SPECTRE_V2_USER_STRICT; + spectre_v2_user_stibp =3D SPECTRE_V2_USER_PRCTL; break; } =20 - /* Initialize Indirect Branch Prediction Barrier */ - if (boot_cpu_has(X86_FEATURE_IBPB)) { - setup_force_cpu_cap(X86_FEATURE_USE_IBPB); + /* + * At this point, an STIBP mode other than "off" has been set. + * If STIBP support is not being forced, check if STIBP always-on + * is preferred. + */ + if (spectre_v2_user_stibp !=3D SPECTRE_V2_USER_STRICT && + boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON)) + spectre_v2_user_stibp =3D SPECTRE_V2_USER_STRICT_PREFERRED; +} =20 - spectre_v2_user_ibpb =3D mode; - switch (cmd) { - case SPECTRE_V2_USER_CMD_NONE: - break; - case SPECTRE_V2_USER_CMD_FORCE: - case SPECTRE_V2_USER_CMD_PRCTL_IBPB: - case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: - static_branch_enable(&switch_mm_always_ibpb); - spectre_v2_user_ibpb =3D SPECTRE_V2_USER_STRICT; - break; - case SPECTRE_V2_USER_CMD_PRCTL: - case SPECTRE_V2_USER_CMD_AUTO: - case SPECTRE_V2_USER_CMD_SECCOMP: - static_branch_enable(&switch_mm_cond_ibpb); - break; - } +static void __init spectre_v2_user_update_mitigation(void) +{ + bool smt_possible =3D IS_ENABLED(CONFIG_SMP); =20 - pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n", - static_key_enabled(&switch_mm_always_ibpb) ? - "always-on" : "conditional"); + if (cpu_smt_control =3D=3D CPU_SMT_FORCE_DISABLED || + cpu_smt_control =3D=3D CPU_SMT_NOT_SUPPORTED) + smt_possible =3D false; + + /* The spectre_v2 cmd line can override spectre_v2_user options */ + if (spectre_v2_cmd =3D=3D SPECTRE_V2_CMD_NONE) { + spectre_v2_user_ibpb =3D SPECTRE_V2_USER_NONE; + spectre_v2_user_stibp =3D SPECTRE_V2_USER_NONE; + } else if (spectre_v2_cmd =3D=3D SPECTRE_V2_CMD_FORCE) { + spectre_v2_user_ibpb =3D SPECTRE_V2_USER_STRICT; + spectre_v2_user_stibp =3D SPECTRE_V2_USER_STRICT; } =20 /* @@ -1488,30 +1486,47 @@ spectre_v2_user_select_mitigation(void) if (!boot_cpu_has(X86_FEATURE_STIBP) || !smt_possible || (spectre_v2_in_eibrs_mode(spectre_v2_enabled) && - !boot_cpu_has(X86_FEATURE_AUTOIBRS))) + !boot_cpu_has(X86_FEATURE_AUTOIBRS))) { + spectre_v2_user_stibp =3D SPECTRE_V2_USER_NONE; return; + } =20 - /* - * At this point, an STIBP mode other than "off" has been set. - * If STIBP support is not being forced, check if STIBP always-on - * is preferred. - */ - if (mode !=3D SPECTRE_V2_USER_STRICT && - boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON)) - mode =3D SPECTRE_V2_USER_STRICT_PREFERRED; - - if (retbleed_mitigation =3D=3D RETBLEED_MITIGATION_UNRET || - retbleed_mitigation =3D=3D RETBLEED_MITIGATION_IBPB) { - if (mode !=3D SPECTRE_V2_USER_STRICT && - mode !=3D SPECTRE_V2_USER_STRICT_PREFERRED) + if (spectre_v2_user_stibp !=3D SPECTRE_V2_USER_NONE && + (retbleed_mitigation =3D=3D RETBLEED_MITIGATION_UNRET || + retbleed_mitigation =3D=3D RETBLEED_MITIGATION_IBPB)) { + if (spectre_v2_user_stibp !=3D SPECTRE_V2_USER_STRICT && + spectre_v2_user_stibp !=3D SPECTRE_V2_USER_STRICT_PREFERRED) pr_info("Selecting STIBP always-on mode to complement retbleed mitigati= on\n"); - mode =3D SPECTRE_V2_USER_STRICT_PREFERRED; + spectre_v2_user_stibp =3D SPECTRE_V2_USER_STRICT_PREFERRED; } + pr_info("%s\n", spectre_v2_user_strings[spectre_v2_user_stibp]); +} =20 - spectre_v2_user_stibp =3D mode; +static void __init spectre_v2_user_apply_mitigation(void) +{ + /* Initialize Indirect Branch Prediction Barrier */ + if (boot_cpu_has(X86_FEATURE_IBPB) && + spectre_v2_user_ibpb !=3D SPECTRE_V2_USER_NONE) { + setup_force_cpu_cap(X86_FEATURE_USE_IBPB); + + switch (spectre_v2_user_ibpb) { + case SPECTRE_V2_USER_NONE: + break; + case SPECTRE_V2_USER_STRICT: + static_branch_enable(&switch_mm_always_ibpb); + break; + case SPECTRE_V2_USER_PRCTL: + case SPECTRE_V2_USER_SECCOMP: + static_branch_enable(&switch_mm_cond_ibpb); + break; + default: + break; + } =20 -set_mode: - pr_info("%s\n", spectre_v2_user_strings[mode]); + pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n", + static_key_enabled(&switch_mm_always_ibpb) ? + "always-on" : "conditional"); + } } =20 static const char * const spectre_v2_strings[] =3D { --=20 2.34.1 From nobody Sun Nov 24 11:56:51 2024 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2058.outbound.protection.outlook.com [40.107.237.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3793321642A for ; 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Tue, 5 Nov 2024 15:55:28 -0600 From: David Kaplan To: Thomas Gleixner , Borislav Petkov , Peter Zijlstra , Josh Poimboeuf , Pawan Gupta , Ingo Molnar , Dave Hansen , , "H . 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Define new AUTO mitigation for bhi. Signed-off-by: David Kaplan --- arch/x86/kernel/cpu/bugs.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 9a41fd121b71..62ba49062182 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -82,6 +82,8 @@ static void __init l1d_flush_select_mitigation(void); static void __init srso_select_mitigation(void); static void __init gds_select_mitigation(void); static void __init gds_apply_mitigation(void); +static void __init bhi_select_mitigation(void); +static void __init bhi_apply_mitigation(void); =20 /* The base value of the SPEC_CTRL MSR without task-specific bits set */ u64 x86_spec_ctrl_base; @@ -201,6 +203,7 @@ void __init cpu_select_mitigations(void) */ srso_select_mitigation(); gds_select_mitigation(); + bhi_select_mitigation(); =20 /* * After mitigations are selected, some may need to update their @@ -222,6 +225,7 @@ void __init cpu_select_mitigations(void) rfds_apply_mitigation(); srbds_apply_mitigation(); gds_apply_mitigation(); + bhi_apply_mitigation(); } =20 /* @@ -1743,12 +1747,13 @@ static bool __init spec_ctrl_bhi_dis(void) =20 enum bhi_mitigations { BHI_MITIGATION_OFF, + BHI_MITIGATION_AUTO, BHI_MITIGATION_ON, BHI_MITIGATION_VMEXIT_ONLY, }; =20 static enum bhi_mitigations bhi_mitigation __ro_after_init =3D - IS_ENABLED(CONFIG_MITIGATION_SPECTRE_BHI) ? BHI_MITIGATION_ON : BHI_MITIG= ATION_OFF; + IS_ENABLED(CONFIG_MITIGATION_SPECTRE_BHI) ? BHI_MITIGATION_AUTO : BHI_MIT= IGATION_OFF; =20 static int __init spectre_bhi_parse_cmdline(char *str) { @@ -1769,6 +1774,18 @@ static int __init spectre_bhi_parse_cmdline(char *st= r) early_param("spectre_bhi", spectre_bhi_parse_cmdline); =20 static void __init bhi_select_mitigation(void) +{ + if (!boot_cpu_has(X86_BUG_BHI) || cpu_mitigations_off()) + bhi_mitigation =3D BHI_MITIGATION_OFF; + + if (bhi_mitigation =3D=3D BHI_MITIGATION_OFF) + return; + + if (bhi_mitigation =3D=3D BHI_MITIGATION_AUTO) + bhi_mitigation =3D BHI_MITIGATION_ON; +} + +static void __init bhi_apply_mitigation(void) { if (bhi_mitigation =3D=3D BHI_MITIGATION_OFF) return; @@ -1900,9 +1917,6 @@ static void __init spectre_v2_select_mitigation(void) mode =3D=3D SPECTRE_V2_RETPOLINE) spec_ctrl_disable_kernel_rrsba(); =20 - if (boot_cpu_has(X86_BUG_BHI)) - bhi_select_mitigation(); - spectre_v2_enabled =3D mode; pr_info("%s\n", spectre_v2_strings[mode]); =20 --=20 2.34.1 From nobody Sun Nov 24 11:56:51 2024 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2070.outbound.protection.outlook.com [40.107.220.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 161222170A7 for ; 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Tue, 5 Nov 2024 15:55:28 -0600 From: David Kaplan To: Thomas Gleixner , Borislav Petkov , Peter Zijlstra , Josh Poimboeuf , Pawan Gupta , Ingo Molnar , Dave Hansen , , "H . Peter Anvin" CC: Subject: [PATCH v2 15/35] x86/bugs: Restructure spectre_v2 mitigation Date: Tue, 5 Nov 2024 15:54:35 -0600 Message-ID: <20241105215455.359471-16-david.kaplan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105215455.359471-1-david.kaplan@amd.com> References: <20241105215455.359471-1-david.kaplan@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B374:EE_|PH7PR12MB7233:EE_ X-MS-Office365-Filtering-Correlation-Id: 082b9fb6-29a4-4072-afd6-08dcfde491e0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|7416014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?qj835Pq6TpQY8pgRDtcYK2jj0o8d2ix54TqqS/b/Pztqxd9KUyNR0g7LBdTS?= =?us-ascii?Q?7YoE3fcLUqS+AcUHdfUpIW+QtsWkO6guJo6vQLUyB3mU43FZuDAV017dZbe9?= =?us-ascii?Q?fpp+wpymkdPyAEJ9CEXNYvcdNjJ68inuSKROKNLhtOvmnxEQsjG/Ddbh3ZKP?= =?us-ascii?Q?Ijsu7JQHZiGUZDIspytIA/7kXtz1Cdd4CXSAQpZJYBkxwSqrhE5zoN0f+HDy?= =?us-ascii?Q?rEJ6OeX0J08Fc2eV3UQh3Q5U9JV1y1EShHDBm34D9AgdpXpB0FqUnsck15fy?= =?us-ascii?Q?6Yml5u1ry+5DkbVX3MjvqiSkwlabdMGoJjIqgaxHOs2Z8O0ELFbVnNn2ktTW?= =?us-ascii?Q?0uMR+2jcd9pnHI4G0teKYdz419ddir0PE3QyxwNFeVJXAmTz1nb5G604ihPJ?= =?us-ascii?Q?bwSTuEHHvIhGvlG60WpOANHT4vRpwoBOwiOsFyoqca8YRFCXSZDC4x21Ywkt?= =?us-ascii?Q?CGlorfyKUIjELakE8LyufL7en5dEN9Rl70KsbMK0mQsnO1T56DyaIg9TW7Ir?= =?us-ascii?Q?G9BKXC1j1rdSkQew/2114ylC56G3CwvnI9vJw04KMxxMgzmH8cXsVPHKMubM?= =?us-ascii?Q?HvI0FeZt1v7LErlwP/OVa4mrKZ3MQKTpLSGeiKLEV+w2bciKS2trEKOVJnGW?= =?us-ascii?Q?NHFga+X1isXrohw7TQoTv00cdIqAoL51640ef7mjFYuEcwtJ2tIp9meSuOuY?= =?us-ascii?Q?JOU9KveLBliDIUqXnkhaLAr2ioVFZGkyq9xfCQxDOOsAPA2E66A26JD2mrI+?= =?us-ascii?Q?btrlo7FOFYenbqrVfjHTF7KVfslX8/b+YJUHKyu36M2y4ZfLnCYhFwgravvB?= =?us-ascii?Q?bR8sCo10sIPvLXOWI5iQQ3eXqKc309ZTeCdM6elK5yg0kqexg5flTnRsLJpa?= =?us-ascii?Q?4LR/+0WEcakBYWQ+NIvAPtQRLOEMxsKTFQobmanfdQW+FNY5U701laYu1oBX?= =?us-ascii?Q?4Is/FxQwfxqJrVpPZzUGRi5Y1iqhPMRIDdWVxaur2nzJUS0W9pSFvqZqa+vF?= =?us-ascii?Q?z73VfE9btdWKTQLtWFgxxrhJhPMYVBVdYIIOFtvEqcjvveHElumrF+f5wrw8?= =?us-ascii?Q?nTDoSMfKh3YS7rlPJRAqAvMCj37sQpAX7wBff2jsKMSHWv9SORbiVo6MXYIT?= =?us-ascii?Q?LyU4LICZjHbY5cagsWyJig26mEfFYyU4YnzaS+iCgODDZCF25uofUR79b+Sm?= =?us-ascii?Q?zbshU01uhHxUCMWFWzjE0UD9b+m0uEmr6qC9O8yZbpOhmMgMuTXw84B7E0aw?= =?us-ascii?Q?wUgg9757M/YClruJDrY8tX5ettTk04P70w78ySkaRJp2+lMWNg6nB3REJ6V7?= =?us-ascii?Q?mzxw6jT86qjd0lK6ti1IWqUv9RwhwSfaveP5mdbOrQsXQp6u3eVJoDJFepv6?= =?us-ascii?Q?548Cl6eNYqDq4kbkUvoBulvShFbwhHef6mj0fSNO0aHIRKLmsQ=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(7416014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 21:55:32.0778 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 082b9fb6-29a4-4072-afd6-08dcfde491e0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B374.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7233 Content-Type: text/plain; charset="utf-8" Restructure spectre_v2 to use select/update/apply functions to create consistent vulnerability handling. The spectre_v2 mitigation may be updated based on the selected retbleed mitigation. Signed-off-by: David Kaplan --- arch/x86/kernel/cpu/bugs.c | 62 ++++++++++++++++++++++++++------------ 1 file changed, 42 insertions(+), 20 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 62ba49062182..ec5cc66513bd 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -56,6 +56,8 @@ static void __init spectre_v1_select_mitigation(void); static void __init spectre_v1_apply_mitigation(void); static void __init spectre_v2_select_mitigation(void); +static void __init spectre_v2_update_mitigation(void); +static void __init spectre_v2_apply_mitigation(void); static void __init retbleed_select_mitigation(void); static void __init retbleed_update_mitigation(void); static void __init retbleed_apply_mitigation(void); @@ -209,6 +211,7 @@ void __init cpu_select_mitigations(void) * After mitigations are selected, some may need to update their * choices. */ + spectre_v2_update_mitigation(); retbleed_update_mitigation(); spectre_v2_user_update_mitigation(); mds_update_mitigation(); @@ -217,6 +220,7 @@ void __init cpu_select_mitigations(void) rfds_update_mitigation(); =20 spectre_v1_apply_mitigation(); + spectre_v2_apply_mitigation(); retbleed_apply_mitigation(); spectre_v2_user_apply_mitigation(); mds_apply_mitigation(); @@ -1818,18 +1822,18 @@ static void __init bhi_apply_mitigation(void) =20 static void __init spectre_v2_select_mitigation(void) { - enum spectre_v2_mitigation_cmd cmd =3D spectre_v2_parse_cmdline(); enum spectre_v2_mitigation mode =3D SPECTRE_V2_NONE; + spectre_v2_cmd =3D spectre_v2_parse_cmdline(); =20 /* * If the CPU is not affected and the command line mode is NONE or AUTO * then nothing to do. */ if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && - (cmd =3D=3D SPECTRE_V2_CMD_NONE || cmd =3D=3D SPECTRE_V2_CMD_AUTO)) + (spectre_v2_cmd =3D=3D SPECTRE_V2_CMD_NONE || spectre_v2_cmd =3D=3D S= PECTRE_V2_CMD_AUTO)) return; =20 - switch (cmd) { + switch (spectre_v2_cmd) { case SPECTRE_V2_CMD_NONE: return; =20 @@ -1873,10 +1877,29 @@ static void __init spectre_v2_select_mitigation(voi= d) break; } =20 - if (mode =3D=3D SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled()) + spectre_v2_enabled =3D mode; +} + +static void __init spectre_v2_update_mitigation(void) +{ + if (spectre_v2_cmd =3D=3D SPECTRE_V2_CMD_AUTO) { + if (IS_ENABLED(CONFIG_MITIGATION_IBRS_ENTRY) && + boot_cpu_has_bug(X86_BUG_RETBLEED) && + retbleed_mitigation !=3D RETBLEED_MITIGATION_NONE && + retbleed_mitigation !=3D RETBLEED_MITIGATION_STUFF && + boot_cpu_has(X86_FEATURE_IBRS) && + boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL) { + spectre_v2_enabled =3D SPECTRE_V2_IBRS; + } + } +} + +static void __init spectre_v2_apply_mitigation(void) +{ + if (spectre_v2_enabled =3D=3D SPECTRE_V2_EIBRS && unprivileged_ebpf_enabl= ed()) pr_err(SPECTRE_V2_EIBRS_EBPF_MSG); =20 - if (spectre_v2_in_ibrs_mode(mode)) { + if (spectre_v2_in_ibrs_mode(spectre_v2_enabled)) { if (boot_cpu_has(X86_FEATURE_AUTOIBRS)) { msr_set_bit(MSR_EFER, _EFER_AUTOIBRS); } else { @@ -1885,8 +1908,10 @@ static void __init spectre_v2_select_mitigation(void) } } =20 - switch (mode) { + switch (spectre_v2_enabled) { case SPECTRE_V2_NONE: + return; + case SPECTRE_V2_EIBRS: break; =20 @@ -1912,13 +1937,12 @@ static void __init spectre_v2_select_mitigation(voi= d) * JMPs gets protection against BHI and Intramode-BTI, but RET * prediction from a non-RSB predictor is still a risk. */ - if (mode =3D=3D SPECTRE_V2_EIBRS_LFENCE || - mode =3D=3D SPECTRE_V2_EIBRS_RETPOLINE || - mode =3D=3D SPECTRE_V2_RETPOLINE) + if (spectre_v2_enabled =3D=3D SPECTRE_V2_EIBRS_LFENCE || + spectre_v2_enabled =3D=3D SPECTRE_V2_EIBRS_RETPOLINE || + spectre_v2_enabled =3D=3D SPECTRE_V2_RETPOLINE) spec_ctrl_disable_kernel_rrsba(); =20 - spectre_v2_enabled =3D mode; - pr_info("%s\n", spectre_v2_strings[mode]); + pr_info("%s\n", spectre_v2_strings[spectre_v2_enabled]); =20 /* * If Spectre v2 protection has been enabled, fill the RSB during a @@ -1973,7 +1997,7 @@ static void __init spectre_v2_select_mitigation(void) * the host nor the guest have to clear or fill RSB entries to * avoid poisoning, skip RSB filling at VMEXIT in that case. */ - spectre_v2_determine_rsb_fill_type_at_vmexit(mode); + spectre_v2_determine_rsb_fill_type_at_vmexit(spectre_v2_enabled); } =20 /* @@ -1982,10 +2006,10 @@ static void __init spectre_v2_select_mitigation(voi= d) * firmware calls only when IBRS / Enhanced / Automatic IBRS aren't * otherwise enabled. * - * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because - * the user might select retpoline on the kernel command line and if - * the CPU supports Enhanced IBRS, kernel might un-intentionally not - * enable IBRS around firmware calls. + * Use "spectre_v2_enabled" to check Enhanced IBRS instead of + * boot_cpu_has(), because the user might select retpoline on the kernel + * command line and if the CPU supports Enhanced IBRS, kernel might + * un-intentionally not enable IBRS around firmware calls. */ if (boot_cpu_has_bug(X86_BUG_RETBLEED) && boot_cpu_has(X86_FEATURE_IBPB) && @@ -1997,13 +2021,11 @@ static void __init spectre_v2_select_mitigation(voi= d) pr_info("Enabling Speculation Barrier for firmware calls\n"); } =20 - } else if (boot_cpu_has(X86_FEATURE_IBRS) && !spectre_v2_in_ibrs_mode(mod= e)) { + } else if (boot_cpu_has(X86_FEATURE_IBRS) && + !spectre_v2_in_ibrs_mode(spectre_v2_enabled)) { setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); 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Remove __ssb_select_mitigation() and split the functionality between the select/apply functions. Signed-off-by: David Kaplan --- arch/x86/kernel/cpu/bugs.c | 34 ++++++++++++++++------------------ 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index ec5cc66513bd..a3bbb0831845 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -65,6 +65,7 @@ static void __init spectre_v2_user_select_mitigation(void= ); static void __init spectre_v2_user_update_mitigation(void); static void __init spectre_v2_user_apply_mitigation(void); static void __init ssb_select_mitigation(void); +static void __init ssb_apply_mitigation(void); static void __init l1tf_select_mitigation(void); static void __init mds_select_mitigation(void); static void __init mds_update_mitigation(void); @@ -223,6 +224,7 @@ void __init cpu_select_mitigations(void) spectre_v2_apply_mitigation(); retbleed_apply_mitigation(); spectre_v2_user_apply_mitigation(); + ssb_apply_mitigation(); mds_apply_mitigation(); taa_apply_mitigation(); mmio_apply_mitigation(); @@ -2214,19 +2216,18 @@ static enum ssb_mitigation_cmd __init ssb_parse_cmd= line(void) return cmd; } =20 -static enum ssb_mitigation __init __ssb_select_mitigation(void) +static void ssb_select_mitigation(void) { - enum ssb_mitigation mode =3D SPEC_STORE_BYPASS_NONE; enum ssb_mitigation_cmd cmd; =20 if (!boot_cpu_has(X86_FEATURE_SSBD)) - return mode; + return; =20 cmd =3D ssb_parse_cmdline(); if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && (cmd =3D=3D SPEC_STORE_BYPASS_CMD_NONE || cmd =3D=3D SPEC_STORE_BYPASS_CMD_AUTO)) - return mode; + return; =20 switch (cmd) { case SPEC_STORE_BYPASS_CMD_SECCOMP: @@ -2235,28 +2236,34 @@ static enum ssb_mitigation __init __ssb_select_miti= gation(void) * enabled. */ if (IS_ENABLED(CONFIG_SECCOMP)) - mode =3D SPEC_STORE_BYPASS_SECCOMP; + ssb_mode =3D SPEC_STORE_BYPASS_SECCOMP; else - mode =3D SPEC_STORE_BYPASS_PRCTL; + ssb_mode =3D SPEC_STORE_BYPASS_PRCTL; break; case SPEC_STORE_BYPASS_CMD_ON: - mode =3D SPEC_STORE_BYPASS_DISABLE; + ssb_mode =3D SPEC_STORE_BYPASS_DISABLE; break; case SPEC_STORE_BYPASS_CMD_AUTO: case SPEC_STORE_BYPASS_CMD_PRCTL: - mode =3D SPEC_STORE_BYPASS_PRCTL; + ssb_mode =3D SPEC_STORE_BYPASS_PRCTL; break; case SPEC_STORE_BYPASS_CMD_NONE: break; } =20 + if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) + pr_info("%s\n", ssb_strings[ssb_mode]); +} + +static void __init ssb_apply_mitigation(void) +{ /* * We have three CPU feature flags that are in play here: * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation */ - if (mode =3D=3D SPEC_STORE_BYPASS_DISABLE) { + if (ssb_mode =3D=3D SPEC_STORE_BYPASS_DISABLE) { setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); /* * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may @@ -2271,15 +2278,6 @@ static enum ssb_mitigation __init __ssb_select_mitig= ation(void) } } =20 - return mode; -} - -static void ssb_select_mitigation(void) -{ - ssb_mode =3D __ssb_select_mitigation(); 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Define new AUTO mitigation for l1tf. Signed-off-by: David Kaplan --- arch/x86/include/asm/processor.h | 1 + arch/x86/kernel/cpu/bugs.c | 27 +++++++++++++++++++++------ arch/x86/kvm/vmx/vmx.c | 2 ++ 3 files changed, 24 insertions(+), 6 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/proces= sor.h index ea4b87b44455..49da4636ce5a 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -743,6 +743,7 @@ void store_cpu_caps(struct cpuinfo_x86 *info); =20 enum l1tf_mitigations { L1TF_MITIGATION_OFF, + L1TF_MITIGATION_AUTO, L1TF_MITIGATION_FLUSH_NOWARN, L1TF_MITIGATION_FLUSH, L1TF_MITIGATION_FLUSH_NOSMT, diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index a3bbb0831845..98ef1cbc9e2a 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -67,6 +67,7 @@ static void __init spectre_v2_user_apply_mitigation(void); static void __init ssb_select_mitigation(void); static void __init ssb_apply_mitigation(void); static void __init l1tf_select_mitigation(void); +static void __init l1tf_apply_mitigation(void); static void __init mds_select_mitigation(void); static void __init mds_update_mitigation(void); static void __init mds_apply_mitigation(void); @@ -225,6 +226,7 @@ void __init cpu_select_mitigations(void) retbleed_apply_mitigation(); spectre_v2_user_apply_mitigation(); ssb_apply_mitigation(); + l1tf_apply_mitigation(); mds_apply_mitigation(); taa_apply_mitigation(); mmio_apply_mitigation(); @@ -2533,7 +2535,7 @@ EXPORT_SYMBOL_GPL(itlb_multihit_kvm_mitigation); =20 /* Default mitigation for L1TF-affected CPUs */ enum l1tf_mitigations l1tf_mitigation __ro_after_init =3D - IS_ENABLED(CONFIG_MITIGATION_L1TF) ? L1TF_MITIGATION_FLUSH : L1TF_MITIGAT= ION_OFF; + IS_ENABLED(CONFIG_MITIGATION_L1TF) ? L1TF_MITIGATION_AUTO : L1TF_MITIGATI= ON_OFF; #if IS_ENABLED(CONFIG_KVM_INTEL) EXPORT_SYMBOL_GPL(l1tf_mitigation); #endif @@ -2580,23 +2582,36 @@ static void override_cache_bits(struct cpuinfo_x86 = *c) } =20 static void __init l1tf_select_mitigation(void) +{ + if (!boot_cpu_has_bug(X86_BUG_L1TF) || cpu_mitigations_off()) { + l1tf_mitigation =3D L1TF_MITIGATION_OFF; + return; + } + + if (l1tf_mitigation =3D=3D L1TF_MITIGATION_AUTO) { + if (cpu_mitigations_auto_nosmt()) + l1tf_mitigation =3D L1TF_MITIGATION_FLUSH_NOSMT; + else + l1tf_mitigation =3D L1TF_MITIGATION_FLUSH; + } + +} + +static void __init l1tf_apply_mitigation(void) { u64 half_pa; =20 if (!boot_cpu_has_bug(X86_BUG_L1TF)) return; =20 - if (cpu_mitigations_off()) - l1tf_mitigation =3D L1TF_MITIGATION_OFF; - else if (cpu_mitigations_auto_nosmt()) - l1tf_mitigation =3D L1TF_MITIGATION_FLUSH_NOSMT; - override_cache_bits(&boot_cpu_data); =20 switch (l1tf_mitigation) { case L1TF_MITIGATION_OFF: + return; case L1TF_MITIGATION_FLUSH_NOWARN: case L1TF_MITIGATION_FLUSH: + case L1TF_MITIGATION_AUTO: break; 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Tue, 5 Nov 2024 15:55:30 -0600 From: David Kaplan To: Thomas Gleixner , Borislav Petkov , Peter Zijlstra , Josh Poimboeuf , Pawan Gupta , Ingo Molnar , Dave Hansen , , "H . Peter Anvin" CC: Subject: [PATCH v2 18/35] x86/bugs: Restructure srso mitigation Date: Tue, 5 Nov 2024 15:54:38 -0600 Message-ID: <20241105215455.359471-19-david.kaplan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105215455.359471-1-david.kaplan@amd.com> References: <20241105215455.359471-1-david.kaplan@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B374:EE_|PH7PR12MB6809:EE_ X-MS-Office365-Filtering-Correlation-Id: 8d47968d-f443-4dd0-dd2c-08dcfde49311 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|7416014|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?DKtVaKZcfz6iouk31xwdochWmHmpAbGS0pMo4CQylzybAmFnAML2r6vYcPIj?= =?us-ascii?Q?xdsFAL3p+AjR2egpCDYRRZYj256xYtQZvaYd17U2IZ2FAEyUdx9nZGtM0WIq?= =?us-ascii?Q?LrmLR8PWZfYBCJbvSznDzmm4sdo7mN60er9sC/gtKXvZMDGEkL5EdpZRFDdh?= =?us-ascii?Q?f+4BOEi04jFIyUI34J91sQjvjkLP8rR1Nn4MAwgXVGxUkNhel92AU8qsP6An?= =?us-ascii?Q?ep6rRB3mZj+r41j9YdTTzdANsuYobqoar3bvA3/TpkwNqH9JxpQ+EySRAU6h?= =?us-ascii?Q?hmYLhoqITtunI+tzlgRlULvdoqHnYTa6NiLNBNqRhPEUMqWmF7euCLnZOfa4?= =?us-ascii?Q?Xu8bskArUX34mgqLkvOKCFdlAh4UuLZyBQHztnZGH3W1kDKrQdvyXeKpm00b?= =?us-ascii?Q?iyyLULFsUeaxRXFrVVwu6PLA9YypIYg8OFz68tVljRy/R6unPLYJH4Wy77ns?= =?us-ascii?Q?FkdpVXGcRucb95zP9fzQ1Hg147uXKrE9eenShHv+tMtO4DjaNCuj5M36he/4?= =?us-ascii?Q?PbHyTa9XQwaLECQQEuPhIw6w5zVNLCPej9G6tKwkmPNhHL+ANY95fGT9T48i?= =?us-ascii?Q?Vz6NcQa7Bkv85Bnrw86xSrEfRoUkCm57/ptRtGv0NgkT6wcFXsqUlEouW7Nv?= =?us-ascii?Q?Yof5XY7CoFlXB/ePUX4N6dgMVnpP4pi88r7F2ds7DNTb7mujmgAApYCrmd2i?= =?us-ascii?Q?JVRNzaAZjLCH9C+pVJ+65tR+mV/42povHeXgnuosEr2pux8r5uiBZ1AWT76d?= =?us-ascii?Q?OkEST11ADe31BOjKkEM3vFfYuxyjo5GzORMKsHEdv4dQ6S0XwRaKBELB34I5?= =?us-ascii?Q?JWyCkSksnkue1kezoJwz7GyiJo/81+V4uI9tPAk7trE7VSkq1bhMzwLPboG8?= =?us-ascii?Q?kqsEMcOpAXMCgZHk3hiOmJHWYRRIA0//D0iAfgk3TDJWYUsm+3YrRcaZWjww?= =?us-ascii?Q?nWmbE26GK1QIJDBanp4jZu3H7KLhl1T0kTUgbrsKHRb772RTyIZY94yf4M6e?= =?us-ascii?Q?QuLxqL47re9RGesJZsWoQDW338Wziwo4S7wM1qwizn5w6vLtz81K9we3+RqR?= =?us-ascii?Q?v4oZPRyPGz3VNu3gZtY2H8mJa7+PIOxJjEEVAA+jrAkbhXyYdB0nK9+zzMSt?= =?us-ascii?Q?LdG18qADLRVrSJKCn4YDfTSNhQx5hxfp5OTqO0WhPKtZRDNXYCjZk35Nx8aK?= =?us-ascii?Q?j3Ju/WPKFTURCTNFGUvIRIsHBfWWMABR8kx1860bzT5Tt+rmjfybZEMSZheU?= =?us-ascii?Q?Swhb/acLDymA+J91ZGrocuSAShzD6OjFW3A+HfwDCP+d0vHuHme78AsQlk2j?= =?us-ascii?Q?tVkV0OwhHlxVQ1uBThie2RfpeTntGJW70AIa1k1xHSG9i9DXHtLFWYeevKOF?= =?us-ascii?Q?dmh8q1wjhWdU7UAzYBuLQaW4MpExHdM14WLYIn2zpmyRw/oogg=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(7416014)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 21:55:34.0935 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8d47968d-f443-4dd0-dd2c-08dcfde49311 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B374.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6809 Content-Type: text/plain; charset="utf-8" Restructure srso to use select/update/apply functions to create consistent vulnerability handling. Like with retbleed, the command line options directly select mitigations which can later be modified. Signed-off-by: David Kaplan --- arch/x86/kernel/cpu/bugs.c | 182 ++++++++++++++++++------------------- 1 file changed, 89 insertions(+), 93 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 98ef1cbc9e2a..178415d8026a 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -84,6 +84,8 @@ static void __init srbds_select_mitigation(void); static void __init srbds_apply_mitigation(void); static void __init l1d_flush_select_mitigation(void); static void __init srso_select_mitigation(void); +static void __init srso_update_mitigation(void); +static void __init srso_apply_mitigation(void); static void __init gds_select_mitigation(void); static void __init gds_apply_mitigation(void); static void __init bhi_select_mitigation(void); @@ -200,11 +202,6 @@ void __init cpu_select_mitigations(void) rfds_select_mitigation(); srbds_select_mitigation(); l1d_flush_select_mitigation(); - - /* - * srso_select_mitigation() depends and must run after - * retbleed_select_mitigation(). - */ srso_select_mitigation(); gds_select_mitigation(); bhi_select_mitigation(); @@ -220,6 +217,7 @@ void __init cpu_select_mitigations(void) taa_update_mitigation(); mmio_update_mitigation(); rfds_update_mitigation(); + srso_update_mitigation(); =20 spectre_v1_apply_mitigation(); spectre_v2_apply_mitigation(); @@ -232,6 +230,7 @@ void __init cpu_select_mitigations(void) mmio_apply_mitigation(); rfds_apply_mitigation(); srbds_apply_mitigation(); + srso_apply_mitigation(); gds_apply_mitigation(); bhi_apply_mitigation(); } @@ -2671,6 +2670,7 @@ early_param("l1tf", l1tf_cmdline); =20 enum srso_mitigation { SRSO_MITIGATION_NONE, + SRSO_MITIGATION_AUTO, SRSO_MITIGATION_UCODE_NEEDED, SRSO_MITIGATION_SAFE_RET_UCODE_NEEDED, SRSO_MITIGATION_MICROCODE, @@ -2679,14 +2679,6 @@ enum srso_mitigation { SRSO_MITIGATION_IBPB_ON_VMEXIT, }; =20 -enum srso_mitigation_cmd { - SRSO_CMD_OFF, - SRSO_CMD_MICROCODE, - SRSO_CMD_SAFE_RET, - SRSO_CMD_IBPB, - SRSO_CMD_IBPB_ON_VMEXIT, -}; - static const char * const srso_strings[] =3D { [SRSO_MITIGATION_NONE] =3D "Vulnerable", [SRSO_MITIGATION_UCODE_NEEDED] =3D "Vulnerable: No microcode", @@ -2697,8 +2689,7 @@ static const char * const srso_strings[] =3D { [SRSO_MITIGATION_IBPB_ON_VMEXIT] =3D "Mitigation: IBPB on VMEXIT only" }; =20 -static enum srso_mitigation srso_mitigation __ro_after_init =3D SRSO_MITIG= ATION_NONE; -static enum srso_mitigation_cmd srso_cmd __ro_after_init =3D SRSO_CMD_SAFE= _RET; +static enum srso_mitigation srso_mitigation __ro_after_init =3D SRSO_MITIG= ATION_AUTO; =20 static int __init srso_parse_cmdline(char *str) { @@ -2706,15 +2697,15 @@ static int __init srso_parse_cmdline(char *str) return -EINVAL; =20 if (!strcmp(str, "off")) - srso_cmd =3D SRSO_CMD_OFF; + srso_mitigation =3D SRSO_MITIGATION_NONE; else if (!strcmp(str, "microcode")) - srso_cmd =3D SRSO_CMD_MICROCODE; + srso_mitigation =3D SRSO_MITIGATION_MICROCODE; else if (!strcmp(str, "safe-ret")) - srso_cmd =3D SRSO_CMD_SAFE_RET; + srso_mitigation =3D SRSO_MITIGATION_SAFE_RET; else if (!strcmp(str, "ibpb")) - srso_cmd =3D SRSO_CMD_IBPB; + srso_mitigation =3D SRSO_MITIGATION_IBPB; else if (!strcmp(str, "ibpb-vmexit")) - srso_cmd =3D SRSO_CMD_IBPB_ON_VMEXIT; + srso_mitigation =3D SRSO_MITIGATION_IBPB_ON_VMEXIT; else pr_err("Ignoring unknown SRSO option (%s).", str); =20 @@ -2728,13 +2719,15 @@ static void __init srso_select_mitigation(void) { bool has_microcode =3D boot_cpu_has(X86_FEATURE_IBPB_BRTYPE); =20 - if (!boot_cpu_has_bug(X86_BUG_SRSO) || - cpu_mitigations_off() || - srso_cmd =3D=3D SRSO_CMD_OFF) { - if (boot_cpu_has(X86_FEATURE_SBPB)) - x86_pred_cmd =3D PRED_CMD_SBPB; + if (!boot_cpu_has_bug(X86_BUG_SRSO) || cpu_mitigations_off()) + srso_mitigation =3D SRSO_MITIGATION_NONE; + + if (srso_mitigation =3D=3D SRSO_MITIGATION_NONE) return; - } + + /* Default mitigation */ + if (srso_mitigation =3D=3D SRSO_MITIGATION_AUTO) + srso_mitigation =3D SRSO_MITIGATION_SAFE_RET; =20 if (has_microcode) { /* @@ -2747,94 +2740,97 @@ static void __init srso_select_mitigation(void) setup_force_cpu_cap(X86_FEATURE_SRSO_NO); return; } - - if (retbleed_mitigation =3D=3D RETBLEED_MITIGATION_IBPB) { - srso_mitigation =3D SRSO_MITIGATION_IBPB; - goto out; - } } else { pr_warn("IBPB-extending microcode not applied!\n"); pr_warn(SRSO_NOTICE); =20 - /* may be overwritten by SRSO_CMD_SAFE_RET below */ - srso_mitigation =3D SRSO_MITIGATION_UCODE_NEEDED; + /* Fall-back to Safe-RET */ + srso_mitigation =3D SRSO_MITIGATION_SAFE_RET_UCODE_NEEDED; } =20 - switch (srso_cmd) { - case SRSO_CMD_MICROCODE: - if (has_microcode) { - srso_mitigation =3D SRSO_MITIGATION_MICROCODE; - pr_warn(SRSO_NOTICE); - } + switch (srso_mitigation) { + case SRSO_MITIGATION_MICROCODE: + pr_warn(SRSO_NOTICE); break; =20 - case SRSO_CMD_SAFE_RET: - if (IS_ENABLED(CONFIG_MITIGATION_SRSO)) { - /* - * Enable the return thunk for generated code - * like ftrace, static_call, etc. - */ - setup_force_cpu_cap(X86_FEATURE_RETHUNK); - setup_force_cpu_cap(X86_FEATURE_UNRET); - - if (boot_cpu_data.x86 =3D=3D 0x19) { - setup_force_cpu_cap(X86_FEATURE_SRSO_ALIAS); - x86_return_thunk =3D srso_alias_return_thunk; - } else { - setup_force_cpu_cap(X86_FEATURE_SRSO); - x86_return_thunk =3D srso_return_thunk; - } - if (has_microcode) - srso_mitigation =3D SRSO_MITIGATION_SAFE_RET; - else - srso_mitigation =3D SRSO_MITIGATION_SAFE_RET_UCODE_NEEDED; - } else { + case SRSO_MITIGATION_SAFE_RET: + case SRSO_MITIGATION_SAFE_RET_UCODE_NEEDED: + if (!IS_ENABLED(CONFIG_MITIGATION_SRSO)) pr_err("WARNING: kernel not compiled with MITIGATION_SRSO.\n"); - } break; =20 - case SRSO_CMD_IBPB: - if (IS_ENABLED(CONFIG_MITIGATION_IBPB_ENTRY)) { - if (has_microcode) { - setup_force_cpu_cap(X86_FEATURE_ENTRY_IBPB); - srso_mitigation =3D SRSO_MITIGATION_IBPB; - - /* - * IBPB on entry already obviates the need for - * software-based untraining so clear those in case some - * other mitigation like Retbleed has selected them. - */ - setup_clear_cpu_cap(X86_FEATURE_UNRET); - setup_clear_cpu_cap(X86_FEATURE_RETHUNK); - } - } else { + case SRSO_MITIGATION_IBPB: + if (!IS_ENABLED(CONFIG_MITIGATION_IBPB_ENTRY)) pr_err("WARNING: kernel not compiled with MITIGATION_IBPB_ENTRY.\n"); - } break; =20 - case SRSO_CMD_IBPB_ON_VMEXIT: - if (IS_ENABLED(CONFIG_MITIGATION_SRSO)) { - if (!boot_cpu_has(X86_FEATURE_ENTRY_IBPB) && has_microcode) { - setup_force_cpu_cap(X86_FEATURE_IBPB_ON_VMEXIT); - srso_mitigation =3D SRSO_MITIGATION_IBPB_ON_VMEXIT; + case SRSO_MITIGATION_IBPB_ON_VMEXIT: + if (!IS_ENABLED(CONFIG_MITIGATION_SRSO)) + pr_err("WARNING: kernel not compiled with MITIGATION_SRSO.\n"); + break; + default: + break; + } +} + +static void __init srso_update_mitigation(void) +{ + /* If retbleed is using IBPB, that works for SRSO as well */ + if (retbleed_mitigation =3D=3D RETBLEED_MITIGATION_IBPB) + srso_mitigation =3D SRSO_MITIGATION_IBPB; + + if (srso_mitigation !=3D SRSO_MITIGATION_NONE) + pr_info("%s\n", srso_strings[srso_mitigation]); +} =20 - /* - * There is no need for RSB filling: entry_ibpb() ensures - * all predictions, including the RSB, are invalidated, - * regardless of IBPB implementation. - */ - setup_clear_cpu_cap(X86_FEATURE_RSB_VMEXIT); - } +static void __init srso_apply_mitigation(void) +{ + if (srso_mitigation =3D=3D SRSO_MITIGATION_NONE) { + if (boot_cpu_has(X86_FEATURE_SBPB)) + x86_pred_cmd =3D PRED_CMD_SBPB; + return; + } + switch (srso_mitigation) { + case SRSO_MITIGATION_SAFE_RET: + case SRSO_MITIGATION_SAFE_RET_UCODE_NEEDED: + /* + * Enable the return thunk for generated code + * like ftrace, static_call, etc. + */ + setup_force_cpu_cap(X86_FEATURE_RETHUNK); + setup_force_cpu_cap(X86_FEATURE_UNRET); + + if (boot_cpu_data.x86 =3D=3D 0x19) { + setup_force_cpu_cap(X86_FEATURE_SRSO_ALIAS); + x86_return_thunk =3D srso_alias_return_thunk; } else { - pr_err("WARNING: kernel not compiled with MITIGATION_SRSO.\n"); - } + setup_force_cpu_cap(X86_FEATURE_SRSO); + x86_return_thunk =3D srso_return_thunk; + } + break; + case SRSO_MITIGATION_IBPB: + setup_force_cpu_cap(X86_FEATURE_ENTRY_IBPB); + /* + * IBPB on entry already obviates the need for + * software-based untraining so clear those in case some + * other mitigation like Retbleed has selected them. + */ + setup_clear_cpu_cap(X86_FEATURE_UNRET); + setup_clear_cpu_cap(X86_FEATURE_RETHUNK); + break; + case SRSO_MITIGATION_IBPB_ON_VMEXIT: + setup_force_cpu_cap(X86_FEATURE_IBPB_ON_VMEXIT); + /* + * There is no need for RSB filling: entry_ibpb() ensures + * all predictions, including the RSB, are invalidated, + * regardless of IBPB implementation. + */ + setup_clear_cpu_cap(X86_FEATURE_RSB_VMEXIT); break; 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Note that while mitigating against untrusted userspace requires both mitigate_user_kernel and mitigate_user_user, these are kept separate. The kernel can control what code executes inside of it and that may affect the risk associated with vulnerabilities especially if new kernel mitigations are implemented. The same isn't typically true of userspace. In other words, the risk associated with user_user or guest_guest attacks is unlikely to change over time. While the risk associated with user_kernel or guest_host attacks may change. Therefore, these controls are separated. Signed-off-by: David Kaplan --- .../hw-vuln/attack_vector_controls.rst | 172 ++++++++++++++++++ Documentation/admin-guide/hw-vuln/index.rst | 1 + 2 files changed, 173 insertions(+) create mode 100644 Documentation/admin-guide/hw-vuln/attack_vector_control= s.rst diff --git a/Documentation/admin-guide/hw-vuln/attack_vector_controls.rst b= /Documentation/admin-guide/hw-vuln/attack_vector_controls.rst new file mode 100644 index 000000000000..541c8a3cac13 --- /dev/null +++ b/Documentation/admin-guide/hw-vuln/attack_vector_controls.rst @@ -0,0 +1,172 @@ +.. SPDX-License-Identifier: GPL-2.0 + +Attack Vector Controls +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Attack vector controls provide a simple method to configure only the mitig= ations +for CPU vulnerabilities which are relevant given the intended use of a sys= tem. +Administrators are encouraged to consider which attack vectors are relevan= t and +disable all others in order to recoup system performance. + +When new relevant CPU vulnerabilities are found, they will be added to the= se +attack vector controls so administrators will likely not need to reconfigu= re +their command line parameters as mitigations will continue to be correctly +applied based on the chosen attack vector controls. + +Attack Vectors +-------------- + +There are 5 sets of attack-vector mitigations currently supported by the k= ernel: + +#. :ref:`user_kernel` (mitigate_user_kernel=3D ) +#. :ref:`user_user` (mitigate_user_user=3D ) +#. :ref:`guest_host` (mitigate_guest_host=3D ) +#. :ref:`guest_guest` (mitigate_guest_guest=3D) +#. :ref:`cross_thread` (mitigate_cross_thread=3D ) + +Each control may either be specified as 'off' or 'on'. + +.. _user_kernel: + +User-to-Kernel +^^^^^^^^^^^^^^ + +The user-to-kernel attack vector involves a malicious userspace program +attempting to leak kernel data into userspace by exploiting a CPU vulnerab= ility. +The kernel data involved might be limited to certain kernel memory, or inc= lude +all memory in the system, depending on the vulnerability exploited. + +If no untrusted userspace applications are being run, such as with single-= user +systems, consider disabling user-to-kernel mitigations. + +Note that the CPU vulnerabilities mitigated by Linux have generally not be= en +shown to be exploitable from browser-based sandboxes. User-to-kernel +mitigations are therefore mostly relevant if unknown userspace application= s may +be run by untrusted users. + +*mitigate_user_kernel defaults to 'on'* + +.. _user_user: + +User-to-User +^^^^^^^^^^^^ + +The user-to-user attack vector involves a malicious userspace program atte= mpting +to influence the behavior of another unsuspecting userspace program in ord= er to +exfiltrate data. The vulnerability of a userspace program is based on the +program itself and the interfaces it provides. + +If no untrusted userspace applications are being run, consider disabling +user-to-user mitigations. + +Note that because the Linux kernel contains a mapping of all physical memo= ry, +preventing a malicious userspace program from leaking data from another +userspace program requires mitigating user-to-kernel attacks as well for +complete protection. + +*mitigate_user_user defaults to 'on'* + +.. _guest_host: + +Guest-to-Host +^^^^^^^^^^^^^ + +The guest-to-host attack vector involves a malicious VM attempting to leak +hypervisor data into the VM. The data involved may be limited, or may +potentially include all memory in the system, depending on the vulnerabili= ty +exploited. + +If no untrusted VMs are being run, consider disabling guest-to-host mitiga= tions. + +*mitigate_guest_host defaults to 'on' if KVM support is present* + +.. _guest_guest: + +Guest-to-Guest +^^^^^^^^^^^^^^ + +The guest-to-guest attack vector involves a malicious VM attempting to inf= luence +the behavior of another unsuspecting VM in order to exfiltrate data. The +vulnerability of a VM is based on the code inside the VM itself and the +interfaces it provides. + +If no untrusted VMs, or only a single VM is being run, consider disabling +guest-to-guest mitigations. + +Similar to the user-to-user attack vector, preventing a malicious VM from +leaking data from another VM requires mitigating guest-to-host attacks as = well +due to the Linux kernel phys map. + +*mitigate_guest_guest defaults to 'on' if KVM support is present* + +.. _cross_thread: + +Cross-Thread +^^^^^^^^^^^^ + +The cross-thread attack vector involves a malicious userspace program or +malicious VM either observing or attempting to influence the behavior of c= ode +running on the SMT sibling thread in order to exfiltrate data. + +Many cross-thread attacks can only be mitigated if SMT is disabled, which = will +result in reduced CPU core count and reduced performance. Enabling mitiga= tions +for the cross-thread attack vector may result in SMT being disabled, depen= ding +on the CPU vulnerabilities detected. + +*mitigate_cross_thread defaults to 'off'* + +Interactions with command-line options +-------------------------------------- + +The global 'mitigations=3Doff' command line takes precedence over all atta= ck +vector controls and will disable all mitigations. + +Vulnerability-specific controls (e.g. "retbleed=3Doff") take precedence ov= er all +attack vector controls. Mitigations for individual vulnerabilities may be +turned on or off via their command-line options regardless of the attack v= ector +controls. + +Summary of attack-vector mitigations +------------------------------------ + +When a vulnerability is mitigated due to an attack-vector control, the def= ault +mitigation option for that particular vulnerability is used. To use a dif= ferent +mitigation, please use the vulnerability-specific command line option. + +The table below summarizes which vulnerabilities are mitigated when differ= ent +attack vectors are enabled and assuming the CPU is vulnerable. + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D +Vulnerability User-to-Kernel User-to-User Guest-to-Host Guest-to-Guest C= ross-Thread +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D +BHI X X +GDS X X X X = X +L1TF X = (Note 1) +MDS X X X X = (Note 1) +MMIO X X X X = (Note 1) +Meltdown X +Retbleed X X = (Note 2) +RFDS X X X X +Spectre_v1 X +Spectre_v2 X X +Spectre_v2_user X X +SRBDS X X X X +SRSO X X +SSB (Note 3) +TAA X X X X = (Note 1) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D + +Notes: + 1 -- Disables SMT if cross-thread mitigations are selected and CPU is = vulnerable + + 2 -- Disables SMT if cross-thread mitigations are selected, CPU is vul= nerable, + and STIBP is not supported + + 3 -- Speculative store bypass is always enabled by default (no kernel + mitigation applied) unless overridden with spec_store_bypass_disable op= tion + +When an attack-vector is disabled (e.g., *mitigate_user_kernel=3Doff*), all +mitigations for the vulnerabilities listed in the above table are disabled, +unless mitigation is required for a different enabled attack-vector or a +mitigation is explicitly selected via a vulnerability-specific command line +option. diff --git a/Documentation/admin-guide/hw-vuln/index.rst b/Documentation/ad= min-guide/hw-vuln/index.rst index ff0b440ef2dc..1add4a0baeb0 100644 --- a/Documentation/admin-guide/hw-vuln/index.rst +++ b/Documentation/admin-guide/hw-vuln/index.rst @@ -9,6 +9,7 @@ are configurable at compile, boot or run time. .. toctree:: :maxdepth: 1 =20 + attack_vector_controls spectre l1tf mds --=20 2.34.1 From nobody Sun Nov 24 11:56:51 2024 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2061.outbound.protection.outlook.com [40.107.94.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D56F7217302 for ; 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Peter Anvin" CC: Subject: [PATCH v2 20/35] x86/bugs: Define attack vectors Date: Tue, 5 Nov 2024 15:54:40 -0600 Message-ID: <20241105215455.359471-21-david.kaplan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105215455.359471-1-david.kaplan@amd.com> References: <20241105215455.359471-1-david.kaplan@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B374:EE_|SA1PR12MB5672:EE_ X-MS-Office365-Filtering-Correlation-Id: 6c986a0a-3ba1-456a-6255-08dcfde49378 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|36860700013|82310400026|1800799024|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?mr3C1UsW9YqwqVfsfirjD6qiNk9Z4U6sHLl5eViTQI1WPi2ofTAsiPclsi6O?= =?us-ascii?Q?eY7A7uO2to9J9rlFEM5lveqTGLnC2pZxuXQc02A63bFy6X0tXX1yj8W7uu4t?= =?us-ascii?Q?/am4osmVhrZITthoonZZd7nbIZ3SeGU+yEfrt4N9//AxB7zBgkAaUypIOUKq?= =?us-ascii?Q?PNTYybhpJVsFIja/jzyAswTNmZj+O6JzhkgYv03tbOnKj1NtnGN3ylHDngxl?= =?us-ascii?Q?Xi+MgpOO8W3VcDaFTja03DNxx5sR8JH2JcwuZZvev07pF0dCBVGQh08F3r9C?= =?us-ascii?Q?IadDIIa+tlTP1dr2sUBO+5dEpi6gD4QUUygmOXJJUvAQfMkr+ygnXv/P6RtP?= =?us-ascii?Q?djNG+i44zhQEZvP/YFmnbaahTmjODK53smZe2pbhxKr8pRr0GFsu5DpQ0b9A?= =?us-ascii?Q?m6aRSWfA/KoEMAAt7rLV5F307ZV+PG3QdKMrGGlh3DrtThLKDW5wvskPt/NH?= =?us-ascii?Q?cy3QVPx2i2Bc5Pj9bPEwCFrfgmOfpvvaSvr1m8W0d3XplQOAO6UOp4qCNPPR?= =?us-ascii?Q?nxAwbQBFlERLfv4jIxu+908D+7j8Agso0k7fBWpGEzOewvmyxwAYUDqaJ7SE?= =?us-ascii?Q?/PUB+cUa5t/pyyHnX6n02EQWepzoiGysRRuXGp50hCVudTxMx15GKQ+IlagR?= =?us-ascii?Q?98gVWT318SzJ1htIGmw7lvCGlehU+Ufuw2O0S+dtRp9rp5an7iFP34WAAJL8?= =?us-ascii?Q?C7dMuKgzr6g7q+7ILHRc5eTT1EKYMWdYQwXuNykAFLGFpUzMVE5E36mtrYiS?= =?us-ascii?Q?nop4lmwaBRrr+Mcf5Hlphc/QGLuLURl9DUcQDfeOQWdUwX6C+DCqs1xeogb9?= =?us-ascii?Q?iXThD8Hz3nhQgxRN9r6zElx21p+U9Gt6oyLOi7L3QRKIZ4r+At31PdU5PLCa?= =?us-ascii?Q?MRLYKMxXMHKl0+UN8WzLr6yCGau7hx8m8fRLFnGjacm4TugpDEY1f9KmHkBa?= =?us-ascii?Q?pK3HlmM8wHRxoxC70lkvCEB2EjeZwL1LnEYkQ3QF4eVBMex1+2PRUgEsP3rk?= =?us-ascii?Q?Us+ll6zdXUajmV/Z1j+1yWQOnPXwYwG9kSpSFrC6enRfz8fvegnT60HfarbO?= =?us-ascii?Q?330YdIp+EK6gVttoOxhxH37uej6/WE0IeMxzxUITx9iZ/18fbQJ5Gdzdq+fA?= =?us-ascii?Q?mNfUitF1ZIJ3w6gLoxf4UXoSR5/vZAfRo59AakLbMH2Z+uXkoJluhRTsKs+U?= =?us-ascii?Q?kkgpu7xkWp8oP1IG8MBEDbHd10OQaFydawljpSLjeBJCM7ZZmvQIdrIjjdV+?= =?us-ascii?Q?aMePvfNcL2Wd/xW65fgwVM+0gb2+BVl+5IB2cZtY04f1tLeWjX3w2IY4rOrc?= =?us-ascii?Q?+ZZp2q+JgIoXhWJoULZDoEa5Ml+z0E/3yxU499vxxahGBS6wAVxPfllW19ti?= =?us-ascii?Q?ePRCQ8Rn2sd6meWUS+jp3CC5IIElNQ0G1bO4xOJPOD0xpHtDvg=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(7416014)(36860700013)(82310400026)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 21:55:34.7497 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6c986a0a-3ba1-456a-6255-08dcfde49378 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B374.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB5672 Content-Type: text/plain; charset="utf-8" Define 5 new attack vectors that are used for controlling CPU speculation mitigations and associated command line options. Each attack vector may be enabled or disabled, which affects the CPU mitigations enabled. The default settings for these attack vectors are consistent with existing kernel defaults, other than the automatic disabling of VM-based attack vectors if KVM support is not present. Signed-off-by: David Kaplan --- include/linux/cpu.h | 11 +++++++++ kernel/cpu.c | 58 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+) diff --git a/include/linux/cpu.h b/include/linux/cpu.h index bdcec1732445..b25566e1fb04 100644 --- a/include/linux/cpu.h +++ b/include/linux/cpu.h @@ -189,6 +189,17 @@ void cpuhp_report_idle_dead(void); static inline void cpuhp_report_idle_dead(void) { } #endif /* #ifdef CONFIG_HOTPLUG_CPU */ =20 +enum cpu_attack_vectors { + CPU_MITIGATE_USER_KERNEL, + CPU_MITIGATE_USER_USER, + CPU_MITIGATE_GUEST_HOST, + CPU_MITIGATE_GUEST_GUEST, + CPU_MITIGATE_CROSS_THREAD, + NR_CPU_ATTACK_VECTORS, +}; + +bool cpu_mitigate_attack_vector(enum cpu_attack_vectors v); + #ifdef CONFIG_CPU_MITIGATIONS extern bool cpu_mitigations_off(void); extern bool cpu_mitigations_auto_nosmt(void); diff --git a/kernel/cpu.c b/kernel/cpu.c index d0699e47178b..841bcffee5d3 100644 --- a/kernel/cpu.c +++ b/kernel/cpu.c @@ -3200,6 +3200,22 @@ enum cpu_mitigations { =20 static enum cpu_mitigations cpu_mitigations __ro_after_init =3D CPU_MITIGA= TIONS_AUTO; =20 +/* + * All except the cross-thread attack vector are mitigated by default. + * Cross-thread mitigation often requires disabling SMT which is too expen= sive + * to be enabled by default. + * + * Guest-to-Host and Guest-to-Guest vectors are only needed if KVM support= is + * present. + */ +static bool cpu_mitigate_attack_vectors[NR_CPU_ATTACK_VECTORS] __ro_after_= init =3D { + [CPU_MITIGATE_USER_KERNEL] =3D true, + [CPU_MITIGATE_USER_USER] =3D true, + [CPU_MITIGATE_GUEST_HOST] =3D IS_ENABLED(CONFIG_KVM), + [CPU_MITIGATE_GUEST_GUEST] =3D IS_ENABLED(CONFIG_KVM), + [CPU_MITIGATE_CROSS_THREAD] =3D false +}; + static int __init mitigations_parse_cmdline(char *arg) { if (!strcmp(arg, "off")) @@ -3228,11 +3244,53 @@ bool cpu_mitigations_auto_nosmt(void) return cpu_mitigations =3D=3D CPU_MITIGATIONS_AUTO_NOSMT; } EXPORT_SYMBOL_GPL(cpu_mitigations_auto_nosmt); + +#define DEFINE_ATTACK_VECTOR(opt, v) \ +static int __init v##_parse_cmdline(char *arg) \ +{ \ + if (!strcmp(arg, "off")) \ + cpu_mitigate_attack_vectors[v] =3D false; \ + else if (!strcmp(arg, "on")) \ + cpu_mitigate_attack_vectors[v] =3D true; \ + else \ + pr_warn("Unsupported " opt "=3D%s\n", arg); \ + return 0; \ +} \ +early_param(opt, v##_parse_cmdline) + +bool cpu_mitigate_attack_vector(enum cpu_attack_vectors v) +{ + BUG_ON(v >=3D NR_CPU_ATTACK_VECTORS); + return cpu_mitigate_attack_vectors[v]; +} +EXPORT_SYMBOL_GPL(cpu_mitigate_attack_vector); + #else static int __init mitigations_parse_cmdline(char *arg) { pr_crit("Kernel compiled without mitigations, ignoring 'mitigations'; sys= tem may still be vulnerable\n"); return 0; } + +#define DEFINE_ATTACK_VECTOR(opt, v) \ +static int __init v##_parse_cmdline(char *arg) \ +{ \ + pr_crit("Kernel compiled without mitigations, ignoring %s; system may sti= ll be vulnerable\n", opt); \ + return 0; \ +} \ +early_param(opt, v##_parse_cmdline) + +bool cpu_mitigate_attack_vector(enum cpu_attack_vectors v) +{ + return false; +} +EXPORT_SYMBOL_GPL(cpu_mitigate_attack_vector); + #endif early_param("mitigations", mitigations_parse_cmdline); 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Peter Anvin" CC: Subject: [PATCH v2 21/35] x86/bugs: Determine relevant vulnerabilities based on attack vector controls. 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The selections here are based on the individual characteristics of each vulnerability. Signed-off-by: David Kaplan --- arch/x86/kernel/cpu/bugs.c | 69 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 178415d8026a..6a5996d3b324 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -287,6 +287,75 @@ static void x86_amd_ssb_disable(void) wrmsrl(MSR_AMD64_LS_CFG, msrval); } =20 +/* + * Returns true if vulnerability should be mitigated based on the + * selected attack vector controls + * + * See Documentation/admin-guide/hw-vuln/attack_vector_controls.rst + */ +static bool __init should_mitigate_vuln(unsigned int bug) +{ + switch (bug) { + /* + * The only spectre_v1 mitigations in the kernel are related to + * SWAPGS protection on kernel entry. Therefore, protection is + * only required for the user->kernel attack vector. + */ + case X86_BUG_SPECTRE_V1: + return cpu_mitigate_attack_vector(CPU_MITIGATE_USER_KERNEL); + + /* + * Both spectre_v2 and srso may allow user->kernel or + * guest->host attacks through branch predictor manipulation. + */ + case X86_BUG_SPECTRE_V2: + case X86_BUG_SRSO: + return cpu_mitigate_attack_vector(CPU_MITIGATE_USER_KERNEL) || + cpu_mitigate_attack_vector(CPU_MITIGATE_GUEST_HOST); + + /* + * spectre_v2_user refers to user->user or guest->guest branch + * predictor attacks only. Other indirect branch predictor attacks + * are covered by the spectre_v2 vulnerability. + */ + case X86_BUG_SPECTRE_V2_USER: + return cpu_mitigate_attack_vector(CPU_MITIGATE_USER_USER) || + cpu_mitigate_attack_vector(CPU_MITIGATE_GUEST_GUEST); + + /* L1TF is only possible as a guest->host attack */ + case X86_BUG_L1TF: + return cpu_mitigate_attack_vector(CPU_MITIGATE_GUEST_HOST); + + /* + * All the vulnerabilities below allow potentially leaking data + * across address spaces. Therefore, mitigation is required for + * any of these 4 attack vectors. + */ + case X86_BUG_MDS: + case X86_BUG_TAA: + case X86_BUG_MMIO_STALE_DATA: + case X86_BUG_RFDS: + case X86_BUG_SRBDS: + return cpu_mitigate_attack_vector(CPU_MITIGATE_USER_KERNEL) || + cpu_mitigate_attack_vector(CPU_MITIGATE_GUEST_HOST) || + cpu_mitigate_attack_vector(CPU_MITIGATE_USER_USER) || + cpu_mitigate_attack_vector(CPU_MITIGATE_GUEST_GUEST); + /* + * GDS can potentially leak data across address spaces and + * threads. Mitigation is required under all attack vectors. + */ + case X86_BUG_GDS: + return cpu_mitigate_attack_vector(CPU_MITIGATE_USER_KERNEL) || + cpu_mitigate_attack_vector(CPU_MITIGATE_GUEST_HOST) || + cpu_mitigate_attack_vector(CPU_MITIGATE_USER_USER) || + cpu_mitigate_attack_vector(CPU_MITIGATE_GUEST_GUEST) || + cpu_mitigate_attack_vector(CPU_MITIGATE_CROSS_THREAD); + default: + return false; + } +} + + /* Default mitigation for MDS-affected CPUs */ static enum mds_mitigations mds_mitigation __ro_after_init =3D IS_ENABLED(CONFIG_MITIGATION_MDS) ? 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If cross-thread attack mitigations are required, disable SMT. Signed-off-by: David Kaplan --- arch/x86/kernel/cpu/bugs.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 6a5996d3b324..aa916e1af0b9 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -415,8 +415,12 @@ static void __init mds_select_mitigation(void) if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) mds_mitigation =3D MDS_MITIGATION_OFF; =20 - if (mds_mitigation =3D=3D MDS_MITIGATION_AUTO) - mds_mitigation =3D MDS_MITIGATION_FULL; + if (mds_mitigation =3D=3D MDS_MITIGATION_AUTO) { + if (should_mitigate_vuln(X86_BUG_MDS)) + mds_mitigation =3D MDS_MITIGATION_FULL; + else + mds_mitigation =3D MDS_MITIGATION_OFF; + } =20 if (mds_mitigation =3D=3D MDS_MITIGATION_FULL) { if (!boot_cpu_has(X86_FEATURE_MD_CLEAR)) @@ -445,7 +449,8 @@ static void __init mds_apply_mitigation(void) if (mds_mitigation =3D=3D MDS_MITIGATION_FULL) { setup_force_cpu_cap(X86_FEATURE_CLEAR_CPU_BUF); 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Signed-off-by: David Kaplan --- arch/x86/kernel/cpu/bugs.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index aa916e1af0b9..431182a0ecc5 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -510,11 +510,17 @@ static void __init taa_select_mitigation(void) if (taa_mitigation =3D=3D TAA_MITIGATION_OFF) return; =20 - /* This handles the AUTO case. */ - if (boot_cpu_has(X86_FEATURE_MD_CLEAR)) - taa_mitigation =3D TAA_MITIGATION_VERW; - else - taa_mitigation =3D TAA_MITIGATION_UCODE_NEEDED; + if (taa_mitigation =3D=3D TAA_MITIGATION_AUTO) { + if (should_mitigate_vuln(X86_BUG_TAA)) { + if (boot_cpu_has(X86_FEATURE_MD_CLEAR)) + taa_mitigation =3D TAA_MITIGATION_VERW; + else + taa_mitigation =3D TAA_MITIGATION_UCODE_NEEDED; + } else { + taa_mitigation =3D TAA_MITIGATION_OFF; + return; + } + } =20 /* * VERW doesn't clear the CPU buffers when MD_CLEAR=3D1 and MDS_NO=3D1. @@ -555,7 +561,8 @@ static void __init taa_apply_mitigation(void) */ setup_force_cpu_cap(X86_FEATURE_CLEAR_CPU_BUF); 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Signed-off-by: David Kaplan --- arch/x86/kernel/cpu/bugs.c | 37 ++++++++++++++++++++++--------------- 1 file changed, 22 insertions(+), 15 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 431182a0ecc5..ab1a8ae31588 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -612,20 +612,26 @@ static void __init mmio_select_mitigation(void) if (mmio_mitigation =3D=3D MMIO_MITIGATION_OFF) return; =20 - /* - * Check if the system has the right microcode. - * - * CPU Fill buffer clear mitigation is enumerated by either an explicit - * FB_CLEAR or by the presence of both MD_CLEAR and L1D_FLUSH on MDS - * affected systems. - */ - if ((x86_arch_cap_msr & ARCH_CAP_FB_CLEAR) || - (boot_cpu_has(X86_FEATURE_MD_CLEAR) && - boot_cpu_has(X86_FEATURE_FLUSH_L1D) && - !(x86_arch_cap_msr & ARCH_CAP_MDS_NO))) - mmio_mitigation =3D MMIO_MITIGATION_VERW; - else - mmio_mitigation =3D MMIO_MITIGATION_UCODE_NEEDED; + if (mmio_mitigation =3D=3D MMIO_MITIGATION_AUTO) { + if (should_mitigate_vuln(X86_BUG_MMIO_STALE_DATA)) { + /* + * Check if the system has the right microcode. + * + * CPU Fill buffer clear mitigation is enumerated by either an explicit + * FB_CLEAR or by the presence of both MD_CLEAR and L1D_FLUSH on MDS + * affected systems. + */ + if ((x86_arch_cap_msr & ARCH_CAP_FB_CLEAR) || + (boot_cpu_has(X86_FEATURE_MD_CLEAR) && + boot_cpu_has(X86_FEATURE_FLUSH_L1D) && + !(x86_arch_cap_msr & ARCH_CAP_MDS_NO))) + mmio_mitigation =3D MMIO_MITIGATION_VERW; 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Signed-off-by: David Kaplan --- arch/x86/kernel/cpu/bugs.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index ab1a8ae31588..ecf7046673b9 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -718,8 +718,14 @@ static void __init rfds_select_mitigation(void) if (rfds_mitigation =3D=3D RFDS_MITIGATION_OFF) return; =20 - if (rfds_mitigation =3D=3D RFDS_MITIGATION_AUTO) - rfds_mitigation =3D RFDS_MITIGATION_VERW; + if (rfds_mitigation =3D=3D RFDS_MITIGATION_AUTO) { + if (should_mitigate_vuln(X86_BUG_RFDS)) + rfds_mitigation =3D RFDS_MITIGATION_VERW; + else { + rfds_mitigation =3D RFDS_MITIGATION_OFF; + return; + } + } =20 if (!(x86_arch_cap_msr & ARCH_CAP_RFDS_CLEAR)) rfds_mitigation =3D RFDS_MITIGATION_UCODE_NEEDED; --=20 2.34.1 From nobody Sun Nov 24 11:56:51 2024 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2074.outbound.protection.outlook.com [40.107.236.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C4D9217904 for ; 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Signed-off-by: David Kaplan --- arch/x86/kernel/cpu/bugs.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index ecf7046673b9..083452942264 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -834,8 +834,14 @@ static void __init srbds_select_mitigation(void) if (!boot_cpu_has_bug(X86_BUG_SRBDS)) return; =20 - if (srbds_mitigation =3D=3D SRBDS_MITIGATION_AUTO) - srbds_mitigation =3D SRBDS_MITIGATION_FULL; + if (srbds_mitigation =3D=3D SRBDS_MITIGATION_AUTO) { + if (should_mitigate_vuln(X86_BUG_SRBDS)) + srbds_mitigation =3D SRBDS_MITIGATION_FULL; + else { + srbds_mitigation =3D SRBDS_MITIGATION_OFF; + return; + } + } =20 /* * Check to see if this is one of the MDS_NO systems supporting TSX that --=20 2.34.1 From nobody Sun Nov 24 11:56:51 2024 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2048.outbound.protection.outlook.com [40.107.244.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEDC9217F2B for ; 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Peter Anvin" CC: Subject: [PATCH v2 27/35] x86/bugs: Add attack vector controls for gds Date: Tue, 5 Nov 2024 15:54:47 -0600 Message-ID: <20241105215455.359471-28-david.kaplan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105215455.359471-1-david.kaplan@amd.com> References: <20241105215455.359471-1-david.kaplan@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B374:EE_|CH3PR12MB7667:EE_ X-MS-Office365-Filtering-Correlation-Id: 7628e642-950b-41b0-422a-08dcfde49641 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|7416014|376014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?jQUclHa7afDhN0J1kSQww6AoV6x4R1Zr9OpABpiPcXDgD9ZgkH9Oni6ccmEw?= =?us-ascii?Q?ff3tjVgcCMxNZQYkckvL1ZEIXAAn3y1HfVfDlb/yqLVmlvCt1EeVFsr3BiEn?= =?us-ascii?Q?H8KiGnJvv0wE/0qUdyHFbtZwm6IjMBWvTJpR94cbUntl4BthYyW99JzElVWI?= =?us-ascii?Q?QmDY0noWAgUqBT1tAWesNA2pODkpbkmAN8LkijWUqjL61sjsFkhRVJFSUt6K?= =?us-ascii?Q?OZ1LpjE9cCygYoqVzdrKwInoyIS2MJJuru05dNupOor8bADZu5hw6W526fup?= =?us-ascii?Q?id7qTr8cnmhxfaDKtoc3pwEz2K7SmfEv8bCRDCMPZaU06WW7WCI3kNoQPYvF?= =?us-ascii?Q?kV+rra9nA/HRoTOY4twMiD49oDHJEke4v0PA9w53ledFp7Ibn9TU9EOgMcR8?= =?us-ascii?Q?jbM1o9XGv3YQ/ngBQUeyR+s9EHRvfWO/0GvLkbhl5s9Lm0ttGtscrOi+Hyl7?= =?us-ascii?Q?AYy2MHS60b0ZIWOFoi5TmebZ3EDuLsyuh6IfaCdvogBWMBok685dtFGx3OHC?= =?us-ascii?Q?A877qdSLQbM+MXrEtxFnDUr2mta76mNeyppivMSeoLQy4+Gv7q6LhuY65yNl?= =?us-ascii?Q?CH8bf+L3uQgdWKay888zSIuYdctHgk7DYiFesOGxeAoXsKq9T+H0CUveX8dN?= =?us-ascii?Q?BF7fsQSwrAn3a86Xv+/IOKGaklZ0E3Flhoo0XdaHStE8qrPyCNZ3q0wSZ5Yr?= =?us-ascii?Q?9pDoyji960LT6JnupeML/GB6GZAwj3QEmWFa3B9t7U4eZENUtTbSfphKwNdx?= =?us-ascii?Q?nGDpgmUXSYkSrctvQ3z2Lzyd/h4xVXbcf+bQfW8X6+RbbK2kO8At2tpBmkJp?= =?us-ascii?Q?/HONPGF4+vD3eTPB3cPN67YsY2uDL2wTrccbp+BsHrmoMDUSRHD+DgvpDo8b?= =?us-ascii?Q?2ec01lRyUQIT3xwR8vOXnTJFn/K5D1n85Zr6qvV7L5uhPV7YfUNml3iyDsfw?= =?us-ascii?Q?hWrKhCzYZ70DjHHNx8R+mP7iJqC63dlwZFDbPKS46oORvl17c5ISM+ht8f4L?= =?us-ascii?Q?HKH3fjFKtNowSE+SLqVLD76CwQzrNaUhRJ00zkbdafWJmm9WnjiV+RVc4W0I?= =?us-ascii?Q?7ID1J/VcBZHF2PJVgLs841SWInoherQCloYbd3VCgCqehAnNx1GbVCLSh7I1?= =?us-ascii?Q?7DihdT7V9dJPagmH6mmnFAEiQsj2Dmue8yI0kxu+2hOU7LA3+WCdUYr23dLq?= =?us-ascii?Q?Phm9NlNVoTdv2sVHo85T/9PPnADZ1WCp8ugo+Ype2m2xQliElpTUfgPKGhqg?= =?us-ascii?Q?hYqLCPfA4KqXL2Vv/7IPiI5VfL8UhMwqMovtSy9r2QaB1cK9UX2Za54cMGGB?= =?us-ascii?Q?nGb9YXqO6mmbcBahM/M/HsniHfO6tB5rGQN6IO1yF4WIhEkTJvaC4S7Twee9?= =?us-ascii?Q?QYAfmMeFRC9lUhm/nxtsnKfNvHZiDZaHuuNLfx0BklB2fUbQpw=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(7416014)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 21:55:39.4372 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7628e642-950b-41b0-422a-08dcfde49641 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B374.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7667 Content-Type: text/plain; charset="utf-8" Use attack vector controls to determine if gds mitigation is required. Signed-off-by: David Kaplan --- arch/x86/kernel/cpu/bugs.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 083452942264..8612be5445ba 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -995,8 +995,14 @@ static void __init gds_select_mitigation(void) gds_mitigation =3D GDS_MITIGATION_OFF; /* Will verify below that mitigation _can_ be disabled */ =20 - if (gds_mitigation =3D=3D GDS_MITIGATION_AUTO) - gds_mitigation =3D GDS_MITIGATION_FULL; + if (gds_mitigation =3D=3D GDS_MITIGATION_AUTO) { + if (should_mitigate_vuln(X86_BUG_GDS)) + gds_mitigation =3D GDS_MITIGATION_FULL; + else { + gds_mitigation =3D GDS_MITIGATION_OFF; + return; + } + } =20 /* No microcode */ if (!(x86_arch_cap_msr & ARCH_CAP_GDS_CTRL)) { --=20 2.34.1 From nobody Sun Nov 24 11:56:51 2024 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2079.outbound.protection.outlook.com [40.107.244.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21A23217F36 for ; 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Tue, 5 Nov 2024 15:55:35 -0600 From: David Kaplan To: Thomas Gleixner , Borislav Petkov , Peter Zijlstra , Josh Poimboeuf , Pawan Gupta , Ingo Molnar , Dave Hansen , , "H . Peter Anvin" CC: Subject: [PATCH v2 28/35] x86/bugs: Add attack vector controls for spectre_v1 Date: Tue, 5 Nov 2024 15:54:48 -0600 Message-ID: <20241105215455.359471-29-david.kaplan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105215455.359471-1-david.kaplan@amd.com> References: <20241105215455.359471-1-david.kaplan@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B370:EE_|SA1PR12MB7341:EE_ X-MS-Office365-Filtering-Correlation-Id: 8eefd04e-2b3d-4ead-213c-08dcfde4969b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|7416014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?sVYPGt6WGp6T5Rm2jyXbuNCG6sHjDgsCNlzaytts92a7UzOioZAE4Bn7aI8k?= =?us-ascii?Q?xADUeFa+2Kx7B7j+FvkuIQfFGiVU8wKQSirXdKitSBr8YDDPELa8Qv/KbyaN?= =?us-ascii?Q?mlSy5askmQ7sAh5cOxr58UceImNs6CElSHeQw4vgQWp++GlVTHSMd1de9efx?= =?us-ascii?Q?xxJAM7S91oa07aEyU+rEjAUjUDN5ZuBTof9BbaqHQbEn/kXyfoH56tyPYk3D?= =?us-ascii?Q?c5y5+bzrsh70ZYhndY8nckixaA2QQl7gqw6BKlGGiqIzyrMX7i7mEDMGdQjW?= =?us-ascii?Q?EcO4c157ev1O5m+KycY+7dF7NdI+fCal6TJr6dPcWAFoCvIXghycgshDTGLs?= =?us-ascii?Q?VS1e/1MeB7/juZ8uAVaMN+EcHn9yR0IH0Mv9C+vFLEAAUohcPkYRWyWRr8WP?= =?us-ascii?Q?2K459ldPiTLopHgkZ4oJNXXYO0PDuU6UK/NBOhTqJmrTsg1l4T3K0ozmsMMF?= =?us-ascii?Q?yRJgLphc0FvD9hfVxfIxmATrN7P2W84MwiLH4yZfqNifEoDlE5+UCa7IGoeQ?= =?us-ascii?Q?+zbnOJ3wl7D7JfbC4jjfEO29VUJIJwuS8OvxQdGqHbOrgiks/5oyFC7W9uLk?= =?us-ascii?Q?JyK8Qo0Xf8zti4QUVjHhQIKNIXHHa9T+aMSUyT11Ec6naSf/xily2A9utLbA?= =?us-ascii?Q?TI557SoJoIh/osghmXX6WBw8pRjucshT90ttrcaADpPL49ZiNIUBzeLr431e?= =?us-ascii?Q?SUO9ytiw/GbtaD27WmIG12SBXi0eLDYzm8NxEowuOnIO7ceeGFdKA2jJnNM1?= =?us-ascii?Q?LZ7jxVYrReJZcZipAK30ymcbsMw3gYrCqLNg1zp5dpQpOjlyp6fbY8W//efV?= =?us-ascii?Q?e/xO6ALlvO99pXjHgdPmwbTDb4efXABQOOcudWAB+EIBp8ribuzP+ZLpO7Mo?= =?us-ascii?Q?GrfMzYzKyxecIRyxzeN1KLB6KfcE5T+Hiw/o9o3NhbKOZhjAdDvUfdgSPOH8?= =?us-ascii?Q?p1yBSPyj321sqHefeNUewDAQgtV7D0nSsjVygMDEvn/36OYSU3g+U7kWsUPi?= =?us-ascii?Q?fCR318y2nJKhSfp8MQDX1u9NZ5aN+ivTQ5jGy3oTnhQ9ZTHSIpVlXsLcBv+9?= =?us-ascii?Q?sZuBykWWGGR+BuCiYj0iCh3vz7AlBIzusQwXHQ2TZilJhH0e0wKhmeaRa/70?= =?us-ascii?Q?UpTAZptwxzp76IjXOBG99CWCb3v67Ks84N5rs2BYwIlal8GAAGZFbtmu0DLF?= =?us-ascii?Q?WC42Lej3FPBotGOvaKLrq2j25987antJhW2FOHtQFSJr+uii9GSVYxlvZ7Pa?= =?us-ascii?Q?cbgAt78wx/2YubYfphadXmcN2ouqSNNTuNkFNiJVJzUoIYUyxSkznx6VEoHL?= =?us-ascii?Q?0op2w7xtbrYwK/uyzl5ITbmC1G3ofZhjHOqdeB8Z0mzPuktNycJoJKdzYE7o?= =?us-ascii?Q?/yv1xv7KXoyWbjeG6Ep2VjyhbJLGHUjXGzeabftPYfBmUZUcMg=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(7416014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 21:55:39.9793 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8eefd04e-2b3d-4ead-213c-08dcfde4969b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B370.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7341 Content-Type: text/plain; charset="utf-8" Use attack vector controls to determine if spectre_v1 mitigation is required. Signed-off-by: David Kaplan --- arch/x86/kernel/cpu/bugs.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 8612be5445ba..f63fa8a3b9ee 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -1108,6 +1108,9 @@ static void __init spectre_v1_select_mitigation(void) { if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) spectre_v1_mitigation =3D SPECTRE_V1_MITIGATION_NONE; + + if (!should_mitigate_vuln(X86_BUG_SPECTRE_V1)) + spectre_v1_mitigation =3D SPECTRE_V1_MITIGATION_NONE; } =20 static void __init spectre_v1_apply_mitigation(void) --=20 2.34.1 From nobody Sun Nov 24 11:56:51 2024 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2048.outbound.protection.outlook.com [40.107.243.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A6EF216441 for ; Tue, 5 Nov 2024 21:55:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Disable SMT if cross-thread protection is desired and STIBP is not available. Signed-off-by: David Kaplan --- arch/x86/kernel/cpu/bugs.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index f63fa8a3b9ee..545151114947 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -1267,13 +1267,17 @@ static void __init retbleed_select_mitigation(void) } =20 if (retbleed_mitigation =3D=3D RETBLEED_MITIGATION_AUTO) { - if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD || - boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_HYGON) { - if (IS_ENABLED(CONFIG_MITIGATION_UNRET_ENTRY)) - retbleed_mitigation =3D RETBLEED_MITIGATION_UNRET; - else if (IS_ENABLED(CONFIG_MITIGATION_IBPB_ENTRY) && - boot_cpu_has(X86_FEATURE_IBPB)) - retbleed_mitigation =3D RETBLEED_MITIGATION_IBPB; + if (should_mitigate_vuln(X86_BUG_RETBLEED)) { + if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD || + boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_HYGON) { + if (IS_ENABLED(CONFIG_MITIGATION_UNRET_ENTRY)) + retbleed_mitigation =3D RETBLEED_MITIGATION_UNRET; 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Signed-off-by: David Kaplan --- arch/x86/kernel/cpu/bugs.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 545151114947..6479c800e973 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -1548,6 +1548,13 @@ spectre_v2_user_select_mitigation(void) spectre_v2_user_stibp =3D SPECTRE_V2_USER_STRICT; break; case SPECTRE_V2_USER_CMD_AUTO: + if (should_mitigate_vuln(X86_BUG_SPECTRE_V2_USER)) { + spectre_v2_user_ibpb =3D SPECTRE_V2_USER_PRCTL; + spectre_v2_user_stibp =3D SPECTRE_V2_USER_PRCTL; + } else { + return; + } + break; case SPECTRE_V2_USER_CMD_PRCTL: spectre_v2_user_ibpb =3D SPECTRE_V2_USER_PRCTL; spectre_v2_user_stibp =3D SPECTRE_V2_USER_PRCTL; --=20 2.34.1 From nobody Sun Nov 24 11:56:51 2024 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2086.outbound.protection.outlook.com [40.107.237.86]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 63060218D86 for ; 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Tue, 5 Nov 2024 15:55:36 -0600 From: David Kaplan To: Thomas Gleixner , Borislav Petkov , Peter Zijlstra , Josh Poimboeuf , Pawan Gupta , Ingo Molnar , Dave Hansen , , "H . Peter Anvin" CC: Subject: [PATCH v2 31/35] x86/bugs: Add attack vector controls for bhi Date: Tue, 5 Nov 2024 15:54:51 -0600 Message-ID: <20241105215455.359471-32-david.kaplan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105215455.359471-1-david.kaplan@amd.com> References: <20241105215455.359471-1-david.kaplan@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B370:EE_|SJ2PR12MB9237:EE_ X-MS-Office365-Filtering-Correlation-Id: f221b094-1d75-433a-401c-08dcfde4975c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|7416014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?d5pDjT4npJGdxUmOVXLXkQ4CGC1l/BlTOLKrSjGjwkVenv5eLxU45hJuFRXd?= =?us-ascii?Q?M0eq5iAay9t2cEpp/cqiWBko+P8v069BteNeYN+eQLS4nyvaN7YFMjp6IK6R?= =?us-ascii?Q?xi5V1ZGVMVxQDkkjcPqmzbhhiiOich2qLM0Q1RtQpCI7e3O5qHSHCaw3UWE9?= =?us-ascii?Q?8ppPnI3C9VBIjEeKKdr2aEpj6+apTPEbneecUN09ocikeR/rkb8GHsXQhGdt?= =?us-ascii?Q?xS+QwT1hpO6Fd7atLQHM0vwjo7vqtXFrahRw/2yVMT3+Gy5U477cmHuOY36U?= =?us-ascii?Q?7iO3pUt9uCz1t7q7EYOSFMqdveScO0qCRsHat3P50YvfQlWDjaeJIM1oEikx?= =?us-ascii?Q?MLcjslKMfvjM/jPNFfW8OlVAfKpN5e1LlY/T3HinzoF6i1IcqOUVRxgsz/Fw?= =?us-ascii?Q?iByiUjy7cicMtV65HApIvzK5fo6vGZ6i0rDytp96wHiGY5sNdh3SOFi0KpHb?= =?us-ascii?Q?G0TsNJUj2MbLR1v9XEUdASmnWomJ0g75wYU6S045+r/Ez1o7b0JLFXlxP61o?= =?us-ascii?Q?eMxk0C4+5l0P+aTZ+kzrb69OjdW93MWGmisGbG3OcpA6wtNXs7ek3EF4RMIW?= =?us-ascii?Q?QJriiFkeZyBFvOtIAAN4IPzHVH6AVr26vGjkE09JQzzImoq3yrmKSCXFHN/8?= =?us-ascii?Q?8dXI7vWxzcuHiwlsyRHOuPcKTMYgV4BTtSVBcITW3WRB2Hndp/yU4iYTXQvp?= =?us-ascii?Q?UcKI5NShj0iFlsQKMU4G981CWIwoyuPPIBs9jH36PcWQqT+xbrnPLoCHIhgv?= =?us-ascii?Q?nedWcKBGdPgiGyJK/SAuLvSpEthBpYd+0yGzOR+3LXlAT5UAhGGpgkqDsCen?= =?us-ascii?Q?nvkOTcCyrXkMSH2kgxrdaup1Wl9g8b85QD/YEetliJYPhHgsZv3Mb7GgUeBF?= =?us-ascii?Q?TeMvVWFdesNGWkpfHWykdoeSi/AeRT5ho1962dRBQFKAT7RU4jRmEpC73mCg?= =?us-ascii?Q?3qjTsft4XNRa5LjAx1KgjuvQ0HhN5n7yka/3J9/6CIjQl8p/8UH6gnlHsD92?= =?us-ascii?Q?QYkkAoO3TejViS7buIM2j3Drrj/Isp4Hd2qL8Gup/Hz6g3Fy5Qyprz1r3Q05?= =?us-ascii?Q?26KguqLGbGlFwgnpyWwB81OP+D+VpigAVykCQI5i29qtm6JL3CvwqOq/GIg4?= =?us-ascii?Q?yc5tWjb8hLr6RAZWmUrppjW2TXsMfeYGIFcT/B9HhjmW6lDlhkMz4016FJ2I?= =?us-ascii?Q?YQ8N2kEG2GAmY1o/J9zo53Tkph8cULpYm2xS/YEF09MXEo5fiL/3XiseAtXw?= =?us-ascii?Q?kzNigmo39VL5Nq71AGrjOgxe+thx5NlE/Dm9F2kyZuMjAgD/OQA8gPnCFccG?= =?us-ascii?Q?Uic8u/iw+NlsJZHuXxrPg3/a/xbww1wSz89QDi7vEvxmI7TZ99n6UB35ewUL?= =?us-ascii?Q?ybajcKsD9ob3gR9Wiy8LoFMGAQygDTX5ldM18w/MUaGv1d/rfw=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(7416014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 21:55:41.2762 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f221b094-1d75-433a-401c-08dcfde4975c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B370.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9237 Content-Type: text/plain; charset="utf-8" There are two BHI mitigations, one for SYSCALL and one for VMEXIT. Split these up so they can be selected individually based on attack vector. Signed-off-by: David Kaplan --- arch/x86/kernel/cpu/bugs.c | 38 ++++++++++++++++++++++++++------------ 1 file changed, 26 insertions(+), 12 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 6479c800e973..cc5248cdfe6f 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -1876,8 +1876,9 @@ static bool __init spec_ctrl_bhi_dis(void) enum bhi_mitigations { BHI_MITIGATION_OFF, BHI_MITIGATION_AUTO, - BHI_MITIGATION_ON, - BHI_MITIGATION_VMEXIT_ONLY, + BHI_MITIGATION_FULL, + BHI_MITIGATION_VMEXIT, + BHI_MITIGATION_SYSCALL }; =20 static enum bhi_mitigations bhi_mitigation __ro_after_init =3D @@ -1891,9 +1892,9 @@ static int __init spectre_bhi_parse_cmdline(char *str) if (!strcmp(str, "off")) bhi_mitigation =3D BHI_MITIGATION_OFF; else if (!strcmp(str, "on")) - bhi_mitigation =3D BHI_MITIGATION_ON; + bhi_mitigation =3D BHI_MITIGATION_FULL; else if (!strcmp(str, "vmexit")) - bhi_mitigation =3D BHI_MITIGATION_VMEXIT_ONLY; + bhi_mitigation =3D BHI_MITIGATION_VMEXIT; else pr_err("Ignoring unknown spectre_bhi option (%s)", str); =20 @@ -1909,8 +1910,17 @@ static void __init bhi_select_mitigation(void) if (bhi_mitigation =3D=3D BHI_MITIGATION_OFF) return; =20 - if (bhi_mitigation =3D=3D BHI_MITIGATION_AUTO) - bhi_mitigation =3D BHI_MITIGATION_ON; + if (bhi_mitigation =3D=3D BHI_MITIGATION_AUTO) { + if (cpu_mitigate_attack_vector(CPU_MITIGATE_USER_KERNEL)) { + if (cpu_mitigate_attack_vector(CPU_MITIGATE_GUEST_HOST)) + bhi_mitigation =3D BHI_MITIGATION_FULL; + else + bhi_mitigation =3D BHI_MITIGATION_SYSCALL; + } else if (cpu_mitigate_attack_vector(CPU_MITIGATE_GUEST_HOST)) + bhi_mitigation =3D BHI_MITIGATION_VMEXIT; + else + bhi_mitigation =3D BHI_MITIGATION_OFF; + } } =20 static void __init bhi_apply_mitigation(void) @@ -1933,15 +1943,19 @@ static void __init bhi_apply_mitigation(void) if (!IS_ENABLED(CONFIG_X86_64)) return; =20 - if (bhi_mitigation =3D=3D BHI_MITIGATION_VMEXIT_ONLY) { - pr_info("Spectre BHI mitigation: SW BHB clearing on VM exit only\n"); + /* Mitigate KVM if guest->host protection is desired */ + if (bhi_mitigation =3D=3D BHI_MITIGATION_FULL || + bhi_mitigation =3D=3D BHI_MITIGATION_VMEXIT) { setup_force_cpu_cap(X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT); - return; + pr_info("Spectre BHI mitigation: SW BHB clearing on VM exit\n"); } =20 - pr_info("Spectre BHI mitigation: SW BHB clearing on syscall and VM exit\n= "); - setup_force_cpu_cap(X86_FEATURE_CLEAR_BHB_LOOP); - setup_force_cpu_cap(X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT); + /* Mitigate syscalls if user->kernel protection is desired */ + if (bhi_mitigation =3D=3D BHI_MITIGATION_FULL || + bhi_mitigation =3D=3D BHI_MITIGATION_SYSCALL) { + setup_force_cpu_cap(X86_FEATURE_CLEAR_BHB_LOOP); + pr_info("Spectre BHI mitigation: SW BHB clearing on syscall\n"); + } } =20 static void __init spectre_v2_select_mitigation(void) --=20 2.34.1 From nobody Sun Nov 24 11:56:51 2024 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2075.outbound.protection.outlook.com [40.107.223.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1DD5E218334 for ; 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Tue, 5 Nov 2024 15:55:37 -0600 From: David Kaplan To: Thomas Gleixner , Borislav Petkov , Peter Zijlstra , Josh Poimboeuf , Pawan Gupta , Ingo Molnar , Dave Hansen , , "H . Peter Anvin" CC: Subject: [PATCH v2 32/35] x86/bugs: Add attack vector controls for spectre_v2 Date: Tue, 5 Nov 2024 15:54:52 -0600 Message-ID: <20241105215455.359471-33-david.kaplan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105215455.359471-1-david.kaplan@amd.com> References: <20241105215455.359471-1-david.kaplan@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B374:EE_|DS0PR12MB7769:EE_ X-MS-Office365-Filtering-Correlation-Id: d8f5ea38-2f9a-4ba5-6cba-08dcfde497b0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?hWYALAyGrFg3HqhwDWHGJrk1g0eAuj3X6m8aO4r9NMWaLBVMymhRQIex6I9X?= =?us-ascii?Q?3TRlSUF6K2A0PNZG/3EhwUynwTk4A8QlV0sfaUdOOaF2eMWRQGEmO1oKhOdb?= =?us-ascii?Q?sUCMAAm6it+en8XVHSj4Z9R+fryzyUkSWZlW1WF0+hCsPPl942BUtIYoVUUC?= =?us-ascii?Q?kFYVyF3vXeHti14fLo82jDRUsQFGkdXSF7+DscvzVPlvsJyvTUOswuq5Pf0M?= =?us-ascii?Q?qITTxBF/6kRB3tFIzKc2cMkGBTKbAJilpc1bpHFdPesF6UwhJDMOhYR4HXAG?= =?us-ascii?Q?cK6xVDTukTIq3AxRq7bDLrIlLzj3SseFH5UNaNPNF18jlPabfpC+bQtsyYee?= =?us-ascii?Q?tTEn5xWJQXDX9zi/etP+1Ixfs3rK0zORD7JP9VxCbndjdGMnQmSj3x/duGPY?= =?us-ascii?Q?czgU6nj3lOMXakP48Od5ddRXvgILN57u/NhasNktUJnhlO7a6fcl8KcPeEbz?= =?us-ascii?Q?Hm5DglR6XCE5tpS4ZHUwVBUhPvhvHIuDoMhBJGdiGRUVv+9w+w0vy9kd1VwW?= =?us-ascii?Q?6IAKYR5lvgDQEU0PCJXogyQyAWYXDkhBTlIxhPc+4YVslvi9mwI2QzpQyW6H?= =?us-ascii?Q?+R1huNFBTlolD35qBPTGkFfY3s1woBlCuf4mnKZJk1GxLb4nDWIU7qWSKx9A?= =?us-ascii?Q?gYIK1foDSGZ1Juqy7V3PZcAn+Vx4Xx4oReDtTyv46WIoc6MtCDVF4d61t3V6?= =?us-ascii?Q?4tnWXX+eFwlmXcila1tskI7SciUzncE4YbL6Bj4Q6uMJ50DGA6TDSE4v0ai9?= =?us-ascii?Q?m/CGg7nxdp5h0NePImK2iyFFOTjL9WK5PTOmBmy/GVuNFTzIXK9t+V4IGVSK?= =?us-ascii?Q?ejRsp07W2cB8mJPRnR9cHNwyJX77LVA7J02orUC9ZvoETeA5NqLXLBuAo5rY?= =?us-ascii?Q?N3Eqc3/VPXpAPZQ2RDkC1coZNsAStEEOqn+0qIeF5j0F1PIfPrusDhoU/H1j?= =?us-ascii?Q?l/Xg1J+0vOrDH8yOQtIrpkqbLJrzC3BZpmoT4tH/E4IdW7nqKuIsuUn1sFKn?= =?us-ascii?Q?f2lkYUmu3tHZOexuLCW0XmVANLercrnzrzxX5L1rNdWFM6xXSUZs9gqpn9q+?= =?us-ascii?Q?ysSY8KoYoHwW+3pbL3qo4YI6NBapOVXv/w889eokPE7cAsMVuK+FA9IsAhSt?= =?us-ascii?Q?5wctTIeZZTxTGKUFTeHN2xymbmfXBrxk0POb7ZWbsCmCWuvGbm8OBD3Zn7+u?= =?us-ascii?Q?uEqF7yruqW43MzD/ol+C3mxnfOhNskEnxeJyKQ8hDIW655TjeeCo3M20sWGg?= =?us-ascii?Q?jJeKt9MLEObrsS6Rwr7zhUo1Jkc2wR9wzxZXJ4IMZiKGNph2wXnTNtlnVNej?= =?us-ascii?Q?pCI6iwRKB9OxRb7+ChGEKSxN+4B/d0oZHK67x3ae2Fo1Mlf5KDMNqtun+twQ?= =?us-ascii?Q?2jPPgystvzDjLOU+gSY92HtViYbST62nNJMk94oqDsWrSEaNmA=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 21:55:41.8435 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d8f5ea38-2f9a-4ba5-6cba-08dcfde497b0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B374.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7769 Content-Type: text/plain; charset="utf-8" Use attack vector controls to determine if spectre_v2 mitigation is required. Signed-off-by: David Kaplan --- arch/x86/kernel/cpu/bugs.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index cc5248cdfe6f..4d71b4f969dc 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -1975,13 +1975,15 @@ static void __init spectre_v2_select_mitigation(voi= d) case SPECTRE_V2_CMD_NONE: return; =20 - case SPECTRE_V2_CMD_FORCE: case SPECTRE_V2_CMD_AUTO: + if (!should_mitigate_vuln(X86_BUG_SPECTRE_V2)) + break; + fallthrough; + case SPECTRE_V2_CMD_FORCE: if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { mode =3D SPECTRE_V2_EIBRS; break; } - mode =3D spectre_v2_select_retpoline(); break; =20 --=20 2.34.1 From nobody Sun Nov 24 11:56:51 2024 Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2043.outbound.protection.outlook.com [40.107.102.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C8F02185A4 for ; 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Peter Anvin" CC: Subject: [PATCH v2 33/35] x86/bugs: Add attack vector controls for l1tf Date: Tue, 5 Nov 2024 15:54:53 -0600 Message-ID: <20241105215455.359471-34-david.kaplan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105215455.359471-1-david.kaplan@amd.com> References: <20241105215455.359471-1-david.kaplan@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B370:EE_|IA1PR12MB7590:EE_ X-MS-Office365-Filtering-Correlation-Id: 52a9bee0-bb27-4fb4-879f-08dcfde49805 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?GNTWASc5UY/+9OZjWOSwQPR9lz6L4bp2HbL6LQBvfTv/vL5UJ4TiIIn78pqj?= =?us-ascii?Q?u5w9jnDOrxiWt13/HkVzjFymWC8rD45FISTsNdF8EdZoOHIOqDugSIcUsnxD?= =?us-ascii?Q?m5v2zp1X5EkVNCSm4bxj/ADgNVqQ697JU7w3zUfCRzq2t+/slgxYppU/HF1u?= =?us-ascii?Q?rewYpqq7G0LknHNrbQU9g8W+tD0z8G8+XU7wxQR1wiRYpyas6w+/WUHHP74e?= =?us-ascii?Q?pYILbmqAtxMZrvy1uw4OnErANRWpu/f62kosTlG2NHe3pryZJ0jFPqL5wn9y?= =?us-ascii?Q?x2rD2/Pa9peqB+g9AwR00PQlNQr2G30/Tux7/o53Nk6FfvkqAvfTI0kvirof?= =?us-ascii?Q?4xA/+f2pRsJvEZcCp7VqJKrKLUByJebDpClO99hu88dSid6lrrq0hjqN0cgV?= =?us-ascii?Q?j0L5xENjhfe+VFmXxr5v3Ktf3eoT2zTi93c9lCe0HGaWl13v+qtgzbz6y9oG?= =?us-ascii?Q?HYu2XleLEWyrYOapWX/lk/qSmQCww0+aqWbEeu6vq025pZa2alZN0GaB482z?= =?us-ascii?Q?LPOFyw+GQThnLyf76dklAHYqO79h4zyemD2hBoEzOITashTTVRiFb1g+23sq?= =?us-ascii?Q?hEst6uKz+g/0AB9Xi5ty4nrvm+8YcO0WPdi5iee8EEiiZk4tTrRhIYNPzvXc?= =?us-ascii?Q?1FFxPuczzjqMvzGY9om+rkaF8AqE+Ma58MLIlaSnAuPb2hrPjLGMWRtymXVh?= =?us-ascii?Q?LfQWOJEABHHgXhxSzmSUsZhcjJ8AAz/1zRTX2Hp3XELsZW/mzmqCJw2uO0J8?= =?us-ascii?Q?jcyBmQcMC5kmI7FPwmwk9d4pzKgq6LrwexXj0X7gBnmw0bkqOuP6J11z/6Ca?= =?us-ascii?Q?r2qaIxIGWfBjs7lHfMThPWO7icpoGUoNxIOEcyI2vvSnylbtKMujdEdTX0QD?= =?us-ascii?Q?O44AwbiMrvboNqSHDT7OhWnnTr4GlKpSQJD3MygpyHgj1oLM427kfKp6fMRI?= =?us-ascii?Q?IZGJO6hkngCAiiY6mwz3uyxt/s90HHEAOxoSFs3Bcxw4L5coFYboHYm0wsvD?= =?us-ascii?Q?spnMFRX3i1YwhTM3RNdUIoKtfxviiaR0+khgihOelXM+KHFRn5MvnsWzzotD?= =?us-ascii?Q?PUnVbmvZVamvY65xCTN4AvUU9zKTlY63euIqLql2ZQYRziQx23knINljGt0x?= =?us-ascii?Q?5luCdVgTtejKTr7KZJh2bNHSSGS/4Mu8mLclvNg7FZpcpEVQlu1zqnE/h+7h?= =?us-ascii?Q?FB86Xg29cdm+BLxE8SqDVGRKrNzcqkX+V5olxVTt+I1kvPCwgY6eB5ZulDp2?= =?us-ascii?Q?3kRHMPieY0BDs92aTZRv+cQcApEkva2ZbSktqJ2Nuvx5RUd3jWVkamKzza0H?= =?us-ascii?Q?HiGDBcfuomR91npwvdgeC5z9fnZetFg0HSy9xDaLuv+2oUN0Orr9qupxhgUg?= =?us-ascii?Q?26mAMKWouoA7FfbgDR/nurFyoMQ5qOePPJeA+iWOdrMC6b0g/w=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(7416014)(376014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 21:55:42.3856 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 52a9bee0-bb27-4fb4-879f-08dcfde49805 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B370.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7590 Content-Type: text/plain; charset="utf-8" Use attack vector controls to determine if l1tf mitigation is required. Disable SMT if cross-thread attack vector option is selected. Signed-off-by: David Kaplan --- arch/x86/kernel/cpu/bugs.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 4d71b4f969dc..81876a24c83c 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -2725,10 +2725,15 @@ static void __init l1tf_select_mitigation(void) } =20 if (l1tf_mitigation =3D=3D L1TF_MITIGATION_AUTO) { - if (cpu_mitigations_auto_nosmt()) - l1tf_mitigation =3D L1TF_MITIGATION_FLUSH_NOSMT; - else - l1tf_mitigation =3D L1TF_MITIGATION_FLUSH; + if (!should_mitigate_vuln(X86_BUG_L1TF)) + l1tf_mitigation =3D L1TF_MITIGATION_OFF; + else { + if (cpu_mitigations_auto_nosmt() || + cpu_mitigate_attack_vector(CPU_MITIGATE_CROSS_THREAD)) + l1tf_mitigation =3D L1TF_MITIGATION_FLUSH_NOSMT; + else + l1tf_mitigation =3D L1TF_MITIGATION_FLUSH; + } } =20 } --=20 2.34.1 From nobody Sun Nov 24 11:56:51 2024 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2064.outbound.protection.outlook.com [40.107.223.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5B59216450 for ; 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Peter Anvin" CC: Subject: [PATCH v2 34/35] x86/bugs: Add attack vector controls for srso Date: Tue, 5 Nov 2024 15:54:54 -0600 Message-ID: <20241105215455.359471-35-david.kaplan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105215455.359471-1-david.kaplan@amd.com> References: <20241105215455.359471-1-david.kaplan@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B374:EE_|PH8PR12MB6962:EE_ X-MS-Office365-Filtering-Correlation-Id: d17b6a6b-8081-46ab-18f9-08dcfde4981e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700013|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?rb5lo1Nf0i9rGqU9qcXMQ4O2PJQNqC4ZSENH5QflZnPh1RoSpEtF4i8ZdOyU?= =?us-ascii?Q?bJvbJgBlwY4CaNlvVeXPQKN/Rt4vp4CmCwBrl41KTs3gdNvqvfWND7a5JA2p?= =?us-ascii?Q?RUBiKmXOtVVClMoyEKpoCYOybLmo6q6S58fP0LGFx+eRf+HGU1Fc7umn4NkJ?= =?us-ascii?Q?vh+MvupkCWjxKN4mrfVnPnaDiM0d/9rzB9Ev+ZDGfg2bu6dvKiIs4GnbpUlp?= =?us-ascii?Q?X+O7Rui4rEivt7ZbN3lZ7BKDmXdvRlcL8MlspoD2WsvDW1iVHPC5h6z2z/5a?= =?us-ascii?Q?SIpMGfzafUtYDl50sQp9XYUXFoatDnNSW69DbIyqoBXV2z9l3LPlJxgFN4BM?= =?us-ascii?Q?3SboWjldl96QeTPaGZpNJUMY8Hnv0lS8h1QQWt5n9eGl9mylZbwZQ6OOPr2S?= =?us-ascii?Q?od5G7gHBr/KVYBFo7OIN+Qbei8vOdBgd31SJKt0P3AN7SHeWK+4wknzWC799?= =?us-ascii?Q?bclFh4TjO/rMZtFeW2mBbG75TRLi/GUIYEeGWpkCyTN3O52vAnPRfnOODsRr?= =?us-ascii?Q?akb0l2BzWdEwIPj84PO75OrPsLCnB5Ott7IQjgpK52eED3EPSixxakcDjc+X?= =?us-ascii?Q?kvzE8xuTsvbGgAamTmeQ8kzMU7DfGe/+ZkLTMQV8bEn7QJz86IrvyMgzFVez?= =?us-ascii?Q?rL/rgS/lWMeuQ1SB21T0+z4U4JHJJmadyDGijEF9R6X0sx2V5nfHq+iCW9UJ?= =?us-ascii?Q?edS0Y5mUoX140CERzg2UQGB9Y0zTmZ6Dv0kijottajY0oir8bpl9ttVwbteA?= =?us-ascii?Q?OKOJ4Za+zvImB76bbC4+fCy2+uc8vSbChZ7XqpoYKEHgb5zuL57s7tPhnsYO?= =?us-ascii?Q?9JoN1dEc08fHRUNbzBaTcJjqXUjI/TUQTeeuaeXNAZiKAAuq+b+hpq3mSand?= =?us-ascii?Q?RxseRcnRefaWyjulJKJN65uWVjjqGJs3bcQd8r3noOhmE+E9KNNpJ5MczElf?= =?us-ascii?Q?pnS43SwS/RqUM4arz4QWFa4mf8VZETEuld65KkuVOrZoxOlpDDHnn7IxugI2?= =?us-ascii?Q?gZJYFczKVpMiwq1dthClc15J/4Uli2QndSiQy8ZyBqZFiGt66NYeON2R0+El?= =?us-ascii?Q?WA3aL80WYuwV9j5uMndNKsxlcuk7YOOOZ06gEMZXPLwc7TfU5i4oZRIwuR0N?= =?us-ascii?Q?FdBbbV0Fcw/MsPs2tDxvjX4wD5CQC7sMzd58rQyY3KthFFY5kF23vMoehDDw?= =?us-ascii?Q?zYFTfD8bDgBilPOFOOyJejY/mg+4RwIey8V2hd4UbaePUFOO/YKIz9TEkFli?= =?us-ascii?Q?2DHwIZSR+wW3M2A6EmGXFCqEddNoJS4xWHDoC8XDZpEtSpq+8Ih+7HX/3gws?= =?us-ascii?Q?JZO4fGj1ZJF6Nu96gKToLGj2ZKhKjqOKsTBsJVuJre/FYkVvl/yclCqZ1JIc?= =?us-ascii?Q?q2DSB0Y2s9YgBNDNP5p/r9X8vp6oR8pHHl4JwQg20c6P3V834A=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(82310400026)(36860700013)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 21:55:42.5622 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d17b6a6b-8081-46ab-18f9-08dcfde4981e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B374.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6962 Content-Type: text/plain; charset="utf-8" Use attack vector controls to determine if srso mitigation is required. Signed-off-by: David Kaplan --- arch/x86/kernel/cpu/bugs.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 81876a24c83c..8552666c1b64 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -2868,8 +2868,14 @@ static void __init srso_select_mitigation(void) return; =20 /* Default mitigation */ - if (srso_mitigation =3D=3D SRSO_MITIGATION_AUTO) - srso_mitigation =3D SRSO_MITIGATION_SAFE_RET; + if (srso_mitigation =3D=3D SRSO_MITIGATION_AUTO) { + if (should_mitigate_vuln(X86_BUG_SRSO)) + srso_mitigation =3D SRSO_MITIGATION_SAFE_RET; + else { + srso_mitigation =3D SRSO_MITIGATION_NONE; + return; + } + } =20 if (has_microcode) { /* --=20 2.34.1 From nobody Sun Nov 24 11:56:51 2024 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2051.outbound.protection.outlook.com [40.107.94.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8F342170A7 for ; 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Tue, 5 Nov 2024 15:55:38 -0600 From: David Kaplan To: Thomas Gleixner , Borislav Petkov , Peter Zijlstra , Josh Poimboeuf , Pawan Gupta , Ingo Molnar , Dave Hansen , , "H . Peter Anvin" CC: Subject: [PATCH v2 35/35] x86/pti: Add attack vector controls for pti Date: Tue, 5 Nov 2024 15:54:55 -0600 Message-ID: <20241105215455.359471-36-david.kaplan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105215455.359471-1-david.kaplan@amd.com> References: <20241105215455.359471-1-david.kaplan@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B370:EE_|PH7PR12MB7843:EE_ X-MS-Office365-Filtering-Correlation-Id: fb1055d0-bdae-498e-5dad-08dcfde4983c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?FuHqkH8wTNHxD7gxTcPjsCeP9Y5Nt3OM3J2Zp/xvOUZDzYDbwPTInJreo0AL?= =?us-ascii?Q?AKDDdHJ1lbzv3258ZA6WBgw9n719FuIuUHb2jSjIY7fpEp+4ugqSOgxlUmhk?= =?us-ascii?Q?02FE2iro9hrSr/kHWtMXsoUhYJ483GnFk3vp6bG3loKnSX1g7guv324xnQ6q?= =?us-ascii?Q?blYaCraewIQ0TOuX4Npu3Hu5saEPeESRDpL42iKc/2P70jU6kWe2PIe1EIBe?= =?us-ascii?Q?lfyvM43Eyxw3XiB51GK+CE4TbbvPu482ahjSGkWYoMtfstjtwgs+6L+HdkM3?= =?us-ascii?Q?5xKJsYptBk59oobelOpeFlA2Ll8ibluqKiNM6gnMCNGdggYiFL1P9Ki9lq0c?= =?us-ascii?Q?DuPMzfNajZkTWcNIuwZxoSTA48m3y4bZV9t/4ouCL3rY7Hlbo5Azb+vz0tWw?= =?us-ascii?Q?QdnFvUW0dUHA2GplAT0wdSGrpXwSCykrOJsvSGUTD2UguBvHVoqR2zmO7Gc0?= =?us-ascii?Q?Gl7oSP2ZmFVeA/5DQ7nP3rVSP0+6QcJndObta1H4wtd/qrJXj27NXOqj7PVg?= =?us-ascii?Q?Ww34+PPVux10d19uby3CwSY3DEDiCp0iqCeHq+ESc+J1bDhyNVkSU3cxkr/e?= =?us-ascii?Q?DInNc76owZIxmnJ+4FOYeIoId95de9vkTxOwFBcCtwraGwexXzoyVWEtjyy0?= =?us-ascii?Q?/fasg8Ie2pZLmmdLtYuKh8uUZSbXkteqfj5biNd0NDz3xjbs3EJpr9YvYfV/?= =?us-ascii?Q?e3Ed/lFD6m7nCJcwQ3y9hyS3kJGBGbBVDZoWdR0vrPioJGXfMbrUOfgAWHe3?= =?us-ascii?Q?TVGJelbOsWA7QuqJVhvnwpUd2FrVGvFOzPz12PO+KqQ8ojEQSXaIp9dr7njb?= =?us-ascii?Q?Sy2O7qiwLYhluSHffEK3T8CNxWhtUkdqp+rvCZzEimwCkZebDnMQicftTXaV?= =?us-ascii?Q?RcEsv9Vg2Z0IjLzHXNp7ePaGlXkV5LLvnkKxIrQDzv7ke9XojHCNeW3iyQn8?= =?us-ascii?Q?2jNVr+P6HM+907NDgNGSZ//SDJfcOY3unNjvBaE4RfbIvJ+8csGq2sZHb6Eq?= =?us-ascii?Q?9Zzwarmz3qVd/TykaYxNEOZ+gPFBgKqGf49GCpk2qrnlHl4yneUttaVPkqNj?= =?us-ascii?Q?w/B74Nrivh40Qin48PN/71Px2dzvfPZIx0BR1W6T9DXbkXzFhZHNaYqShVOs?= =?us-ascii?Q?jp0wEk2uDRuIR58CKcl8+3mrJ3CY/XXZpiZKeVpvtwUibarhnJQrYGZX5RDO?= =?us-ascii?Q?ok1/0xo9PJewoJ/Ln7J1K00VsLqDtxEA46vE/UfX3C9JI4jPAIubrJBUx4hS?= =?us-ascii?Q?gZzf5GzUEC0ckPeYAjn5tpfrJZ1+YiGjWXzM4vE6jfWEk8OJbrdZwoCzpQZJ?= =?us-ascii?Q?o+KTfjp3X6midGnJEj0SZBep2m0i/pTAM3+vIoVNezVx6rV9SJriVYRP9p3W?= =?us-ascii?Q?Igjb/5/XLhExpTonnGJTIVBELAJTL7Ns1OBsnz4SEOvnS8jg4g=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 21:55:42.7450 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fb1055d0-bdae-498e-5dad-08dcfde4983c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B370.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7843 Content-Type: text/plain; charset="utf-8" Disable PTI mitigation if user->kernel attack vector mitigations are disabled. Signed-off-by: David Kaplan --- arch/x86/mm/pti.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/mm/pti.c b/arch/x86/mm/pti.c index 851ec8f1363a..9e1ed3df04e8 100644 --- a/arch/x86/mm/pti.c +++ b/arch/x86/mm/pti.c @@ -94,7 +94,8 @@ void __init pti_check_boottime_disable(void) if (pti_mode =3D=3D PTI_FORCE_ON) pti_print_if_secure("force enabled on command line."); =20 - if (pti_mode =3D=3D PTI_AUTO && !boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) + if (pti_mode =3D=3D PTI_AUTO && (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN) = || + !cpu_mitigate_attack_vector(CPU_MITIGATE_USER_KERNEL))) return; =20 setup_force_cpu_cap(X86_FEATURE_PTI); --=20 2.34.1