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(unknown [10.28.34.196]) by maili.marvell.com (Postfix) with ESMTP id 474795C68E3; Tue, 5 Nov 2024 04:56:28 -0800 (PST) From: Linu Cherian To: , , , CC: , , , , , , , Linu Cherian , Simon Horman Subject: [PATCH v5 net-next 1/3] octeontx2-af: Refactor few NPC mcam APIs Date: Tue, 5 Nov 2024 18:26:18 +0530 Message-ID: <20241105125620.2114301-2-lcherian@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105125620.2114301-1-lcherian@marvell.com> References: <20241105125620.2114301-1-lcherian@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: UADgHH6YheXbStJvpWTHbCXiV9UvaXUM X-Proofpoint-ORIG-GUID: UADgHH6YheXbStJvpWTHbCXiV9UvaXUM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 Content-Type: text/plain; charset="utf-8" Introduce lowlevel variant of rvu_mcam_remove/add_counter_from/to_rule for better code reuse, which assumes necessary locks are taken at higher level. These low level functions would be used for implementing default rule counter APIs in the subsequent patch. Signed-off-by: Linu Cherian Reviewed-by: Simon Horman --- Changelog from v4: No changes here. .../net/ethernet/marvell/octeontx2/af/rvu.h | 6 +- .../ethernet/marvell/octeontx2/af/rvu_npc.c | 89 ++++++++++++++++--- .../marvell/octeontx2/af/rvu_npc_fs.c | 36 ++------ 3 files changed, 92 insertions(+), 39 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/= ethernet/marvell/octeontx2/af/rvu.h index 5016ba82e142..d92a5f47a476 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h @@ -960,7 +960,11 @@ void rvu_npc_disable_default_entries(struct rvu *rvu, = u16 pcifunc, int nixlf); void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixl= f); void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixl= f, int group, int alg_idx, int mcam_index); - +void __rvu_mcam_remove_counter_from_rule(struct rvu *rvu, u16 pcifunc, + struct rvu_npc_mcam_rule *rule); +void __rvu_mcam_add_counter_to_rule(struct rvu *rvu, u16 pcifunc, + struct rvu_npc_mcam_rule *rule, + struct npc_install_flow_rsp *rsp); void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc, int blkaddr, int *alloc_cnt, int *enable_cnt); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_npc.c index 97722ce8c4cb..c4ef1e83cc46 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c @@ -2975,9 +2975,9 @@ int rvu_mbox_handler_npc_mcam_shift_entry(struct rvu = *rvu, return rc; } =20 -int rvu_mbox_handler_npc_mcam_alloc_counter(struct rvu *rvu, - struct npc_mcam_alloc_counter_req *req, - struct npc_mcam_alloc_counter_rsp *rsp) +static int __npc_mcam_alloc_counter(struct rvu *rvu, + struct npc_mcam_alloc_counter_req *req, + struct npc_mcam_alloc_counter_rsp *rsp) { struct npc_mcam *mcam =3D &rvu->hw->mcam; u16 pcifunc =3D req->hdr.pcifunc; @@ -2998,11 +2998,9 @@ int rvu_mbox_handler_npc_mcam_alloc_counter(struct r= vu *rvu, if (!req->contig && req->count > NPC_MAX_NONCONTIG_COUNTERS) return NPC_MCAM_INVALID_REQ; =20 - mutex_lock(&mcam->lock); =20 /* Check if unused counters are available or not */ if (!rvu_rsrc_free_count(&mcam->counters)) { - mutex_unlock(&mcam->lock); return NPC_MCAM_ALLOC_FAILED; } =20 @@ -3035,12 +3033,27 @@ int rvu_mbox_handler_npc_mcam_alloc_counter(struct = rvu *rvu, } } =20 - mutex_unlock(&mcam->lock); return 0; } =20 -int rvu_mbox_handler_npc_mcam_free_counter(struct rvu *rvu, - struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp) +int rvu_mbox_handler_npc_mcam_alloc_counter(struct rvu *rvu, + struct npc_mcam_alloc_counter_req *req, + struct npc_mcam_alloc_counter_rsp *rsp) +{ + struct npc_mcam *mcam =3D &rvu->hw->mcam; + int err; + + mutex_lock(&mcam->lock); + + err =3D __npc_mcam_alloc_counter(rvu, req, rsp); + + mutex_unlock(&mcam->lock); + return err; +} + +static int __npc_mcam_free_counter(struct rvu *rvu, + struct npc_mcam_oper_counter_req *req, + struct msg_rsp *rsp) { struct npc_mcam *mcam =3D &rvu->hw->mcam; u16 index, entry =3D 0; @@ -3050,10 +3063,8 @@ int rvu_mbox_handler_npc_mcam_free_counter(struct rv= u *rvu, if (blkaddr < 0) return NPC_MCAM_INVALID_REQ; =20 - mutex_lock(&mcam->lock); err =3D npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr); if (err) { - mutex_unlock(&mcam->lock); return err; } =20 @@ -3077,10 +3088,66 @@ int rvu_mbox_handler_npc_mcam_free_counter(struct r= vu *rvu, index, req->cntr); } =20 - mutex_unlock(&mcam->lock); return 0; } =20 +int rvu_mbox_handler_npc_mcam_free_counter(struct rvu *rvu, + struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp) +{ + struct npc_mcam *mcam =3D &rvu->hw->mcam; + int err; + + mutex_lock(&mcam->lock); + + err =3D __npc_mcam_free_counter(rvu, req, rsp); + + mutex_unlock(&mcam->lock); + + return err; +} + +void __rvu_mcam_remove_counter_from_rule(struct rvu *rvu, u16 pcifunc, + struct rvu_npc_mcam_rule *rule) +{ + struct npc_mcam_oper_counter_req free_req =3D { 0 }; + struct msg_rsp free_rsp; + + if (!rule->has_cntr) + return; + + free_req.hdr.pcifunc =3D pcifunc; + free_req.cntr =3D rule->cntr; + + __npc_mcam_free_counter(rvu, &free_req, &free_rsp); + rule->has_cntr =3D false; +} + +void __rvu_mcam_add_counter_to_rule(struct rvu *rvu, u16 pcifunc, + struct rvu_npc_mcam_rule *rule, + struct npc_install_flow_rsp *rsp) +{ + struct npc_mcam_alloc_counter_req cntr_req =3D { 0 }; + struct npc_mcam_alloc_counter_rsp cntr_rsp =3D { 0 }; + int err; + + cntr_req.hdr.pcifunc =3D pcifunc; + cntr_req.contig =3D true; + cntr_req.count =3D 1; + + /* we try to allocate a counter to track the stats of this + * rule. If counter could not be allocated then proceed + * without counter because counters are limited than entries. + */ + err =3D __npc_mcam_alloc_counter(rvu, &cntr_req, &cntr_rsp); + if (!err && cntr_rsp.count) { + rule->cntr =3D cntr_rsp.cntr; + rule->has_cntr =3D true; + rsp->counter =3D rule->cntr; + } else { + rsp->counter =3D err; + } +} + int rvu_mbox_handler_npc_mcam_unmap_counter(struct rvu *rvu, struct npc_mcam_unmap_counter_req *req, struct msg_rsp *rsp) { diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c b/drive= rs/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c index 150635de2bd5..7a1c18b1486d 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c @@ -1081,44 +1081,26 @@ static void rvu_mcam_add_rule(struct npc_mcam *mcam, static void rvu_mcam_remove_counter_from_rule(struct rvu *rvu, u16 pcifunc, struct rvu_npc_mcam_rule *rule) { - struct npc_mcam_oper_counter_req free_req =3D { 0 }; - struct msg_rsp free_rsp; + struct npc_mcam *mcam =3D &rvu->hw->mcam; =20 - if (!rule->has_cntr) - return; + mutex_lock(&mcam->lock); =20 - free_req.hdr.pcifunc =3D pcifunc; - free_req.cntr =3D rule->cntr; + __rvu_mcam_remove_counter_from_rule(rvu, pcifunc, rule); =20 - rvu_mbox_handler_npc_mcam_free_counter(rvu, &free_req, &free_rsp); - rule->has_cntr =3D false; + mutex_unlock(&mcam->lock); } =20 static void rvu_mcam_add_counter_to_rule(struct rvu *rvu, u16 pcifunc, struct rvu_npc_mcam_rule *rule, struct npc_install_flow_rsp *rsp) { - struct npc_mcam_alloc_counter_req cntr_req =3D { 0 }; - struct npc_mcam_alloc_counter_rsp cntr_rsp =3D { 0 }; - int err; + struct npc_mcam *mcam =3D &rvu->hw->mcam; =20 - cntr_req.hdr.pcifunc =3D pcifunc; - cntr_req.contig =3D true; - cntr_req.count =3D 1; + mutex_lock(&mcam->lock); =20 - /* we try to allocate a counter to track the stats of this - * rule. If counter could not be allocated then proceed - * without counter because counters are limited than entries. - */ - err =3D rvu_mbox_handler_npc_mcam_alloc_counter(rvu, &cntr_req, - &cntr_rsp); - if (!err && cntr_rsp.count) { - rule->cntr =3D cntr_rsp.cntr; - rule->has_cntr =3D true; - rsp->counter =3D rule->cntr; - } else { - rsp->counter =3D err; - } + __rvu_mcam_add_counter_to_rule(rvu, pcifunc, rule, rsp); + + mutex_unlock(&mcam->lock); } =20 static int npc_mcast_update_action_index(struct rvu *rvu, struct npc_insta= ll_flow_req *req, --=20 2.34.1 From nobody Sun Nov 24 12:30:57 2024 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2634B1D5AA1; Tue, 5 Nov 2024 12:56:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.156.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730811410; cv=none; b=ZkMW7yZFCLXUrcCGL7N/kCcjL8A3FH2GIwKJ1vUp5Df4zDtVDC8TOHywF3VYDxyeQiwVmR04VcIA8SnkMhkj7wt7nPUSORylFlJcuvtfjAQf/9cjUk5qRzZASSHKa+BLhLBYTfWlfLHxckUzgkcRBN+lDp0TAUT7pynnTIq/cDk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730811410; c=relaxed/simple; bh=T1ONFHU+RvAAlRiquTJy6I70F87fppQc7Luk8M6p3ZQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ZMXImfjO2TqHicx+K/ZnKX2SJ834lh2qKabAEY0IO5/X0nQFinkYBmBwsyNDOBg0zc0fy9Onu7OxBdaGYEf98QBrzbqbgM/oSVNNHiTgno6/ZX7rBRRhDfSEABmxHrWtt7JoOzYlOvDlmpCCNzo7JxO99XRj2Qf9VmwZEBOAzIc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=QkcuM572; arc=none smtp.client-ip=67.231.156.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="QkcuM572" Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4A57Ufsx023824; Tue, 5 Nov 2024 04:56:37 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=A ChNZyKddo0CvoixqhVuK1l0fBpA1VPDc8S3vS530wo=; b=QkcuM572bQuJDbPX7 T7v4IY7yzwM+QV/kPY9Nlz7/uTa8aN0DDezcHzXK+ezC+WNv8nlCpFR3WJh8McdY AE9yZ0g9ZIwtwCpif64X55q5B1SvAxe1dA4Bt+THm8YcYRh47QL7SORDMSXatsqZ OR8tNQDPTEo52OAk7pIDDoIizNgGQ8VMeIhpJ+JnaMlGz4NVLyvQRgiW5770D9bw pZCDx70AmpU2OEY7gn8utEo5ntLDlGovkefDo3wbSoojnQZdoU0Gmb8bF0y9jRVR MyyX4xMZm/sAXuLKuTr2mjGKA7OghFdXn62kfXfRSFlY+D8lwdCV6Hy4wKxdt+mc vWxVg== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 42qf1e8kcr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 05 Nov 2024 04:56:37 -0800 (PST) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 5 Nov 2024 04:56:35 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 5 Nov 2024 04:56:35 -0800 Received: from virtx40.. (unknown [10.28.34.196]) by maili.marvell.com (Postfix) with ESMTP id 5EA6B5C68E3; Tue, 5 Nov 2024 04:56:32 -0800 (PST) From: Linu Cherian To: , , , CC: , , , , , , , Linu Cherian Subject: [PATCH v5 net-next 2/3] octeontx2-af: Knobs for NPC default rule counters Date: Tue, 5 Nov 2024 18:26:19 +0530 Message-ID: <20241105125620.2114301-3-lcherian@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105125620.2114301-1-lcherian@marvell.com> References: <20241105125620.2114301-1-lcherian@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: E5MsFUr0gmHumoib0omjezhclWBR1zv_ X-Proofpoint-ORIG-GUID: E5MsFUr0gmHumoib0omjezhclWBR1zv_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 Content-Type: text/plain; charset="utf-8" Add devlink knobs to enable/disable counters on NPC default rule entries. Sample command to enable default rule counters: devlink dev param set name npc_def_rule_cntr value true cmode runtime Sample command to read the counter: cat /sys/kernel/debug/cn10k/npc/mcam_rules Signed-off-by: Linu Cherian --- Changelog from v4: Few code cleanups in npc_config_cntr_default_entries, - Minor code refactoring to make it explicit that counter reset is done only for newly enabled counters - Removed redundant init for rsp variable - Removed braces that are not required - "Reviewed-by" from Simon not added due to above changes. .../net/ethernet/marvell/octeontx2/af/rvu.h | 2 + .../marvell/octeontx2/af/rvu_devlink.c | 32 ++++++++++++++ .../ethernet/marvell/octeontx2/af/rvu_npc.c | 43 +++++++++++++++++++ 3 files changed, 77 insertions(+) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/= ethernet/marvell/octeontx2/af/rvu.h index d92a5f47a476..e8c6a6fe9bd5 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h @@ -525,6 +525,7 @@ struct rvu { struct mutex alias_lock; /* Serialize bar2 alias access */ int vfs; /* Number of VFs attached to RVU */ u16 vf_devid; /* VF devices id */ + bool def_rule_cntr_en; int nix_blkaddr[MAX_NIX_BLKS]; =20 /* Mbox */ @@ -989,6 +990,7 @@ void npc_set_mcam_action(struct rvu *rvu, struct npc_mc= am *mcam, void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr, u16 src, struct mcam_entry *entry, u8 *intf, u8 *ena); +int npc_config_cntr_default_entries(struct rvu *rvu, bool enable); bool is_cgx_config_permitted(struct rvu *rvu, u16 pcifunc); bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature); u32 rvu_cgx_get_fifolen(struct rvu *rvu); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c b/driv= ers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c index 7498ab429963..9c26e19a860b 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c @@ -1238,6 +1238,7 @@ enum rvu_af_dl_param_id { RVU_AF_DEVLINK_PARAM_ID_DWRR_MTU, RVU_AF_DEVLINK_PARAM_ID_NPC_MCAM_ZONE_PERCENT, RVU_AF_DEVLINK_PARAM_ID_NPC_EXACT_FEATURE_DISABLE, + RVU_AF_DEVLINK_PARAM_ID_NPC_DEF_RULE_CNTR_ENABLE, RVU_AF_DEVLINK_PARAM_ID_NIX_MAXLF, }; =20 @@ -1358,6 +1359,32 @@ static int rvu_af_dl_npc_mcam_high_zone_percent_vali= date(struct devlink *devlink return 0; } =20 +static int rvu_af_dl_npc_def_rule_cntr_get(struct devlink *devlink, u32 id, + struct devlink_param_gset_ctx *ctx) +{ + struct rvu_devlink *rvu_dl =3D devlink_priv(devlink); + struct rvu *rvu =3D rvu_dl->rvu; + + ctx->val.vbool =3D rvu->def_rule_cntr_en; + + return 0; +} + +static int rvu_af_dl_npc_def_rule_cntr_set(struct devlink *devlink, u32 id, + struct devlink_param_gset_ctx *ctx, + struct netlink_ext_ack *extack) +{ + struct rvu_devlink *rvu_dl =3D devlink_priv(devlink); + struct rvu *rvu =3D rvu_dl->rvu; + int err; + + err =3D npc_config_cntr_default_entries(rvu, ctx->val.vbool); + if (!err) + rvu->def_rule_cntr_en =3D ctx->val.vbool; + + return err; +} + static int rvu_af_dl_nix_maxlf_get(struct devlink *devlink, u32 id, struct devlink_param_gset_ctx *ctx) { @@ -1444,6 +1471,11 @@ static const struct devlink_param rvu_af_dl_params[]= =3D { rvu_af_dl_npc_mcam_high_zone_percent_get, rvu_af_dl_npc_mcam_high_zone_percent_set, rvu_af_dl_npc_mcam_high_zone_percent_validate), + DEVLINK_PARAM_DRIVER(RVU_AF_DEVLINK_PARAM_ID_NPC_DEF_RULE_CNTR_ENABLE, + "npc_def_rule_cntr", DEVLINK_PARAM_TYPE_BOOL, + BIT(DEVLINK_PARAM_CMODE_RUNTIME), + rvu_af_dl_npc_def_rule_cntr_get, + rvu_af_dl_npc_def_rule_cntr_set, NULL), DEVLINK_PARAM_DRIVER(RVU_AF_DEVLINK_PARAM_ID_NIX_MAXLF, "nix_maxlf", DEVLINK_PARAM_TYPE_U16, BIT(DEVLINK_PARAM_CMODE_RUNTIME), diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_npc.c index c4ef1e83cc46..821fe242f821 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c @@ -2691,6 +2691,49 @@ void npc_mcam_rsrcs_reserve(struct rvu *rvu, int blk= addr, int entry_idx) npc_mcam_set_bit(mcam, entry_idx); } =20 +int npc_config_cntr_default_entries(struct rvu *rvu, bool enable) +{ + struct npc_mcam *mcam =3D &rvu->hw->mcam; + struct npc_install_flow_rsp rsp; + struct rvu_npc_mcam_rule *rule; + int blkaddr; + + blkaddr =3D rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); + if (blkaddr < 0) + return -EINVAL; + + mutex_lock(&mcam->lock); + list_for_each_entry(rule, &mcam->mcam_rules, list) { + if (!is_mcam_entry_enabled(rvu, mcam, blkaddr, rule->entry)) + continue; + if (!rule->default_rule) + continue; + if (enable && !rule->has_cntr) { /* Alloc and map new counter */ + __rvu_mcam_add_counter_to_rule(rvu, rule->owner, + rule, &rsp); + if (rsp.counter < 0) { + dev_err(rvu->dev, + "%s: Failed to allocate cntr for default rule (err=3D%d)\n", + __func__, rsp.counter); + break; + } + npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr, + rule->entry, rsp.counter); + /* Reset counter before use */ + rvu_write64(rvu, blkaddr, + NPC_AF_MATCH_STATX(rule->cntr), 0x0); + } + + /* Free and unmap counter */ + if (!enable && rule->has_cntr) + __rvu_mcam_remove_counter_from_rule(rvu, rule->owner, + rule); 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(unknown [10.28.34.196]) by maili.marvell.com (Postfix) with ESMTP id 385225C68E3; Tue, 5 Nov 2024 04:56:35 -0800 (PST) From: Linu Cherian To: , , , CC: , , , , , , , Linu Cherian Subject: [PATCH v5 net-next 3/3] devlink: Add documentation for OcteonTx2 AF Date: Tue, 5 Nov 2024 18:26:20 +0530 Message-ID: <20241105125620.2114301-4-lcherian@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105125620.2114301-1-lcherian@marvell.com> References: <20241105125620.2114301-1-lcherian@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: _wQHqliY693OPhGsuFYl6gdBNJnrjpzP X-Proofpoint-ORIG-GUID: _wQHqliY693OPhGsuFYl6gdBNJnrjpzP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.687,Hydra:6.0.235,FMLib:17.0.607.475 definitions=2020-10-13_15,2020-10-13_02,2020-04-07_01 Content-Type: text/plain; charset="utf-8" Add documentation for the following devlink params - npc_mcam_high_zone_percent - npc_def_rule_cntr - nix_maxlf Signed-off-by: Linu Cherian --- Changelog from v4: - Describe the behaviour when counters are not sufficient to meet all the enabled rules - Add definition for default rules - Add sample commands to read counters for default rules - "Reviewed-by" from Simon not added due to above changes. .../networking/devlink/octeontx2.rst | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/Documentation/networking/devlink/octeontx2.rst b/Documentation= /networking/devlink/octeontx2.rst index d33a90dd44bf..84206537aedb 100644 --- a/Documentation/networking/devlink/octeontx2.rst +++ b/Documentation/networking/devlink/octeontx2.rst @@ -40,6 +40,27 @@ The ``octeontx2 AF`` driver implements the following dri= ver-specific parameters. - runtime - Use to set the quantum which hardware uses for scheduling among tra= nsmit queues. Hardware uses weighted DWRR algorithm to schedule among all transmi= t queues. + * - ``npc_mcam_high_zone_percent`` + - u8 + - runtime + - Use to set the number of high priority zone entries in NPC MCAM tha= t can be allocated + by a user, out of the three priority zone categories high, mid and = low. + * - ``npc_def_rule_cntr`` + - bool + - runtime + - Use to enable or disable hit counters for the default rules in NPC = MCAM. + Its not guaranteed that counters gets enabled and mapped to all the= default rules, + since the counters are scarce and driver follows a best effort appr= oach. + The default rule serves as the primary packet steering rule for a s= pecific PF or VF, + based on its DMAC address which is installed by AF driver as part o= f its initialization. + Sample command to read hit counters for default rule from debugfs i= s as follows, + cat /sys/kernel/debug/cn10k/npc/mcam_rules + * - ``nix_maxlf`` + - u16 + - runtime + - Use to set the maximum number of LFs in NIX hardware block. This wo= uld be useful + to increase the availability of default resources allocated to enab= led LFs like + MCAM entries for example. =20 The ``octeontx2 PF`` driver implements the following driver-specific param= eters. =20 --=20 2.34.1