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MCMB subunit TPDM has the same number and usage of registers as CMB subunit TPDM. MCMB subunit can be enabled for data collection by writing 1 to the first bit of CMB_CR register. The difference is that MCMB subunit TPDM needs to select the lane and enable it in using it. Signed-off-by: Tao Zhang Signed-off-by: Mao Jinlong --- drivers/hwtracing/coresight/coresight-tpda.c | 7 ++-- drivers/hwtracing/coresight/coresight-tpdm.c | 44 +++++++++++++++++--- drivers/hwtracing/coresight/coresight-tpdm.h | 27 ++++++------ 3 files changed, 57 insertions(+), 21 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtraci= ng/coresight/coresight-tpda.c index bfca103f9f84..4b61b9840740 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights res= erved. */ =20 #include @@ -68,11 +68,12 @@ static int tpdm_read_element_size(struct tpda_drvdata *= drvdata, int rc =3D -EINVAL; struct tpdm_drvdata *tpdm_data =3D dev_get_drvdata(csdev->dev.parent); =20 - if (tpdm_has_dsb_dataset(tpdm_data)) { + if (tpdm_data->dsb) { rc =3D fwnode_property_read_u32(dev_fwnode(csdev->dev.parent), "qcom,dsb-element-bits", &drvdata->dsb_esize); } - if (tpdm_has_cmb_dataset(tpdm_data)) { + + if (tpdm_data->cmb) { rc =3D fwnode_property_read_u32(dev_fwnode(csdev->dev.parent), "qcom,cmb-element-bits", &drvdata->cmb_esize); } diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtraci= ng/coresight/coresight-tpdm.c index b7d99e91ab84..0529858586c1 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights res= erved. */ =20 #include @@ -21,6 +21,21 @@ =20 DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm"); =20 +static bool tpdm_has_dsb_dataset(struct tpdm_drvdata *drvdata) +{ + return (drvdata->datasets & TPDM_PIDR0_DS_DSB); +} + +static bool tpdm_has_cmb_dataset(struct tpdm_drvdata *drvdata) +{ + return (drvdata->datasets & TPDM_PIDR0_DS_CMB); +} + +static bool tpdm_has_mcmb_dataset(struct tpdm_drvdata *drvdata) +{ + return (drvdata->datasets & TPDM_PIDR0_DS_MCMB); +} + /* Read dataset array member with the index number */ static ssize_t tpdm_simple_dataset_show(struct device *dev, struct device_attribute *attr, @@ -198,7 +213,7 @@ static umode_t tpdm_cmb_is_visible(struct kobject *kobj, struct device *dev =3D kobj_to_dev(kobj); struct tpdm_drvdata *drvdata =3D dev_get_drvdata(dev->parent); =20 - if (drvdata && tpdm_has_cmb_dataset(drvdata)) + if (drvdata && drvdata->cmb) return attr->mode; =20 return 0; @@ -246,8 +261,10 @@ static void tpdm_reset_datasets(struct tpdm_drvdata *d= rvdata) drvdata->dsb->trig_type =3D false; } =20 - if (drvdata->cmb) + if (drvdata->cmb) { memset(drvdata->cmb, 0, sizeof(struct cmb_dataset)); + drvdata->cmb->trig_ts =3D true; + } } =20 static void set_dsb_mode(struct tpdm_drvdata *drvdata, u32 *val) @@ -388,7 +405,7 @@ static void tpdm_enable_cmb(struct tpdm_drvdata *drvdat= a) { u32 val, i; =20 - if (!tpdm_has_cmb_dataset(drvdata)) + if (!drvdata->cmb) return; =20 /* Configure pattern registers */ @@ -415,6 +432,19 @@ static void tpdm_enable_cmb(struct tpdm_drvdata *drvda= ta) val |=3D TPDM_CMB_CR_MODE; else val &=3D ~TPDM_CMB_CR_MODE; + + if (tpdm_has_mcmb_dataset(drvdata)) { + val &=3D ~TPDM_CMB_CR_XTRIG_LNSEL; + /* Set the lane participates in tghe output pattern */ + val |=3D FIELD_PREP(TPDM_CMB_CR_XTRIG_LNSEL, + drvdata->cmb->mcmb.trig_lane); + + /* Set the enablement of the lane */ + val &=3D ~TPDM_CMB_CR_E_LN; + val |=3D FIELD_PREP(TPDM_CMB_CR_E_LN, + drvdata->cmb->mcmb.lane_select); + } + /* Set the enable bit of CMB control register to 1 */ val |=3D TPDM_CMB_CR_ENA; writel_relaxed(val, drvdata->base + TPDM_CMB_CR); @@ -480,7 +510,7 @@ static void tpdm_disable_cmb(struct tpdm_drvdata *drvda= ta) { u32 val; =20 - if (!tpdm_has_cmb_dataset(drvdata)) + if (!drvdata->cmb) return; =20 val =3D readl_relaxed(drvdata->base + TPDM_CMB_CR); @@ -542,12 +572,14 @@ static int tpdm_datasets_setup(struct tpdm_drvdata *d= rvdata) if (!drvdata->dsb) return -ENOMEM; } - if (tpdm_has_cmb_dataset(drvdata) && (!drvdata->cmb)) { + if ((tpdm_has_cmb_dataset(drvdata) || tpdm_has_mcmb_dataset(drvdata)) + && (!drvdata->cmb)) { drvdata->cmb =3D devm_kzalloc(drvdata->dev, sizeof(*drvdata->cmb), GFP_KERNEL); if (!drvdata->cmb) return -ENOMEM; } + tpdm_reset_datasets(drvdata); =20 return 0; diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtraci= ng/coresight/coresight-tpdm.h index e08d212642e3..fd9153b92335 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights res= erved. */ =20 #ifndef _CORESIGHT_CORESIGHT_TPDM_H @@ -9,7 +9,7 @@ /* The max number of the datasets that TPDM supports */ #define TPDM_DATASETS 7 =20 -/* CMB Subunit Registers */ +/* CMB/MCMB Subunit Registers */ #define TPDM_CMB_CR (0xA00) /* CMB subunit timestamp insertion enable register */ #define TPDM_CMB_TIER (0xA04) @@ -34,6 +34,10 @@ #define TPDM_CMB_TIER_XTRIG_TSENAB BIT(1) /* For timestamp fo all trace */ #define TPDM_CMB_TIER_TS_ALL BIT(2) +/* MCMB trigger lane select */ +#define TPDM_CMB_CR_XTRIG_LNSEL GENMASK(20, 18) +/* MCMB lane enablement */ +#define TPDM_CMB_CR_E_LN GENMASK(17, 10) =20 /* Patten register number */ #define TPDM_CMB_MAX_PATT 2 @@ -112,11 +116,13 @@ * PERIPHIDR0[0] : Fix to 1 if ImplDef subunit present, else 0 * PERIPHIDR0[1] : Fix to 1 if DSB subunit present, else 0 * PERIPHIDR0[2] : Fix to 1 if CMB subunit present, else 0 + * PERIPHIDR0[6] : Fix to 1 if MCMB subunit present, else 0 */ =20 #define TPDM_PIDR0_DS_IMPDEF BIT(0) #define TPDM_PIDR0_DS_DSB BIT(1) #define TPDM_PIDR0_DS_CMB BIT(2) +#define TPDM_PIDR0_DS_MCMB BIT(6) =20 #define TPDM_DSB_MAX_LINES 256 /* MAX number of EDCR registers */ @@ -256,6 +262,9 @@ struct dsb_dataset { * @patt_ts: Indicates if pattern match for timestamp is enabled. * @trig_ts: Indicates if CTI trigger for timestamp is enabled. * @ts_all: Indicates if timestamp is enabled for all packets. + * struct mcmb_dataset + * @mcmb_trig_lane: Save data for trigger lane + * @mcmb_lane_select: Save data for lane enablement */ struct cmb_dataset { u32 trace_mode; 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charset="utf-8" From: Tao Zhang TPDM MCMB subunits supports up to 8 lanes CMB. For MCMB configurations, the field "XTRIG_LNSEL" in CMB_CR register selects which lane participates in the output pattern mach cross trigger mechanism governed by the M_CMB_DXPR and M_CMB_XPMR regisers. Signed-off-by: Tao Zhang Signed-off-by: Mao Jinlong --- .../testing/sysfs-bus-coresight-devices-tpdm | 8 +++ drivers/hwtracing/coresight/coresight-tpdm.c | 51 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 3 ++ 3 files changed, 62 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/D= ocumentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index bf710ea6e0ef..e833edfec79e 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -257,3 +257,11 @@ Contact: Jinlong Mao (QUIC) = , Tao Zhang (QUIC) /mcmb_trig_lane +Date: Nov 2024 +KernelVersion 6.13 +Contact: Tao Zhang (QUIC) +Description: + (RW) Set/Get which lane participates in the output pattern + match cross trigger mechanism for the MCMB subunit TPDM. diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtraci= ng/coresight/coresight-tpdm.c index 0529858586c1..2e4dc86b03ea 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -252,6 +252,18 @@ static umode_t tpdm_cmb_msr_is_visible(struct kobject = *kobj, return 0; } =20 +static umode_t tpdm_mcmb_is_visible(struct kobject *kobj, + struct attribute *attr, int n) +{ + struct device *dev =3D kobj_to_dev(kobj); + struct tpdm_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + + if (drvdata && tpdm_has_mcmb_dataset(drvdata)) + return attr->mode; + + return 0; +} + static void tpdm_reset_datasets(struct tpdm_drvdata *drvdata) { if (tpdm_has_dsb_dataset(drvdata)) { @@ -1023,6 +1035,34 @@ static ssize_t cmb_trig_ts_store(struct device *dev, } static DEVICE_ATTR_RW(cmb_trig_ts); =20 +static ssize_t mcmb_trig_lane_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", + (unsigned int)drvdata->cmb->mcmb.trig_lane); +} + +static ssize_t mcmb_trig_lane_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + unsigned long val; + + if ((kstrtoul(buf, 0, &val)) || (val >=3D TPDM_MCMB_MAX_LANES)) + return -EINVAL; + + guard(spinlock)(&drvdata->spinlock); + drvdata->cmb->mcmb.trig_lane =3D val; + + return size; +} +static DEVICE_ATTR_RW(mcmb_trig_lane); + static struct attribute *tpdm_dsb_edge_attrs[] =3D { &dev_attr_ctrl_idx.attr, &dev_attr_ctrl_val.attr, @@ -1185,6 +1225,11 @@ static struct attribute *tpdm_cmb_msr_attrs[] =3D { NULL, }; =20 +static struct attribute *tpdm_mcmb_attrs[] =3D { + &dev_attr_mcmb_trig_lane.attr, + NULL, +}; + static struct attribute *tpdm_dsb_attrs[] =3D { &dev_attr_dsb_mode.attr, &dev_attr_dsb_trig_ts.attr, @@ -1251,6 +1296,11 @@ static struct attribute_group tpdm_cmb_msr_grp =3D { .name =3D "cmb_msr", }; =20 +static struct attribute_group tpdm_mcmb_attr_grp =3D { + .attrs =3D tpdm_mcmb_attrs, + .is_visible =3D tpdm_mcmb_is_visible, +}; + static const struct attribute_group *tpdm_attr_grps[] =3D { &tpdm_attr_grp, &tpdm_dsb_attr_grp, @@ -1262,6 +1312,7 @@ static const struct attribute_group *tpdm_attr_grps[]= =3D { &tpdm_cmb_trig_patt_grp, &tpdm_cmb_patt_grp, &tpdm_cmb_msr_grp, + &tpdm_mcmb_attr_grp, NULL, }; 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charset="utf-8" From: Tao Zhang Add the sysfs file to set/get the enablement of the lane. For MCMB configurations, the field "E_LN" in CMB_CR register is the individual lane enables. MCMB lane N is enabled for trace generation when M_CMB_CR.E=3D1 and M_CMB_CR.E_LN[N]=3D1. For lanes that are not implemented on a given MCMB configuration, the corresponding bits of this field read as 0 and ignore writes. Signed-off-by: Tao Zhang Signed-off-by: Mao Jinlong --- .../testing/sysfs-bus-coresight-devices-tpdm | 7 +++++ drivers/hwtracing/coresight/coresight-tpdm.c | 29 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpdm.h | 3 ++ 3 files changed, 39 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/D= ocumentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index e833edfec79e..fcc2a8f1f17f 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -265,3 +265,10 @@ Contact: Tao Zhang (QUIC) Description: (RW) Set/Get which lane participates in the output pattern match cross trigger mechanism for the MCMB subunit TPDM. + +What: /sys/bus/coresight/devices//mcmb_lanes_select +Date: Nov 2024 +KernelVersion 6.13 +Contact: Tao Zhang (QUIC) +Description: + (RW) Set/Get the enablement of the individual lane. diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtraci= ng/coresight/coresight-tpdm.c index 2e4dc86b03ea..bb0d6505ec9f 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -1063,6 +1063,34 @@ static ssize_t mcmb_trig_lane_store(struct device *d= ev, } static DEVICE_ATTR_RW(mcmb_trig_lane); =20 +static ssize_t mcmb_lanes_select_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpdm_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "%u\n", + (unsigned int)drvdata->cmb->mcmb.lane_select); +} + +static ssize_t mcmb_lanes_select_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpdm_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + unsigned long val; + + if (kstrtoul(buf, 0, &val) || (val & ~TPDM_MCMB_E_LN_MASK)) + return -EINVAL; + + guard(spinlock)(&drvdata->spinlock); + drvdata->cmb->mcmb.lane_select =3D val & TPDM_MCMB_E_LN_MASK; + + return size; +} +static DEVICE_ATTR_RW(mcmb_lanes_select); + static struct attribute *tpdm_dsb_edge_attrs[] =3D { &dev_attr_ctrl_idx.attr, &dev_attr_ctrl_val.attr, @@ -1227,6 +1255,7 @@ static struct attribute *tpdm_cmb_msr_attrs[] =3D { =20 static struct attribute *tpdm_mcmb_attrs[] =3D { &dev_attr_mcmb_trig_lane.attr, + &dev_attr_mcmb_lanes_select.attr, NULL, }; =20 diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtraci= ng/coresight/coresight-tpdm.h index aa9746b2e77f..a80f3d680995 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -48,6 +48,9 @@ /* MAX lanes in the output pattern for MCMB configurations*/ #define TPDM_MCMB_MAX_LANES 8 =20 +/* Filter bit 0~7 from the value for CR_E_LN */ +#define TPDM_MCMB_E_LN_MASK GENMASK(7, 0) + /* DSB Subunit Registers */ #define TPDM_DSB_CR (0x780) #define TPDM_DSB_TIER (0x784) --=20 2.17.1