From nobody Sun Nov 24 12:39:25 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26B741D27AD; Tue, 5 Nov 2024 10:22:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730802170; cv=none; b=sYwj7kKuWpNdLEg9KJyAkxUjB544t2Erv3WQ7EO40HyeS4Gw0NQnO8IekgktSdYY9kSSICzSpixi4GxY7/esEdOr14e48boBca+8dcw0dN7z9U2BNrbUotO/jcG4rogt5lle7uxY3jdcd81aIzWid3SdyqkxLxto36Kwa2rKvnA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730802170; c=relaxed/simple; bh=ajLTnWap11hSowj5013aFC1Fy6aMYyofhLuaY6gPxZw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kPxeOJXUE3GMKwBusTRIt+rTkcyIrgwq7fhgRTFU69q5tUykQtQ6jKLI61D2mQbp/4uwFVHXil9VkEsMv1KB0OECRgNrraR3iOrH2V/iQf2/IvkR5qOWPy1mb5pEuJiHf8qYEz/pEImdorgwKj2mW1RR9FkpfrM/almJTVtoBlg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=UuqVasVf; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="UuqVasVf" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4A57ug2l003803; Tue, 5 Nov 2024 10:22:46 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= Kck3P5Bet2uVWgnfBXq4aXViMO74GqXyxo1CK95Zd6U=; b=UuqVasVfHE5gwRkr 6Y64AlNhR9md7IC2aM/w1IMdla9Vr22AbgqQp71T+KYfRtI7mgPMUyrelSIodYhX jWUGaHTX4xWlt6LXemG7OBGVYCDGulCTnVkPwCEd+Nt8sYmOpJJAU6HKlZ44KGaH RSPDepfqgLnmrHA2DNBVOapw/PUZbsTXRlHpBNwDIun47mPzRh1Ql8balwdqFa+Y neiAUddDymjcFHNiEhT1Zav3btG0YBCt8DtS2c335Wzibz3mATlbqHs8SbpgbgbM IsaWqKgJspIkl0E4zBjZMIqzIBH1LH+P8K/emONpAFarGS1lLCnOpz8vv+RGBqei 54A8ag== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42qfdx0d16-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 05 Nov 2024 10:22:46 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4A5AMjwC016701 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 5 Nov 2024 10:22:46 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 5 Nov 2024 02:22:42 -0800 From: Varadarajan Narayanan To: , , , , , , , CC: Varadarajan Narayanan Subject: [PATCH v2 1/3] dt-bindings: cache: qcom,llcc: Add IPQ5424 compatible Date: Tue, 5 Nov 2024 15:52:08 +0530 Message-ID: <20241105102210.510025-2-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105102210.510025-1-quic_varada@quicinc.com> References: <20241105102210.510025-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ctg8REFnlIcaA8U9mFBw8MH58vaXT7Mf X-Proofpoint-ORIG-GUID: ctg8REFnlIcaA8U9mFBw8MH58vaXT7Mf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 priorityscore=1501 impostorscore=0 mlxscore=0 bulkscore=0 spamscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411050078 Content-Type: text/plain; charset="utf-8" Document the Last Level Cache Controller on IPQ5424. The 'broadcast' register space is present only in chipsets that have multiple instances of LLCC IP. Since IPQ5424 has only one instance, both the LLCC and LLCC_BROADCAST points to the same register space. Hence, allow only '1' reg & reg-names entry for IPQ5424. Reviewed-by: Rob Herring (Arm) Signed-off-by: Varadarajan Narayanan --- v2: Add Reviewed-by --- .../devicetree/bindings/cache/qcom,llcc.yaml | 20 +++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Docum= entation/devicetree/bindings/cache/qcom,llcc.yaml index ee7edc6f60e2..1a0021676e59 100644 --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml @@ -21,6 +21,7 @@ properties: compatible: enum: - qcom,qdu1000-llcc + - qcom,ipq5424-llcc - qcom,sa8775p-llcc - qcom,sc7180-llcc - qcom,sc7280-llcc @@ -38,11 +39,11 @@ properties: - qcom,x1e80100-llcc =20 reg: - minItems: 2 + minItems: 1 maxItems: 10 =20 reg-names: - minItems: 2 + minItems: 1 maxItems: 10 =20 interrupts: @@ -62,6 +63,21 @@ required: - reg-names =20 allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq5424-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + reg-names: + items: + - const: llcc0_base + - if: properties: compatible: --=20 2.34.1 From nobody Sun Nov 24 12:39:25 2024 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3D541D2F7E; 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charset="utf-8" The 'broadcast' register space is present only in chipsets that have multiple instances of LLCC IP. Since IPQ5424 has only one instance, both the LLCC and LLCC_BROADCAST points to the same register space. Signed-off-by: Varadarajan Narayanan --- v2: Use 'true/false' instead of '1/0' for boolean variables. Add 'no_broadcast_register' to qcom_llcc_config structure to identify SoC without LLCC_BROADCAST register space instead of using 'num_banks'. --- drivers/soc/qcom/llcc-qcom.c | 58 ++++++++++++++++++++++++++++++++++-- 1 file changed, 56 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index a470285f54a8..f34d65fdd185 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -140,6 +140,7 @@ struct qcom_llcc_config { bool need_llcc_cfg; bool no_edac; bool irq_configured; + bool no_broadcast_register; }; =20 struct qcom_sct_config { @@ -152,6 +153,38 @@ enum llcc_reg_offset { LLCC_COMMON_STATUS0, }; =20 +static const struct llcc_slice_config ipq5424_data[] =3D { + { + .usecase_id =3D LLCC_CPUSS, + .slice_id =3D 1, + .max_cap =3D 768, + .priority =3D 1, + .bonus_ways =3D 0xFFFF, + .retain_on_pc =3D true, + .activate_on_init =3D true, + .write_scid_cacheable_en =3D true, + .stale_en =3D true, + .stale_cap_en =3D true, + .alloc_oneway_en =3D true, + .ovcap_en =3D true, + .ovcap_prio =3D true, + .vict_prio =3D true, + }, + { + .usecase_id =3D LLCC_VIDSC0, + .slice_id =3D 2, + .max_cap =3D 256, + .priority =3D 2, + .fixed_size =3D true, + .bonus_ways =3D 0xF000, + .retain_on_pc =3D true, + .activate_on_init =3D true, + .write_scid_cacheable_en =3D true, + .stale_en =3D true, + .stale_cap_en =3D true, + }, +}; + static const struct llcc_slice_config sa8775p_data[] =3D { { .usecase_id =3D LLCC_CPUSS, @@ -2677,6 +2710,17 @@ static const struct qcom_llcc_config qdu1000_cfg[] = =3D { }, }; =20 +static const struct qcom_llcc_config ipq5424_cfg[] =3D { + { + .sct_data =3D ipq5424_data, + .size =3D ARRAY_SIZE(ipq5424_data), + .need_llcc_cfg =3D true, + .reg_offset =3D llcc_v2_1_reg_offset, + .edac_reg_offset =3D &llcc_v2_1_edac_reg_offset, + .no_broadcast_register =3D true, + }, +}; + static const struct qcom_llcc_config sa8775p_cfg[] =3D { { .sct_data =3D sa8775p_data, @@ -2834,6 +2878,11 @@ static const struct qcom_sct_config qdu1000_cfgs =3D= { .num_config =3D ARRAY_SIZE(qdu1000_cfg), }; =20 +static const struct qcom_sct_config ipq5424_cfgs =3D { + .llcc_config =3D ipq5424_cfg, + .num_config =3D ARRAY_SIZE(ipq5424_cfg), +}; + static const struct qcom_sct_config sa8775p_cfgs =3D { .llcc_config =3D sa8775p_cfg, .num_config =3D ARRAY_SIZE(sa8775p_cfg), @@ -3412,8 +3461,12 @@ static int qcom_llcc_probe(struct platform_device *p= dev) =20 drv_data->bcast_regmap =3D qcom_llcc_init_mmio(pdev, i, "llcc_broadcast_b= ase"); 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charset="utf-8" Add a DT node for Last level cache (aka. system cache) controller which provides control over the last level cache present on IPQ5424 SoCs. Reviewed-by: Konrad Dybcio Signed-off-by: Varadarajan Narayanan --- v2: Add Reviewed-by --- arch/arm64/boot/dts/qcom/ipq5424.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qc= om/ipq5424.dtsi index 76af0d87e9a8..497df93acf47 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -137,6 +137,13 @@ soc@0 { #size-cells =3D <2>; ranges =3D <0 0 0 0 0x10 0>; =20 + system-cache-controller@800000 { + compatible =3D "qcom,ipq5424-llcc"; + reg =3D <0 0x00800000 0 0x200000>; + reg-names =3D "llcc0_base"; + interrupts =3D ; + }; + tlmm: pinctrl@1000000 { compatible =3D "qcom,ipq5424-tlmm"; reg =3D <0 0x01000000 0 0x300000>; --=20 2.34.1