From nobody Sun Nov 24 14:23:05 2024 Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96FA21FDFAD; Tue, 5 Nov 2024 06:42:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=85.214.62.61 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730788949; cv=none; b=gb18Rr+SLMBkIsiE1/RFiQ0Q7TpSCkBkmu4IzLMCfGb4Ydv53pZp+zhgP7XJR86REGBr21ZA06Y8vLcLs9uFvzKZWg/aLkzQBYe0MCchnpBZPGcuC8KMNSAUTZ8vXeYQCr1vKkJo3CMK/B+mfzBTu/+VWDMWpWInbwdKprFJgbI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730788949; c=relaxed/simple; bh=/N/tBcY5Ap6L0FyIz7W+ZKJeqrPEXK9I9dM7w+tRjIw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=pZ8Ysazm6AE0SdCIZa65/Pq301sN1jhiTnqkXyrjdqB3W00aBebfj6/2n69dSThUkDKXHNZxVt6OePeYu9Naz1s6z5TkTWEyFbaE5zkITBF+kpUoSgzj21ukGmDr62zyOpzyfTx4i5Hg/cmO7DGwv6chnJY7Am9wU0l/XBnXA0s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=denx.de; spf=pass smtp.mailfrom=denx.de; dkim=pass (2048-bit key) header.d=denx.de header.i=@denx.de header.b=UOE/pQF0; arc=none smtp.client-ip=85.214.62.61 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=denx.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=denx.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=denx.de header.i=@denx.de header.b="UOE/pQF0" Received: from localhost.localdomain (87-97-112-21.pool.digikabel.hu [87.97.112.21]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: hs@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 2220A88EDE; Tue, 5 Nov 2024 07:42:18 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1730788939; bh=xhHi+o5Mgt4vE62+EN185nyzLfwnIHMnzNtTNTjPFfc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UOE/pQF0fr5eZRf5Fq8jpI55EHP9/kiZYNJ6x2vS3lBp6H2XraRZYjcYoB2qOvkNf 2XZyu5qM9kkh2F8azEF9d+uN2OKHtf84dy+9Z1WD6fE7r1BBaCqHgpBTVLvMznCgqb bMcGN6hhju2KbVsTppnJFqTAeuwBW+2WgTdFNh9ryRstSGD9mFxLcfHsusC/cdAghY omCTM/n5ZPFBbBeEstXsqCYRUIBKc9jBXsnaqap9X9T5kOhxcHWbzOsQcA/P4on/O2 MtB4gOEAkSBVVIQ5Nv6rFM+GYEdwacy47RVV37nAs6azQNJgszCNMGv1jbz4jCuBaX E/OeHq1CS+NNg== From: Heiko Schocher To: linux-kernel@vger.kernel.org Cc: Heiko Schocher , Krzysztof Kozlowski , Alexander Stein , Conor Dooley , Frieder Schrempf , Gregor Herburger , Hiago De Franco , Hugo Villeneuve , Joao Paulo Goncalves , Krzysztof Kozlowski , Krzysztof Kozlowski , Mathieu Othacehe , Max Merchel , Michael Walle , Peng Fan , Rob Herring , Shawn Guo , Tim Harvey , devicetree@vger.kernel.org Subject: [PATCH v3 1/3] dt-bindings: arm: fsl: Add ABB SoM and carrier Date: Tue, 5 Nov 2024 07:42:04 +0100 Message-Id: <20241105064206.43626-2-hs@denx.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20241105064206.43626-1-hs@denx.de> References: <20241105064206.43626-1-hs@denx.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Content-Type: text/plain; charset="utf-8" add support for the i.MX8MP based SoM and carrier from ABB. Signed-off-by: Heiko Schocher Reviewed-by: Krzysztof Kozlowski --- Changes in v3: added Reviewed-by from Krzysztof Changes in v2: reworked the compatible strings for ABB imx8mp based boards called dtb checks, no errors for this patch Documentation/devicetree/bindings/arm/fsl.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index b39a7e031177..b933788f756b 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1090,6 +1090,15 @@ properties: - toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT= Modules - const: fsl,imx8mp =20 + - description: ABB Boards with i.MX8M Plus Modules from ADLink + items: + - enum: + - abb,imx8mp-aristanetos3-adpismarc # i.MX8MP ABB SoM on PI = SMARC Board + - abb,imx8mp-aristanetos3-helios # i.MX8MP ABB SoM on hel= ios Board + - abb,imx8mp-aristanetos3-proton2s # i.MX8MP ABB SoM on pro= ton2s Board + - const: abb,imx8mp-aristanetos3-som # i.MX8MP ABB SoM + - const: fsl,imx8mp + - description: Avnet (MSC Branded) Boards with SM2S i.MX8M Plus Modu= les items: - const: avnet,sm2s-imx8mp-14N0600E-ep1 # SM2S-IMX8PLUS-14N0600E= on SM2-MB-EP1 Carrier Board --=20 2.20.1 From nobody Sun Nov 24 14:23:05 2024 Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 372D81C2324; Tue, 5 Nov 2024 06:42:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=85.214.62.61 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730788945; cv=none; b=EljPVVPqEo2dz964eEvxKI5i07gvbc88Xf9juzNTTlW6p6qBwvfA+7p7sWt6w+Bahl/IEGUn1yZqM5LL541TteVIQL+Oyl0CkehqH9EdGXpPsUmaUez0VXTq8Qe/OcLYaHbaPkWUsUZo6ivSkPSB62aAP7E5TUsTBHHrWbezbBM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730788945; c=relaxed/simple; bh=gT6TGfPLEEgNb9a1UcM6k2+GwOFFX10p6GUhgD4xCO0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Q9LzqkR+7lFyp9feUqyhzuRzcbVaHrWU214sF4MaKfXO63j78XdWXr+l6V/RrlTFIrnuytqk37fq4I/PIDZTYHb/Y9wa7rPwU6Jx9aSvJgv0AZ0j3iEJlTz2Pm2J2BDBE/J3lhNP8EZHcLyCOgRugGzQZ9mdGWNA65weCzuO9rk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=denx.de; spf=pass smtp.mailfrom=denx.de; dkim=pass (2048-bit key) header.d=denx.de header.i=@denx.de header.b=Y88NL3vR; arc=none smtp.client-ip=85.214.62.61 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=denx.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=denx.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=denx.de header.i=@denx.de header.b="Y88NL3vR" Received: from localhost.localdomain (87-97-112-21.pool.digikabel.hu [87.97.112.21]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: hs@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 0090488EDD; Tue, 5 Nov 2024 07:42:20 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1730788941; bh=CTUrXm3qAhjs4mU9JLhzVL58+lVPixfrNT8nOp3fw/4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Y88NL3vRuqtA0/QL3iRvwjCKuwKTHUbv/euDTraH7ScQqRoNbYSfUHSJIuq41kEQB U5k5SczfydRsvzxs2GBAg63HgFmJDoyslLyAMJeIy5pmoBag3MWuZsjRuWeu9hNNdc R/wSHgmrCCQKcgTjkE7R63mGd9YbNHMed8kN5kRJc9EFkSykO+yMurFiWCWmnWX2ab YLkaN+ZTsXwgGlPh9rIUQl5PIQtkQvCUQ8LgTg6wTjVCtcI5wlRRni4wH4Rxf4S5Nw 9kYgfGVhtyKlAzoDuO9ZSbO1bzMpk7IFTvugSOIpm2CMDBFgO0iRxNcTwTdta1RUtF g26yd2XFkhgPQ== From: Heiko Schocher To: linux-kernel@vger.kernel.org Cc: Heiko Schocher , Conor Dooley , Krzysztof Kozlowski , Krzysztof Kozlowski , Linus Walleij , Neil Armstrong , Rob Herring , devicetree@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [PATCH v3 2/3] dt-bindings: pinctrl: sx150xq: allow gpio line naming Date: Tue, 5 Nov 2024 07:42:05 +0100 Message-Id: <20241105064206.43626-3-hs@denx.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20241105064206.43626-1-hs@denx.de> References: <20241105064206.43626-1-hs@denx.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Content-Type: text/plain; charset="utf-8" Adding gpio-line-names property works fine for this device node, but dtb check drops warning: 'gpio-line-names' does not match any of the regexes: '-cfg$', 'pinctrl-[0-9= ]+' from schema $id: http://devicetree.org/schemas/pinctrl/semtech,sx1501q.yaml# Allow to add property gpio-line-names for this devices. Signed-off-by: Heiko Schocher Reviewed-by: Krzysztof Kozlowski --- checkpatch shows WARNING: Prefer a maximum 75 chars per line (possible unwrapped commit desc= ription?) 'gpio-line-names' does not match any of the regexes: '-cfg$', 'pinctrl-[0-9= ]+' Ignored, as it is a make output, which helps to understand the reason for adding this patch. Changes in v3: - worked in comments from Krzysztof gpio-line-names should match the actual number of gpios of the device. Changes in v2: patch dt-bindings: pinctrl: sx150xq: allow gpio line naming new in v2 .../bindings/pinctrl/semtech,sx1501q.yaml | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/semtech,sx1501q.yaml= b/Documentation/devicetree/bindings/pinctrl/semtech,sx1501q.yaml index 4214d7311f6b..39d7dad3313b 100644 --- a/Documentation/devicetree/bindings/pinctrl/semtech,sx1501q.yaml +++ b/Documentation/devicetree/bindings/pinctrl/semtech,sx1501q.yaml @@ -26,6 +26,10 @@ properties: reg: maxItems: 1 =20 + gpio-line-names: + minItems: 5 + maxItems: 17 + interrupts: maxItems: 1 =20 @@ -87,6 +91,45 @@ required: =20 allOf: - $ref: pinctrl.yaml# + - if: + properties: + compatible: + contains: + enum: + - semtech,sx1501q + - semtech,sx1504q + - semtech,sx1507q + then: + properties: + gpio-line-names: + minItems: 5 + maxItems: 5 + - if: + properties: + compatible: + contains: + enum: + - semtech,sx1502q + - semtech,sx1505q + - semtech,sx1508q + then: + properties: + gpio-line-names: + minItems: 9 + maxItems: 9 + - if: + properties: + compatible: + contains: + enum: + - semtech,sx1503q + - semtech,sx1506q + - semtech,sx1509q + then: + properties: + gpio-line-names: + minItems: 17 + maxItems: 17 - if: not: properties: --=20 2.20.1 From nobody Sun Nov 24 14:23:05 2024 Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59F221FDFA5; Tue, 5 Nov 2024 06:42:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=85.214.62.61 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730788948; cv=none; b=r6CO0LqQzAhE8TsBPX8YtJ+S5A/GEAUWKmQcvrDnyfNF9fxVk7iicHaMHMBYcNuqml0kKCDp5Z2MaV8U1g7DSDzeAmLOQPwPT2MxrvZkpLvNlvSeNw7oWd5jCqrOB79o6QD6nzd/OAcoVaaAEaJt11HxrsYiKCMTwjxxUG7bl5Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730788948; c=relaxed/simple; bh=JzNYfpx91fdrhZnxCx/keXN+h0DAIbi/iAIomEpFVYc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fwMUtpR2TA9VzUYBevlN59zVE1WKnhHEvPstf+vFoyh5fENkPrdnygJLeomwz3EoUvwGAL1fZVA3datCk+RzckKE3d7aIrV58wQE2WmnPly1MSBUXWQi1z7WkjeNLns4zAvWWPnL2CfbyHr5jgNo3SAkhuZk5fM1xBzQ9aVlAQY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=denx.de; spf=pass smtp.mailfrom=denx.de; dkim=pass (2048-bit key) header.d=denx.de header.i=@denx.de header.b=QcpkbVZw; arc=none smtp.client-ip=85.214.62.61 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=denx.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=denx.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=denx.de header.i=@denx.de header.b="QcpkbVZw" Received: from localhost.localdomain (87-97-112-21.pool.digikabel.hu [87.97.112.21]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: hs@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id B1E9788CF1; Tue, 5 Nov 2024 07:42:22 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1730788943; bh=d+YunzJvv97z5mtITnsxzjkzaCKCEKEVwb+2bLEaz3k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QcpkbVZwzZwbJQj5KCZgR3ZCpxBZ0E+//Y2SaYaSYT0eIKi5AHVeve9lRAY8Hn5Md 9HsxtETw3es9+YITkNo3X+y8hkNpi5SxqGKIwsWF1sdDc3vK46DCCBz/cyQJ49SVt3 XFw7M1YCGS9/Vj0fZ3qtvilscTH/4GCD67+lnxaPfO4VpB1Nh3VEpBIchhVzt5zcOB XJGGqqCvOzI0FxI5XMIJU12oPvWV2kl5JttR2f/Oh7TCxGAEaXmEiMkpXtdzU3SudO ICGZycHzKfRNlK1JqkbHKOUDHbVMKu4QEAXwW2ukAVVENENLlaL5tLbUp9QrlfnDQG ZQFm9MvFNnxOg== From: Heiko Schocher To: linux-kernel@vger.kernel.org Cc: Heiko Schocher , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 3/3] arm64: dts: imx8mp: add aristainetos3 board support Date: Tue, 5 Nov 2024 07:42:06 +0100 Message-Id: <20241105064206.43626-4-hs@denx.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20241105064206.43626-1-hs@denx.de> References: <20241105064206.43626-1-hs@denx.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Content-Type: text/plain; charset="utf-8" Add support for the i.MX8MP based aristainetos3 boards from ABB. The board uses a ABB specific SoM from ADLink, based on NXP i.MX8MP SoC. The SoM is used on 3 different carrier boards, with small differences. Signed-off-by: Heiko Schocher --- Changes in v3: - added comments from Shawn Guo removed unneeded new lines sort nodes, properties alphabetical rename pcie0-refclk -> clock-xxx used GPIO_ACTIVE_HIGH instead of 0 - added comments from Fabio Estevam instead of settting each brightness-level in brightness-levels add num-interpolated-steps - changes from me fix gpio-line-names for semtech gpio controller in imx8mp-aristainetos3-proton2s.dts as patch "dt-bindings: pinctrl: sx150xq: allow gpio line naming" of this series adds the dtb checks for them and 17 entries needed now. Changes in v2: - worked in comments from Krzysztof - removed unneeded dtbos and build now dtbs for each carrierboard. - removed user spidev entries, as I do not know the real spi devices connected to... - call dtb check targets as described in cover letter and fixed warnings except warnings see below: not fixed dtb check warnings - pci (warning pops up for each new dtb from this patch, but also for a lot of other boards, which are already in tree) imx8mp-aristainetos3-adpismarc.dtb: pcie-ep@33800000: reg: [[864026624, 419= 4304], [402653184, 134217728]] is too short from schema $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-e= p.yaml# imx8mp-aristainetos3-adpismarc.dtb: pcie-ep@33800000: reg-names: ['dbi', 'a= ddr_space'] is too short from schema $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-e= p.yaml# - proton2s dtb specific: - rs485 imx8mp-aristainetos3-proton2s.dtb: serial@30a60000: rs485-rts-delay:0: = 0 is not of type 'array' from schema $id: http://devicetree.org/schemas/serial/fsl-imx-uart.= yaml# imx8mp-aristainetos3-proton2s.dtb: serial@30a60000: rs485-rts-delay:1: = 0 is not of type 'array' from schema $id: http://devicetree.org/schemas/serial/fsl-imx-uart.= yaml# imx8mp-aristainetos3-proton2s.dtb: serial@30a60000: Unevaluated propert= ies are not allowed ('linux,rs485-enabled-at-boot-time', 'rs485-rts-active-= low', 'rs485-rts-delay' were unexpected) from schema $id: http://devicetree.org/schemas/serial/fsl-imx-uart.= yaml# do not see, what I am doing wrong, also rs485 works fine - led driver imx8mp-aristainetos3-proton2s.dtb: /soc@0/bus@30800000/i2c@30a30000/tlc= 59108@40: failed to match any schema with compatible: ['ti,tlc59108'] I use the comaptible entry used in drivers/leds/leds-tlc591xx.c Ah, may because file Documentation/devicetree/bindings/leds/leds-tlc591xx.txt is not converted to yaml? - pinctrl driver adding 'gpio-line-names' leads in a warning as this property is not checked yet (and so a warning is dropped). add this check in new patch dt-bindings: pinctrl: sx150xq: allow gpio line naming in v2 arch/arm64/boot/dts/freescale/Makefile | 5 + .../imx8mp-aristainetos3-adpismarc.dts | 37 + .../imx8mp-aristainetos3-helios-lvds.dtso | 113 ++ .../freescale/imx8mp-aristainetos3-helios.dts | 98 ++ .../imx8mp-aristainetos3-proton2s.dts | 161 +++ .../imx8mp-aristainetos3a-som-v1.dtsi | 1107 +++++++++++++++++ 6 files changed, 1521 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-adpi= smarc.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-heli= os-lvds.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-heli= os.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-prot= on2s.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som= -v1.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 9d3df8b218a2..40dcd24bf494 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -163,6 +163,11 @@ imx8mn-tqma8mqnl-mba8mx-usbotg-dtbs +=3D imx8mn-tqma8m= qnl-mba8mx.dtb imx8mn-tqma8m dtb-$(CONFIG_ARCH_MXC) +=3D imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mn-tqma8mqnl-mba8mx-usbotg.dtb =20 +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-aristainetos3-adpismarc.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-aristainetos3-helios.dtb +imx8mp-aristainetos3-helios-lvds-dtbs +=3D imx8mp-aristainetos3-helios.dtb= imx8mp-aristainetos3-helios-lvds.dtbo +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-aristainetos3-helios-lvds.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-aristainetos3-proton2s.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-data-modul-edm-sbc.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-debix-model-a.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-adpismarc.d= ts b/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-adpismarc.dts new file mode 100644 index 000000000000..6a688510dad9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-adpismarc.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2024 Heiko Schocher + */ + +/dts-v1/; + +#include +#include +#include "imx8mp-aristainetos3a-som-v1.dtsi" + +&{/} { + model =3D "Aristainetos3 ADLink PI SMARC carrier"; + compatible =3D "abb,imx8mp-aristanetos3-adpismarc", + "abb,imx8mp-aristanetos3-som", + "fsl,imx8mp"; +}; + +&flexcan1 { + status =3D "okay"; +}; + +&i2c2 { + gpio8: pinctrl@3e { + compatible =3D "semtech,sx1509q"; + reg =3D <0x3e>; + + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + semtech,probe-reset; + gpio-controller; + interrupt-controller; + interrupt-parent =3D <&gpio6>; + interrupts =3D <1 IRQ_TYPE_EDGE_FALLING>; + }; + +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-helios-lvds= .dtso b/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-helios-lvds.dtso new file mode 100644 index 000000000000..9d1f3b4ccc79 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-helios-lvds.dtso @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2024 Heiko Schocher + */ +#include +#include +#include +#include + +/dts-v1/; +/plugin/; + +&{/} { + model =3D "Aristainetos3 helios carrier with LVDS"; + compatible =3D "abb,imx8mp-aristanetos3-helios", + "abb,imx8mp-aristanetos3-som", + "fsl,imx8mp"; + + panel_lvds: panel-lvds { + compatible =3D "lg,lb070wv8"; + power-supply =3D <®_vcc_disp>; + backlight =3D <&lvds_backlight>; + + port { + in_lvds0: endpoint { + remote-endpoint =3D <&ldb_lvds_ch0>; + }; + }; + }; + + reg_vcc_disp: regulator-disp { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lcd0_vcc_en>; + compatible =3D "regulator-fixed"; + regulator-name =3D "disp_power_en_2v8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + gpio =3D <&gpio1 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; +}; + +&gpio3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio3_hog>; + + lvdssel-hog { + gpio-hog; + gpios =3D <23 GPIO_ACTIVE_HIGH>; + output-low; + line-name =3D "LVDSSEL"; + }; +}; + +&hdmi_blk_ctrl { + status =3D "disabled"; +}; + +&hdmi_pvi { + status =3D "disabled"; +}; + +&hdmi_tx { + status =3D "disabled"; +}; + +&hdmi_tx_phy { + status =3D "disabled"; +}; + +&irqsteer_hdmi { + status =3D "disabled"; +}; + +&ldb_lvds_ch0 { + remote-endpoint =3D <&in_lvds0>; +}; + +&lcdif1 { + status =3D "disabled"; +}; + +&lcdif2 { + status =3D "okay"; +}; + +&lcdif3 { + status =3D "disabled"; +}; + +&lvds_backlight { + status =3D "okay"; +}; + +&lvds_bridge { + /* IMX8MP_CLK_MEDIA_LDB =3D IMX8MP_CLK_MEDIA_DISP2_PIX * 7 */ + assigned-clock-rates =3D <232820000>; + status =3D "okay"; +}; + +&media_blk_ctrl { + /* + * currently it is not possible to let display clocks configure + * automatically, so we need to set them manually + */ + assigned-clock-rates =3D <500000000>, <200000000>, <0>, + /* IMX8MP_CLK_MEDIA_DISP2_PIX =3D pixelclk of lvds panel */ + <33260000>, <0>, + /* IMX8MP_VIDEO_PLL1 =3D IMX8MP_CLK_MEDIA_LDB * 2 */ + <465640000>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-helios.dts = b/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-helios.dts new file mode 100644 index 000000000000..a4e649a8239b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-helios.dts @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2024 Heiko Schocher + */ + +/dts-v1/; + +#include +#include +#include "imx8mp-aristainetos3a-som-v1.dtsi" + +&{/} { + model =3D "Aristainetos3 helios carrier"; + compatible =3D "abb,imx8mp-aristanetos3-helios", + "abb,imx8mp-aristanetos3-som", + "fsl,imx8mp"; + + led-controller { + compatible =3D "gpio-leds"; + + led-0 { + function =3D LED_FUNCTION_STATUS; + color =3D ; + function-enumerator =3D <20>; + gpios =3D <&pca6416 12 GPIO_ACTIVE_LOW>; + default-state =3D "off"; + }; + + led-1 { + function =3D LED_FUNCTION_STATUS; + color =3D ; + function-enumerator =3D <20>; + gpios =3D <&pca6416 13 GPIO_ACTIVE_LOW>; + default-state =3D "off"; + }; + + led-2 { + function =3D LED_FUNCTION_STATUS; + color =3D ; + function-enumerator =3D <20>; + gpios =3D <&pca6416 14 GPIO_ACTIVE_LOW>; + default-state =3D "off"; + }; + + led-3 { + function =3D LED_FUNCTION_STATUS; + color =3D ; + function-enumerator =3D <20>; + gpios =3D <&pca6416 15 GPIO_ACTIVE_LOW>; + default-state =3D "off"; + }; + }; +}; + +ðphy1 { + status =3D "disabled"; +}; + +&fec { + status =3D "disabled"; +}; + +&i2c1 { + eeprom@57 { + compatible =3D "atmel,24c64"; + reg =3D <0x57>; + }; +}; + +&i2c3 { + pca6416: gpio@20 { + compatible =3D "ti,tca6416"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "DIN0_CON", + "DIN1_CON", + "DIN2_CON", + "DIN3_CON", + "DIN4_CON", + "DIN5_CON", + "DIN6_CON", + "DIN7_CON", + "PM102_RES", + "COMx_RES", + "BPL_RES", + "PC_RES", + "LED_RED", + "LED_YELLOW", + "LED_GREEN", + "LED_BLUE"; + }; + + rtc@68 { + compatible =3D "st,m41t00"; + reg =3D <0x68>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-proton2s.dt= s b/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-proton2s.dts new file mode 100644 index 000000000000..2a736dbe96b4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-proton2s.dts @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2024 Heiko Schocher + */ + +/dts-v1/; + +#include +#include +#include "imx8mp-aristainetos3a-som-v1.dtsi" + +&{/} { + model =3D "Aristainetos3 proton2s carrier"; + compatible =3D "abb,imx8mp-aristanetos3-proton2s", + "abb,imx8mp-aristanetos3-som", + "fsl,imx8mp"; + + watchdog { + /* MAX6371KA */ + compatible =3D "linux,wdt-gpio"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_watchdog_gpio>; + always-running; + gpios =3D <&gpio1 6 GPIO_ACTIVE_HIGH>; + hw_algo =3D "level"; + /* Reset triggers in 3..9 seconds */ + hw_margin_ms =3D <1500>; + }; +}; + +ðphy1 { + status =3D "disabled"; +}; + +&eqos { + max-speed =3D <100>; +}; + +&ecspi1{ + pinctrl-0 =3D <&pinctrl_ecspi1>; + cs-gpios =3D <&gpio5 9 GPIO_ACTIVE_LOW>; +}; + +&fec { + status =3D "disabled"; +}; + +&gpio1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio_proton2s>; + + gpio-line-names =3D + "", "", "", "", "", "", "", "POWER", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio6 { + gpio-line-names =3D + "RELAY0", "RELAY1", "RELAY2", "HEATER", + "FAN", "SPARE", "CLEAR", "FAULT", + "", "", "", "", "", "", "", "", ""; +}; + +&i2c2 { + tlc59108@40 { + compatible =3D "ti,tlc59108"; + reg =3D <0x40>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + led@0 { + reg =3D <0x0>; + function =3D LED_FUNCTION_STATUS; + color =3D ; + function-enumerator =3D <20>; + }; + + led@1 { + reg =3D <0x1>; + function =3D LED_FUNCTION_STATUS; + color =3D ; + function-enumerator =3D <20>; + }; + + led@2 { + reg =3D <0x2>; + function =3D LED_FUNCTION_STATUS; + color =3D ; + function-enumerator =3D <21>; + }; + + led@3 { + reg =3D <0x3>; + function =3D LED_FUNCTION_STATUS; + color =3D ; + function-enumerator =3D <21>; + }; + + led@4 { + reg =3D <0x4>; + function =3D LED_FUNCTION_STATUS; + color =3D ; + function-enumerator =3D <21>; + }; + + led@5 { + reg =3D <0x5>; + function =3D LED_FUNCTION_STATUS; + color =3D ; + function-enumerator =3D <22>; + }; + + led@6 { + reg =3D <0x6>; + function =3D LED_FUNCTION_STATUS; + color =3D ; + function-enumerator =3D <22>; + }; + + led@7 { + reg =3D <0x7>; + function =3D LED_FUNCTION_STATUS; + color =3D ; + function-enumerator =3D <22>; + }; + }; + + rtc1: rtc@68 { + compatible =3D "dallas,ds1339"; + reg =3D <0x68>; + }; +}; + +&uart1 { + pinctrl-0 =3D <&pinctrl_uart1>; +}; + +&uart2 { + pinctrl-0 =3D <&pinctrl_uart2>; +}; + +&uart3 { + pinctrl-0 =3D <&pinctrl_uart3>; +}; + +&uart4 { + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rts-delay =3D <0 0>; + rts-gpios =3D <&gpio3 9 GPIO_ACTIVE_HIGH>; +}; + +&usdhc1 { + status =3D "disabled"; +}; + +&wdog1 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dts= i b/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi new file mode 100644 index 000000000000..231e480acfd4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi @@ -0,0 +1,1107 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Heiko Schocher + */ + +#include +#include +#include +#include +#include "imx8mp.dtsi" + +/ { + model =3D "ADLINK LEC-iMX8MP-Q-N-4G-32G"; + compatible =3D "abb,imx8mp-aristanetos3-som", "fsl,imx8mp"; + + aliases { + ethernet0 =3D &eqos; + ethernet1 =3D &fec; + mmc0 =3D &usdhc3; /* eMMC */ + mmc1 =3D &usdhc2; /* MicroSD */ + }; + + chosen { + bootargs =3D "console=3Dttymxc1,115200 earlycon=3Dec_imx6q,0x30890000,11= 5200"; + stdout-path =3D &uart2; + }; + + connector { + compatible =3D "usb-c-connector"; + label =3D "USB-C"; + + port { + usb_dr_connector: endpoint { + remote-endpoint =3D <&usb3_dwc>; + }; + }; + }; + + gpio-leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio_led>; + + led-0 { + function =3D LED_FUNCTION_STATUS; + color =3D ; + function-enumerator =3D <0>; + gpios =3D <&gpio3 16 GPIO_ACTIVE_HIGH>; + default-state =3D "on"; + }; + }; + + lvds_backlight: backlight { + compatible =3D "pwm-backlight"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lvds_bklt_en>; + pwms =3D <&pwm2 0 50000 0>; + enable-gpios =3D <&gpio1 10 GPIO_ACTIVE_HIGH>; + brightness-levels =3D <0 100>; + num-interpolated-steps =3D <100>; + default-brightness-level =3D <80>; + status =3D "disabled"; + }; + + memory@40000000 { + device_type =3D "memory"; + /* Memory size 512 MiB..8 GiB will be filled by U-Boot */ + reg =3D <0x0 0x40000000 0 0x08000000>; + }; + + pcie0_refclk: clock-pcie-ref { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <100000000>; + }; + + reg_can1_stby: regulator-can1-stby { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan1_reg>; + gpio =3D <&gpio5 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "can1-stby"; + }; + + reg_can2_stby: regulator-can2-stby { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan2_reg>; + enable-active-high; + gpio =3D <&gpio4 27 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "can2-stby"; + }; + + reg_dp83867_2v5: regulator-enet { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio7 15 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <1800000>; + regulator-name =3D "enet_2v5"; + regulator-boot-on; + regulator-always-on; + }; + + reg_usb1_host_vbus: regulator-usb1-vbus { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usb1_vbus>; + enable-active-high; + gpio =3D <&gpio1 14 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt =3D <5000000>; + regulator-min-microvolt =3D <5000000>; + regulator-name =3D "usb1_host_vbus"; + regulator-always-on; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usdhc2_vmmc>; + enable-active-high; + gpio =3D <&gpio2 19 GPIO_ACTIVE_HIGH>; /* SD2_RESET */ + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + regulator-name =3D "VDD_3V3_SD"; + off-on-delay-us =3D <12000>; + startup-delay-us =3D <100>; + vin-supply =3D <&buck4>; + }; +}; + +&A53_0 { + cpu-supply =3D <&buck2>; +}; + +&A53_1 { + cpu-supply =3D <&buck2>; +}; + +&A53_2 { + cpu-supply =3D <&buck2>; +}; + +&A53_3 { + cpu-supply =3D <&buck2>; +}; + +&clk { + clocks =3D <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, + <&clk_ext3>, <&clk_ext4>; + clock-names =3D "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", + "clk_ext3", "clk_ext4"; + assigned-clocks =3D <&clk IMX8MP_CLK_A53_SRC>, + <&clk IMX8MP_CLK_A53_CORE>, + <&clk IMX8MP_CLK_NOC>, + <&clk IMX8MP_CLK_NOC_IO>, + <&clk IMX8MP_CLK_GIC>, + <&clk IMX8MP_CLK_AUDIO_AHB>, + <&clk IMX8MP_CLK_AUDIO_AXI_SRC>, + <&clk IMX8MP_AUDIO_PLL1>, + <&clk IMX8MP_AUDIO_PLL2>, + <&clk IMX8MP_VIDEO_PLL1>; +}; + +&ecspi1{ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_ecspi1 &pinctrl_ecspi1_cs2>; + cs-gpios =3D <&gpio5 9 GPIO_ACTIVE_LOW &gpio1 6 GPIO_ACTIVE_LOW>; + status =3D "okay"; +}; + +&ecspi2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_ecspi2>; + cs-gpios =3D <&gpio5 13 GPIO_ACTIVE_LOW>; + status =3D "okay"; +}; + +/* eth0 */ +&eqos { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_eqos_rgmii>; + phy-handle =3D <ðphy0>; + phy-mode =3D "rgmii-id"; + snps,force_thresh_dma_mode; + snps,mtl-tx-config =3D <&mtl_tx_setup>; + snps,mtl-rx-config =3D <&mtl_rx_setup>; + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy0: eqos-ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0>; + ti,rx-internal-delay =3D ; + ti,tx-internal-delay =3D ; + ti,fifo-depth =3D ; + ti,min-output-impedance; + ti,dp83867-rxctrl-strap-quirk; + interrupt-parent =3D <&gpio4>; + interrupts =3D <21 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&gpio4 22 GPIO_ACTIVE_LOW>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <5>; + + queue0 { + snps,dcb-algorithm; + snps,priority =3D <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority =3D <0x2>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority =3D <0x4>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority =3D <0x8>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority =3D <0xf0>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <5>; + + queue0 { + snps,dcb-algorithm; + snps,priority =3D <0x1>; + snps,map-to-dma-channel =3D <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority =3D <0x2>; + snps,map-to-dma-channel =3D <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority =3D <0x4>; + snps,map-to-dma-channel =3D <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority =3D <0x8>; + snps,map-to-dma-channel =3D <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority =3D <0xf0>; + snps,map-to-dma-channel =3D <4>; + }; + }; +}; + +/* eth1 */ +&fec { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_fec_rgmii>; + phy-handle =3D <ðphy1>; + phy-mode =3D "rgmii-id"; + fsl,magic-packet; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy1: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + interrupt-parent =3D <&gpio4>; + interrupts =3D <3 IRQ_TYPE_EDGE_FALLING>; + reset-gpio =3D <&gpio4 2 GPIO_ACTIVE_LOW>; + ti,rx-internal-delay =3D ; + ti,tx-internal-delay =3D ; + ti,fifo-depth =3D ; + ti,min-output-impedance; + ti,dp83867-rxctrl-strap-quirk; + eee-broken-1000t; + }; + }; +}; + +&flexcan1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan1>; + xceiver-supply =3D <®_can1_stby>; + status =3D "disabled"; +}; + +&flexcan2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan2>; + xceiver-supply =3D <®_can1_stby>; + status =3D "disabled"; +}; + +&hdmi_blk_ctrl { + status =3D "okay"; +}; + +&hdmi_pvi { + status =3D "okay"; +}; + +&hdmi_tx { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_hdmi>; + status =3D "okay"; +}; + +&hdmi_tx_phy { + status =3D "okay"; +}; + +&i2c1 { + clock-frequency =3D <100000>; + pinctrl-names =3D "default", "gpio"; + pinctrl-0 =3D <&pinctrl_i2c1>; + pinctrl-1 =3D <&pinctrl_i2c1_gpio>; + scl-gpios =3D <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios =3D <&gpio5 15 GPIO_ACTIVE_HIGH>; + status =3D "okay"; + + pmic: pmic@25 { + compatible =3D "nxp,pca9450c"; + reg =3D <0x25>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pmic>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <3 IRQ_TYPE_LEVEL_LOW>; + + /* + * i.MX 8M Plus Data Sheet for Consumer Products + * 3.1.4 Operating ranges + * MIMX8ML8CVNKZAB + */ + regulators { + buck1: BUCK1 { /* VDD_SOC (dual-phase with BUCK3) */ + regulator-name =3D "buck1"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <2187500>; + regulator-ramp-delay =3D <3125>; + regulator-always-on; + regulator-boot-on; + }; + + buck2: BUCK2 { /* VDD_ARM */ + regulator-name =3D "buck2"; + nxp,dvs-run-voltage =3D <950000>; + nxp,dvs-standby-voltage =3D <850000>; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <2187500>; + regulator-ramp-delay =3D <3125>; + regulator-always-on; + regulator-boot-on; + }; + + buck4: BUCK4 { /* VDD_3V3 */ + regulator-name =3D "buck4"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck5: BUCK5 { /* VDD_1V8 */ + regulator-name =3D "buck5"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <3400000>; + regulator-always-on; + regulator-boot-on; + }; + + buck6: BUCK6 { /* NVCC_DRAM_1V1 */ + regulator-name =3D "buck6"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <3400000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo1: LDO1 { /* NVCC_SNVS_1V8 */ + regulator-name =3D "ldo1"; + regulator-min-microvolt =3D <1600000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo2: LDO2 { /* VDDA_1V8 */ + regulator-name =3D "ldo2"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1150000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo3: LDO3 { /* VDDA_1V8 */ + regulator-name =3D "ldo3"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4: LDO4 { /* PMIC_LDO4 */ + regulator-name =3D "ldo4"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo5: LDO5 { /* NVCC_SD2 */ + regulator-name =3D "ldo5"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default", "gpio"; + pinctrl-0 =3D <&pinctrl_i2c2>; + pinctrl-1 =3D <&pinctrl_i2c2_gpio>; + scl-gpios =3D <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios =3D <&gpio5 17 GPIO_ACTIVE_HIGH>; + status =3D "okay"; +}; + +&i2c3 { + clock-frequency =3D <100000>; + pinctrl-names =3D "default", "gpio"; + pinctrl-0 =3D <&pinctrl_i2c3>; + pinctrl-1 =3D <&pinctrl_i2c3_gpio>; + scl-gpios =3D <&gpio5 18 GPIO_ACTIVE_HIGH>; + sda-gpios =3D <&gpio5 19 GPIO_ACTIVE_HIGH>; + status =3D "okay"; +}; + +&i2c5 { + #address-cells =3D <1>; + clock-frequency =3D <100000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c5>; + status =3D "okay"; +}; + +&i2c6 { + clock-frequency =3D <100000>; + pinctrl-names =3D "default", "gpio"; + pinctrl-0 =3D <&pinctrl_i2c6>; + pinctrl-1 =3D <&pinctrl_i2c6_gpio>; + scl-gpios =3D <&gpio3 19 GPIO_ACTIVE_HIGH>; + sda-gpios =3D <&gpio3 20 GPIO_ACTIVE_HIGH>; + status =3D "okay"; + + /* TPM - ST33TPHF2XI2C U2301 */ + tpm: tpm@2e { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_tpm_irq>; + compatible =3D "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; + reg =3D <0x2e>; + + label =3D "tpm"; + interrupt-parent =3D <&gpio3>; + interrupts =3D <14 IRQ_TYPE_LEVEL_LOW>; + reset-gpios =3D <&gpio6 11 GPIO_ACTIVE_LOW>; + status =3D "okay"; + }; + + /* SX1509(0) U2605 */ + gpio6: pinctrl@3f { + compatible =3D "semtech,sx1509q"; + reg =3D <0x3f>; + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + semtech,probe-reset; + gpio-controller; + interrupt-controller; + interrupt-parent =3D <&gpio1>; + interrupts =3D <12 IRQ_TYPE_EDGE_FALLING>; + }; + + /* RTC U2607 */ + rtc0: rtc@51 { + compatible =3D "nxp,pcf8563"; + reg =3D <0x51>; + #clock-cells =3D <0>; + }; + + /* SX1509(1) U2606 */ + gpio7: pinctrl@70 { + compatible =3D "semtech,sx1509q"; + reg =3D <0x70>; + #gpio-cells =3D <2>; + #interrupt-cells =3D <2>; + semtech,probe-reset; + gpio-controller; + interrupt-controller; + interrupt-parent =3D <&gpio4>; + interrupts =3D <19 IRQ_TYPE_EDGE_FALLING>; + + gpio6-cfg { + pins =3D "gpio6"; + output-high; + }; + + gpio7-cfg { + pins =3D "gpio7"; + output-high; + }; + }; +}; + +&irqsteer_hdmi { + status =3D "okay"; +}; + +&lcdif1 { + status =3D "disabled"; +}; + +&lcdif2 { + status =3D "disabled"; +}; + +/* HDMI */ +&lcdif3 { + status =3D "okay"; + +}; + +&lvds_bridge { + status =3D "disabled"; +}; + +&mipi_dsi { + status =3D "disabled"; +}; + +&pcie{ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pcie>; + reset-gpio =3D <&gpio4 20 GPIO_ACTIVE_LOW>; + fsl,tx-deemph-gen1 =3D <0x1f>; + fsl,max-link-speed =3D <3>; + status =3D "okay"; +}; + +&pcie_phy{ + fsl,refclk-pad-mode =3D ; + clocks =3D <&pcie0_refclk>; + clock-names =3D "ref"; + status =3D "okay"; +}; + +&pwm1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwm1>; + status =3D "okay"; +}; + +&pwm2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwm2>; + #pwm-cells =3D <3>; + status =3D "okay"; +}; + +&snvs_pwrkey { + status =3D "okay"; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1>; + status =3D "okay"; +}; + +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart2>; + status =3D "okay"; +}; + +&uart3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart3>; + status =3D "okay"; +}; + +&uart4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart4>; + status =3D "okay"; +}; + +&usb3_phy0 { + status =3D "okay"; +}; + +&usb3_0 { + status =3D "okay"; +}; + +&usb_dwc3_0 { + adp-disable; + hnp-disable; + srp-disable; + dr_mode =3D "otg"; + usb-role-switch; + role-switch-default-mode =3D "peripheral"; + status =3D "okay"; + + port { + usb3_dwc: endpoint { + remote-endpoint =3D <&usb_dr_connector>; + }; + }; +}; + +&usb3_phy1 { + status =3D "okay"; +}; + +&usb3_1 { + status =3D "okay"; +}; + +&usb_dwc3_1 { + dr_mode =3D "host"; + status =3D "okay"; +}; + +&usdhc1 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc1>; + pinctrl-1 =3D <&pinctrl_usdhc1_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc1_200mhz>; + bus-width =3D <4>; + non-removable; + status =3D "okay"; +}; + +/* SD slot */ +&usdhc2 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 =3D <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 =3D <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios =3D <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply =3D <®_usdhc2_vmmc>; + bus-width =3D <4>; + status =3D "okay"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc3>; + pinctrl-1 =3D <&pinctrl_usdhc3_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc3_200mhz>; + vmmc-supply =3D <&buck4>; + vqmmc-supply =3D <&buck5>; + bus-width =3D <8>; + non-removable; + status =3D "okay"; +}; + +&wdog1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_wdog>; + fsl,ext-reset-output; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: aristainetos3-ecspi1-grp { + fsl,pins =3D < + MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82 + MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82 + MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82 + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40000 + >; + }; + + pinctrl_ecspi1_cs2: aristainetos3-ecspi1-cs2-grp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x40000 + >; + }; + + pinctrl_ecspi2: aristainetos3-ecspi2-grp { + fsl,pins =3D < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40000 + >; + }; + + pinctrl_eqos_rgmii: aristainetos3-eqos-rgmii-grp { + fsl,pins =3D < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19 + >; + }; + + pinctrl_fec_rgmii: aristainetos3-fec-rgmii-grp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19 + >; + }; + + pinctrl_flexcan1: aristainetos3-flexcan1-grp { + fsl,pins =3D < + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 + >; + }; + + pinctrl_flexcan1_reg: aristainetos3-flexcan1-reg-grp { + fsl,pins =3D < + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 + >; + }; + + pinctrl_flexcan2: aristainetos3-flexcan2-grp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 + >; + }; + + pinctrl_flexcan2_reg: aristainetos3-flexcan2-reg-grp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 + >; + }; + + pinctrl_gpio3_hog: aristainetos3-gpio3-hog-grp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0xd6 + >; + }; + + pinctrl_gpio_led: aristainetos3-gpio-led-grp { + fsl,pins =3D < + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 + >; + }; + + pinctrl_gpio_proton2s: aristainetos3-gpio-proton2s-grp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x19 + >; + }; + + pinctrl_hdmi: aristainetos3-hdmi-grp { + fsl,pins =3D < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019 + >; + }; + + pinctrl_i2c1: aristainetos3-i2c1-grp { + fsl,pins =3D < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c1_gpio: aristainetos3-i2c1-gpio-grp { + fsl,pins =3D < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c3 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c3 + >; + }; + + pinctrl_i2c2: aristainetos3-i2c2-grp { + fsl,pins =3D < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2_gpio: aristainetos3-i2c2-gpio-grp { + fsl,pins =3D < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c3 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c3 + >; + }; + + pinctrl_i2c3: aristainetos3-i2c3-grp { + fsl,pins =3D < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3_gpio: aristainetos3-i2c3-gpio-grp { + fsl,pins =3D < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c3 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c3 + >; + }; + + pinctrl_i2c5: aristainetos3-i2c5-grp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x400001c3 + MX8MP_IOMUXC_SAI5_MCLK__I2C5_SDA 0x400001c3 + >; + }; + + pinctrl_i2c6: aristainetos3-i2c6-grp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3 + MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3 + >; + }; + + pinctrl_i2c6_gpio: aristainetos3-i2c6-gpio-grp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x1c3 + MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x1c3 + >; + }; + + pinctrl_lcd0_vcc_en: aristainetos3-lcd0-vcc-en-grp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0xd6 + >; + }; + + pinctrl_lvds_bklt_en: aristainetos3-lvds-bklt-en-grp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0xd6 + >; + }; + + pinctrl_pcie: aristainetos3-pcie-grp { + fsl,pins =3D < + MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61 + MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x41 + >; + }; + + pinctrl_pmic: aristainetos3-pmic-grp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + >; + }; + + pinctrl_pwm1: aristainetos3-pwm1-grp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116 + >; + }; + + pinctrl_pwm2: aristainetos3-pwm2-grp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116 + >; + }; + + pinctrl_tpm_irq: aristainetos3-tpm-irq-grp { + fsl,pins =3D < + MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0xd6 + >; + }; + + pinctrl_uart1: aristainetos3-uart1-grp { + fsl,pins =3D < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + >; + }; + + pinctrl_uart2: aristainetos3-uart2-grp { + fsl,pins =3D < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x140 + MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x140 + >; + }; + + pinctrl_uart3: aristainetos3-uart3-grp { + fsl,pins =3D < + MX8MP_IOMUXC_NAND_ALE__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_NAND_CE0_B__UART3_DCE_TX 0x140 + >; + }; + + pinctrl_uart4: aristainetos3-uart4-grp { + fsl,pins =3D < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 + MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x140 + MX8MP_IOMUXC_NAND_DATA02__UART4_DCE_CTS 0x140 + >; + }; + + pinctrl_usb1_vbus: aristainetos3-usb1-grp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19 + >; + }; + + pinctrl_usdhc1: aristainetos3-usdhc1-grp { + fsl,pins =3D < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: aristainetos3-usdhc1-100mhz-grp { + fsl,pins =3D < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: aristainetos3-usdhc1-200mhz-grp { + fsl,pins =3D < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2: aristainetos3-usdhc2-grp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + + >; + }; + + pinctrl_usdhc2_100mhz: aristainetos3-usdhc2-100mhz-grp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: aristainetos3-usdhc2-200mhz-grp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: aristainetos3-usdhc2-gpio-grp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x40000080 + >; + }; + + pinctrl_usdhc2_vmmc: aristainetos3-usdhc2-vmmc-grp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc3: aristainetos3-usdhc3-grp { + fsl,pins =3D < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: aristainetos3-usdhc3-100mhz-grp { + fsl,pins =3D < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: aristainetos3-usdhc3-200mhz-grp { + fsl,pins =3D < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_watchdog_gpio: aristainetos3-wdog-gpio-grp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x19 + >; + }; + + pinctrl_wdog: aristainetos3-wdog-grp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; +}; --=20 2.20.1