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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 06:06:45.7333 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9a09b216-f5dc-428d-772a-08dcfd60071f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FBF.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7611 Content-Type: text/plain; charset="utf-8" From: Huang Rui There is an second stage translation between the guest machine address and host machine address in Xen PVH/HVM. The PCI bar address in the xen guest kernel are not translated at the second stage on Xen PVH/HVM, so it's not the real physical address that hardware would like to know, so we need to set passthrough mode for Xen PVH/HVM as well. Signed-off-by: Huang Rui Signed-off-by: Jiqian Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd= /amdgpu/amdgpu_virt.c index b6397d3229e1..0836fb77b263 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -764,7 +764,8 @@ void amdgpu_detect_virtualization(struct amdgpu_device = *adev) =20 if (!reg) { /* passthrough mode exclus sriov mod */ - if (is_virtual_machine() && !xen_initial_domain()) + if (is_virtual_machine() && + !(xen_initial_domain() && xen_pv_domain())) adev->virt.caps |=3D AMDGPU_PASSTHROUGH_MODE; } =20 --=20 2.34.1 From nobody Sun Nov 24 14:43:37 2024 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2082.outbound.protection.outlook.com [40.107.92.82]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C7931C9EB8 for ; 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Tue, 5 Nov 2024 00:06:45 -0600 From: Jiqian Chen To: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Xinhui Pan CC: , , Pierre-Eric Pelloux-Prayer , Jiqian Chen , Huang Rui Subject: [PATCH 2/2] drm/amdgpu: Bypass resizing bars for PVH dom0 Date: Tue, 5 Nov 2024 14:05:31 +0800 Message-ID: <20241105060531.3503788-3-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241105060531.3503788-1-Jiqian.Chen@amd.com> References: <20241105060531.3503788-1-Jiqian.Chen@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF00004FC1:EE_|CH3PR12MB8583:EE_ X-MS-Office365-Filtering-Correlation-Id: eda62e0a-e3de-4006-bee0-08dcfd600887 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2024 06:06:48.0944 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eda62e0a-e3de-4006-bee0-08dcfd600887 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FC1.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8583 Content-Type: text/plain; charset="utf-8" VPCI of Xen doesn't support resizable bar. When discrete GPU is used on PVH dom0 which using the VPCI, amdgpu fails to probe, so we need to disable this capability for PVH dom0. Signed-off-by: Jiqian Chen Reviewed-by: Huang Rui --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/a= md/amdgpu/amdgpu_device.c index b3fb92bbd9e2..012feb3790dd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1619,6 +1619,10 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device= *adev) if (!IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT)) return 0; =20 + /* Bypass for PVH dom0 which doesn't support resizable bar */ + if (xen_initial_domain() && xen_pvh_domain()) + return 0; + /* Bypass for VF */ if (amdgpu_sriov_vf(adev)) return 0; --=20 2.34.1