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charset="utf-8" A panel assembly is changed in the recent revision of Anbernic RG35XX Plus, so the `anbernic,rg35xx-plus-panel` identifier is neither suitable nor unique for the panel anymore. Fortunately, the panel can be distinguished by a label printed on the FPC cable, so use the label "WL-355608-A8" as an identifier instead. Signed-off-by: Hironori KIKUCHI --- ...rg35xx-plus-panel.yaml =3D> anbernic,wl-355608-a8.yaml} | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) rename Documentation/devicetree/bindings/display/panel/{anbernic,rg35xx-pl= us-panel.yaml =3D> anbernic,wl-355608-a8.yaml} (83%) diff --git a/Documentation/devicetree/bindings/display/panel/anbernic,rg35x= x-plus-panel.yaml b/Documentation/devicetree/bindings/display/panel/anberni= c,wl-355608-a8.yaml similarity index 83% rename from Documentation/devicetree/bindings/display/panel/anbernic,rg35xx= -plus-panel.yaml rename to Documentation/devicetree/bindings/display/panel/anbernic,wl-35560= 8-a8.yaml index 1d67492ebd3..5e8afbea690 100644 --- a/Documentation/devicetree/bindings/display/panel/anbernic,rg35xx-plus-= panel.yaml +++ b/Documentation/devicetree/bindings/display/panel/anbernic,wl-355608-a8= .yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/display/panel/anbernic,rg35xx-plus-pane= l.yaml# +$id: http://devicetree.org/schemas/display/panel/anbernic,wl-355608-a8.yam= l# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 title: Anbernic RG35XX series (WL-355608-A8) 3.5" 640x480 24-bit IPS LCD p= anel @@ -16,13 +16,14 @@ allOf: properties: compatible: oneOf: - - const: anbernic,rg35xx-plus-panel + - const: anbernic,wl-355608-a8 - items: - enum: - anbernic,rg35xx-2024-panel - anbernic,rg35xx-h-panel - anbernic,rg35xx-sp-panel - - const: anbernic,rg35xx-plus-panel + - anbernic,rg35xx-plus-panel + - const: anbernic,wl-355608-a8 =20 reg: maxItems: 1 @@ -47,7 +48,7 @@ examples: #size-cells =3D <0>; =20 panel@0 { - compatible =3D "anbernic,rg35xx-plus-panel"; + compatible =3D "anbernic,wl-355608-a8"; reg =3D <0>; =20 spi-3wire; --=20 2.47.0 From nobody Sun Nov 24 14:41:18 2024 Received: from mail-pg1-f177.google.com (mail-pg1-f177.google.com [209.85.215.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A1F21DCB20; Tue, 5 Nov 2024 05:54:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730786049; cv=none; b=tSSY0jxARyH3PvgRf9CMDQgR0Nqs1zaLZdMLNQZKa0NnR2DfWHePj5EPyptZ+2nDPhDBfFmAKZdaAvuaRqcMPuk48OrXWtkyCWBh0SPLe1gqjr9QRM08eZhh5WKtGxYDFGtFfRqeJXkDDeBZculg+WFfA0hFZSTYvx/1NQA13Eg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730786049; c=relaxed/simple; bh=M1QbV8jUSLdS3bCR5razbuOE+JbrhnHNbA3kueAHOyQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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charset="utf-8" A panel assembly is changed in the recent revision of Anbernic RG35XX Plus, so the `anbernic,rg35xx-plus-panel` identifier is neither suitable nor unique for the panel anymore. Fortunately, the panel can be distinguished by a label printed on the FPC cable, so use the label "WL-355608-A8" as an identifier instead. Signed-off-by: Hironori KIKUCHI --- drivers/gpu/drm/panel/panel-newvision-nv3052c.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c b/drivers/gpu/= drm/panel/panel-newvision-nv3052c.c index 06e16a7c14a..2da1e924177 100644 --- a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c +++ b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c @@ -917,7 +917,7 @@ static const struct nv3052c_panel_info wl_355608_a8_pan= el_info =3D { static const struct spi_device_id nv3052c_ids[] =3D { { "ltk035c5444t", }, { "fs035vg158", }, - { "rg35xx-plus-panel", }, + { "wl-355608-a8", }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(spi, nv3052c_ids); @@ -925,7 +925,7 @@ MODULE_DEVICE_TABLE(spi, nv3052c_ids); static const struct of_device_id nv3052c_of_match[] =3D { { .compatible =3D "leadtek,ltk035c5444t", .data =3D <k035c5444t_panel_i= nfo }, { .compatible =3D "fascontek,fs035vg158", .data =3D &fs035vg158_panel_inf= o }, - { .compatible =3D "anbernic,rg35xx-plus-panel", .data =3D &wl_355608_a8_p= anel_info }, + { .compatible =3D "anbernic,wl-355608-a8", .data =3D &wl_355608_a8_panel_= info }, { /* sentinel */ } }; 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charset="utf-8" It is 3.45 inches in size (diagonally). Signed-off-by: Hironori KIKUCHI --- drivers/gpu/drm/panel/panel-newvision-nv3052c.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c b/drivers/gpu/= drm/panel/panel-newvision-nv3052c.c index 2da1e924177..2f3a8eaade4 100644 --- a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c +++ b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c @@ -906,8 +906,8 @@ static const struct nv3052c_panel_info fs035vg158_panel= _info =3D { static const struct nv3052c_panel_info wl_355608_a8_panel_info =3D { .display_modes =3D wl_355608_a8_mode, .num_modes =3D ARRAY_SIZE(wl_355608_a8_mode), - .width_mm =3D 150, - .height_mm =3D 94, + .width_mm =3D 70, + .height_mm =3D 53, .bus_format =3D MEDIA_BUS_FMT_RGB888_1X24, .bus_flags =3D DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, .panel_regs =3D wl_355608_a8_panel_regs, --=20 2.47.0 From nobody Sun Nov 24 14:41:18 2024 Received: from mail-pl1-f182.google.com (mail-pl1-f182.google.com [209.85.214.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB63A1FF027; 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charset="utf-8" The YLM-LBV0345001H-V2 panel is a display panel used in the recent revision of Anbernic RG35XX Plus, a handheld gaming device from Anbernic. It is 3.45 inches in size (diagonally) with a resolution of 640x480. Signed-off-by: Hironori KIKUCHI --- .../panel/anbernic,ylm-lbv0345001h-v2.yaml | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/anberni= c,ylm-lbv0345001h-v2.yaml diff --git a/Documentation/devicetree/bindings/display/panel/anbernic,ylm-l= bv0345001h-v2.yaml b/Documentation/devicetree/bindings/display/panel/anbern= ic,ylm-lbv0345001h-v2.yaml new file mode 100644 index 00000000000..ae00096bf3d --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/anbernic,ylm-lbv03450= 01h-v2.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/anbernic,ylm-lbv0345001h-= v2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Anbernic RG35XX series (YLM-LBV0345001H-V2) 3.45" 640x480 24-bit IP= S LCD panel + +maintainers: + - Hironori KIKUCHI + +allOf: + - $ref: panel-common.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + oneOf: + - const: anbernic,ylm-lbv0345001h-v2 + - items: + - enum: + - anbernic,rg35xx-2024-panel + - anbernic,rg35xx-h-panel + - anbernic,rg35xx-sp-panel + - anbernic,rg35xx-plus-panel + - const: anbernic,ylm-lbv0345001h-v2 + + reg: + maxItems: 1 + + spi-3wire: true + +required: + - compatible + - reg + - port + - power-supply + - reset-gpios + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + panel@0 { + compatible =3D "anbernic,ylm-lbv0345001h-v2"; + reg =3D <0>; + + spi-3wire; + spi-max-frequency =3D <3125000>; + + reset-gpios =3D <&pio 8 14 GPIO_ACTIVE_LOW>; // PI14 + + backlight =3D <&backlight>; + power-supply =3D <®_lcd>; + + port { + endpoint { + remote-endpoint =3D <&tcon_lcd0_out_lcd>; + }; + }; + }; + }; --=20 2.47.0 From nobody Sun Nov 24 14:41:18 2024 Received: from mail-pf1-f177.google.com (mail-pf1-f177.google.com [209.85.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CADBF1B6D04; Tue, 5 Nov 2024 05:54:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730786063; cv=none; b=Mh3YvTaFLc0+FJrlbVlewAyBdZ+mQ/ddJFProy0/NAbWNOLwWH2hdo0sCMwqMJhB+xfVZGuX3t6CJKu5UVUG1viLfmtCtVDgTXKbn3posQJiWNMdE9XBGqPvA6Opv8bIE/dA6p+owBvCaF+2rcSlXPvR/2yW6QX6MExCgl32h9w= ARC-Message-Signature: i=1; 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Mon, 04 Nov 2024 21:54:18 -0800 (PST) From: Hironori KIKUCHI To: linux-kernel@vger.kernel.org Cc: Hironori KIKUCHI , Neil Armstrong , Jessica Zhang , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ryan Walklin , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH 5/7] drm: panel: nv3052c: Add YLM-LBV0345001H-V2 panel Date: Tue, 5 Nov 2024 14:52:33 +0900 Message-ID: <20241105055239.1577275-6-kikuchan98@gmail.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241105055239.1577275-1-kikuchan98@gmail.com> References: <20241105055239.1577275-1-kikuchan98@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The YLM-LBV0345001H-V2 panel is a display panel used in the recent revision of Anbernic RG35XX Plus, a handheld gaming device from Anbernic. It is 3.45 inches in size (diagonally) with a resolution of 640x480. It has the same interface (pins and connector) as WL-355608-A8, the panel of the former revision of RG35XX Plus, but they differ on its init-sequence. So add entry for the new panel. Signed-off-by: Hironori KIKUCHI --- .../gpu/drm/panel/panel-newvision-nv3052c.c | 177 ++++++++++++++++++ 1 file changed, 177 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c b/drivers/gpu/= drm/panel/panel-newvision-nv3052c.c index 2f3a8eaade4..57f6d5b1288 100644 --- a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c +++ b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c @@ -629,6 +629,155 @@ static const struct nv3052c_reg wl_355608_a8_panel_re= gs[] =3D { { 0x36, 0x0a }, // bgr =3D 1, ss =3D 1, gs =3D 0 }; =20 +static const struct nv3052c_reg ylm_lbv0345001h_v2_panel_regs[] =3D { + // EXTC Command set enable, select page 1 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x01 }, + // Mostly unknown registers + { 0xe3, 0x00 }, + { 0x0a, 0x01 }, + { 0x23, 0xa0 }, + { 0x24, 0x10 }, + { 0x25, 0x09 }, + { 0x28, 0x47 }, + { 0x29, 0x01 }, + { 0x2a, 0xdf }, + { 0x38, 0x9c }, + { 0x39, 0xa7 }, + { 0x3a, 0x3f }, + { 0x91, 0x77 }, + { 0x92, 0x77 }, + { 0xa0, 0x55 }, + { 0xa1, 0x50 }, + { 0xa4, 0x9c }, + { 0xa7, 0x02 }, + { 0xa8, 0x01 }, + { 0xa9, 0x01 }, + { 0xaa, 0xfc }, + { 0xab, 0x28 }, + { 0xac, 0x06 }, + { 0xad, 0x06 }, + { 0xae, 0x06 }, + { 0xaf, 0x03 }, + { 0xb0, 0x08 }, + { 0xb1, 0x26 }, + { 0xb2, 0x28 }, + { 0xb3, 0x28 }, + { 0xb4, 0x03 }, + { 0xb5, 0x08 }, + { 0xb6, 0x26 }, + { 0xb7, 0x08 }, + { 0xb8, 0x26 }, + // EXTC Command set enable, select page 2 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 }, + // Set gray scale voltage to adjust gamma + { 0xb0, 0x02 }, // PGAMVR0 + { 0xb1, 0x0f }, // PGAMVR1 + { 0xb2, 0x11 }, // PGAMVR2 + { 0xb3, 0x32 }, // PGAMVR3 + { 0xb4, 0x36 }, // PGAMVR4 + { 0xb5, 0x3c }, // PGAMVR5 + { 0xb6, 0x20 }, // PGAMPR0 + { 0xb7, 0x3e }, // PGAMPR1 + { 0xb8, 0x0e }, // PGAMPK0 + { 0xb9, 0x05 }, // PGAMPK1 + { 0xba, 0x11 }, // PGAMPK2 + { 0xbb, 0x11 }, // PGAMPK3 + { 0xbc, 0x13 }, // PGAMPK4 + { 0xbd, 0x14 }, // PGAMPK5 + { 0xbe, 0x16 }, // PGAMPK6 + { 0xbf, 0x0e }, // PGAMPK7 + { 0xc0, 0x17 }, // PGAMPK8 + { 0xc1, 0x07 }, // PGAMPK9 + { 0xd0, 0x02 }, // NGAMVR0 + { 0xd1, 0x10 }, // NGAMVR0 + { 0xd2, 0x12 }, // NGAMVR1 + { 0xd3, 0x33 }, // NGAMVR2 + { 0xd4, 0x36 }, // NGAMVR3 + { 0xd5, 0x3c }, // NGAMVR4 + { 0xd6, 0x20 }, // NGAMPR0 + { 0xd7, 0x3e }, // NGAMPR1 + { 0xd8, 0x0d }, // NGAMPK0 + { 0xd9, 0x05 }, // NGAMPK1 + { 0xda, 0x12 }, // NGAMPK2 + { 0xdb, 0x11 }, // NGAMPK3 + { 0xdc, 0x14 }, // NGAMPK4 + { 0xdd, 0x14 }, // NGAMPK5 + { 0xde, 0x18 }, // NGAMPK6 + { 0xdf, 0x0f }, // NGAMPK7 + { 0xe0, 0x17 }, // NGAMPK8 + { 0xe1, 0x08 }, // NGAMPK9 + // EXTC Command set enable, select page 3 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x03 }, + // Mostly unknown registers + { 0x07, 0x03 }, + { 0x08, 0x00 }, + { 0x09, 0x01 }, + { 0x30, 0x00 }, + { 0x31, 0x00 }, + { 0x32, 0x00 }, + { 0x33, 0x00 }, + { 0x34, 0x61 }, + { 0x35, 0xd4 }, + { 0x36, 0x24 }, + { 0x37, 0x03 }, + { 0x40, 0x02 }, + { 0x41, 0x03 }, + { 0x42, 0x04 }, + { 0x43, 0x05 }, + { 0x44, 0x11 }, + { 0x45, 0xe6 }, + { 0x46, 0xe7 }, + { 0x47, 0x11 }, + { 0x48, 0xe8 }, + { 0x49, 0xe9 }, + { 0x50, 0x06 }, + { 0x51, 0x07 }, + { 0x52, 0x08 }, + { 0x53, 0x09 }, + { 0x54, 0x11 }, + { 0x55, 0xea }, + { 0x56, 0xeb }, + { 0x57, 0x11 }, + { 0x58, 0xec }, + { 0x59, 0xed }, + { 0x82, 0x00 }, + { 0x83, 0x00 }, + { 0x84, 0x02 }, + { 0x85, 0x00 }, + { 0x86, 0x1f }, + { 0x87, 0x00 }, + { 0x88, 0x1f }, + { 0x89, 0x0e }, + { 0x8a, 0x0e }, + { 0x8b, 0x10 }, + { 0x8c, 0x10 }, + { 0x8d, 0x0a }, + { 0x8e, 0x0a }, + { 0x8f, 0x0c }, + { 0x90, 0x0c }, + { 0x98, 0x00 }, + { 0x99, 0x00 }, + { 0x9a, 0x01 }, + { 0x9b, 0x00 }, + { 0x9c, 0x1f }, + { 0x9d, 0x00 }, + { 0x9e, 0x1f }, + { 0x9f, 0x0d }, + { 0xa0, 0x0d }, + { 0xa1, 0x0f }, + { 0xa2, 0x0f }, + { 0xa3, 0x09 }, + { 0xa4, 0x09 }, + { 0xa5, 0x0b }, + { 0xa6, 0x0b }, + // EXTC Command set enable, select page 0 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x00 }, + // Interface Pixel Format + { 0x3a, 0x77 }, + // Display Access Control + { 0x36, 0x0a }, // bgr =3D 1, ss =3D 1, gs =3D 0 +}; + static inline struct nv3052c *to_nv3052c(struct drm_panel *panel) { return container_of(panel, struct nv3052c, panel); @@ -881,6 +1030,21 @@ static const struct drm_display_mode wl_355608_a8_mod= e[] =3D { }, }; =20 +static const struct drm_display_mode ylm_lbv0345001h_v2_mode[] =3D { + { + .clock =3D 24000, + .hdisplay =3D 640, + .hsync_start =3D 640 + 64, + .hsync_end =3D 640 + 64 + 20, + .htotal =3D 640 + 64 + 20 + 46, + .vdisplay =3D 480, + .vsync_start =3D 480 + 21, + .vsync_end =3D 480 + 21 + 4, + .vtotal =3D 480 + 21 + 4 + 15, + .flags =3D DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, + }, +}; + static const struct nv3052c_panel_info ltk035c5444t_panel_info =3D { .display_modes =3D ltk035c5444t_modes, .num_modes =3D ARRAY_SIZE(ltk035c5444t_modes), @@ -914,10 +1078,22 @@ static const struct nv3052c_panel_info wl_355608_a8_= panel_info =3D { .panel_regs_len =3D ARRAY_SIZE(wl_355608_a8_panel_regs), }; =20 +static const struct nv3052c_panel_info ylm_lbv0345001h_v2_panel_info =3D { + .display_modes =3D ylm_lbv0345001h_v2_mode, + .num_modes =3D ARRAY_SIZE(ylm_lbv0345001h_v2_mode), + .width_mm =3D 70, + .height_mm =3D 53, + .bus_format =3D MEDIA_BUS_FMT_RGB888_1X24, + .bus_flags =3D DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, + .panel_regs =3D ylm_lbv0345001h_v2_panel_regs, + .panel_regs_len =3D ARRAY_SIZE(ylm_lbv0345001h_v2_panel_regs), +}; + static const struct spi_device_id nv3052c_ids[] =3D { { "ltk035c5444t", }, { "fs035vg158", }, { "wl-355608-a8", }, + { "ylm-lbv0345001h-v2", }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(spi, nv3052c_ids); @@ -926,6 +1102,7 @@ static const struct of_device_id nv3052c_of_match[] = =3D { { .compatible =3D "leadtek,ltk035c5444t", .data =3D <k035c5444t_panel_i= nfo }, { .compatible =3D "fascontek,fs035vg158", .data =3D &fs035vg158_panel_inf= o }, { .compatible =3D "anbernic,wl-355608-a8", .data =3D &wl_355608_a8_panel_= info }, + { .compatible =3D "anbernic,ylm-lbv0345001h-v2", .data =3D &ylm_lbv034500= 1h_v2_panel_info }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, nv3052c_of_match); --=20 2.47.0 From nobody Sun Nov 24 14:41:18 2024 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE0A81FCF65; Tue, 5 Nov 2024 05:54:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 04 Nov 2024 21:54:22 -0800 (PST) Received: from noel.flets-west.jp ([2405:6586:4480:a10:fa8f:7c3e:835f:c642]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e92fa4570fsm10952198a91.30.2024.11.04.21.54.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Nov 2024 21:54:22 -0800 (PST) From: Hironori KIKUCHI To: linux-kernel@vger.kernel.org Cc: Hironori KIKUCHI , Neil Armstrong , Jessica Zhang , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ryan Walklin , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH 6/7] dt-bindings: display: panel: Add YLM-LBV0400001X-V1 panel Date: Tue, 5 Nov 2024 14:52:34 +0900 Message-ID: <20241105055239.1577275-7-kikuchan98@gmail.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241105055239.1577275-1-kikuchan98@gmail.com> References: <20241105055239.1577275-1-kikuchan98@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The YLM-LBV0400001X-V1 panel is a display panel used in the Anbernic RG40XX series (H and V), a handheld gaming device from Anbernic. It is 4.00 inches in size (diagonally) with a resolution of 640x480. Signed-off-by: Hironori KIKUCHI --- .../panel/anbernic,ylm-lbv0400001x-v1.yaml | 65 +++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/anberni= c,ylm-lbv0400001x-v1.yaml diff --git a/Documentation/devicetree/bindings/display/panel/anbernic,ylm-l= bv0400001x-v1.yaml b/Documentation/devicetree/bindings/display/panel/anbern= ic,ylm-lbv0400001x-v1.yaml new file mode 100644 index 00000000000..68e1a705469 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/anbernic,ylm-lbv04000= 01x-v1.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/anbernic,ylm-lbv0400001x-= v1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Anbernic RG40XX H/V (YLM-LBV0400001X-V1) 4.00" 640x480 24-bit IPS L= CD panel + +maintainers: + - Hironori KIKUCHI + +allOf: + - $ref: panel-common.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + oneOf: + - const: anbernic,ylm-lbv0400001x-v1 + - items: + - enum: + - anbernic,rg40xx-panel + - const: anbernic,ylm-lbv0400001x-v1 + + reg: + maxItems: 1 + + spi-3wire: true + +required: + - compatible + - reg + - port + - power-supply + - reset-gpios + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + panel@0 { + compatible =3D "anbernic,ylm-lbv0400001x-v1"; + reg =3D <0>; + + spi-3wire; + spi-max-frequency =3D <3125000>; + + reset-gpios =3D <&pio 8 14 GPIO_ACTIVE_LOW>; // PI14 + + backlight =3D <&backlight>; + power-supply =3D <®_lcd>; + + port { + endpoint { + remote-endpoint =3D <&tcon_lcd0_out_lcd>; + }; + }; + }; + }; --=20 2.47.0 From nobody Sun Nov 24 14:41:18 2024 Received: from mail-pf1-f169.google.com (mail-pf1-f169.google.com [209.85.210.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CD151FF7A0; Tue, 5 Nov 2024 05:54:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730786069; cv=none; b=nL1yramvveZ06jaOp1NeeGRo2imgGX69CSR6BPMBRpTlpxWjZICQPy7fk1ae9rCK/MqRNAusq4hT3mg8uuCMB19Elmn2l+HASu65KsAZR6vWoyhl8nVBtPWwEespiYB+RMOe4oB5qSw4D/rheDVDPpZ77ozu/fOVU1uNG0v/znU= ARC-Message-Signature: i=1; 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Mon, 04 Nov 2024 21:54:26 -0800 (PST) From: Hironori KIKUCHI To: linux-kernel@vger.kernel.org Cc: Hironori KIKUCHI , Neil Armstrong , Jessica Zhang , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ryan Walklin , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH 7/7] drm: panel: nv3052c: Add YLM-LBV0400001X-V1 panel Date: Tue, 5 Nov 2024 14:52:35 +0900 Message-ID: <20241105055239.1577275-8-kikuchan98@gmail.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241105055239.1577275-1-kikuchan98@gmail.com> References: <20241105055239.1577275-1-kikuchan98@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The YLM-LBV0400001X-V1 panel is a display panel used in the Anbernic RG40XX series (H and V), a handheld gaming device from Anbernic. It is 4.00 inches in size (diagonally) with a resolution of 640x480. It's similar to YLM-LBV0345001H-V2, but different in size and its init-sequence. So add entry for the new panel. Signed-off-by: Hironori KIKUCHI --- .../gpu/drm/panel/panel-newvision-nv3052c.c | 211 ++++++++++++++++++ 1 file changed, 211 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c b/drivers/gpu/= drm/panel/panel-newvision-nv3052c.c index 57f6d5b1288..71f81d21465 100644 --- a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c +++ b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c @@ -778,6 +778,189 @@ static const struct nv3052c_reg ylm_lbv0345001h_v2_pa= nel_regs[] =3D { { 0x36, 0x0a }, // bgr =3D 1, ss =3D 1, gs =3D 0 }; =20 +static const struct nv3052c_reg ylm_lbv0400001x_v1_panel_regs[] =3D { + // EXTC Command set enable, select page 1 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x01 }, + // Mostly unknown registers + { 0xe3, 0x00 }, + { 0x0a, 0x01 }, + { 0x23, 0xa0 }, + { 0x25, 0x14 }, + { 0x28, 0x47 }, + { 0x29, 0x01 }, + { 0x2a, 0xdf }, + { 0x38, 0x9c }, + { 0x39, 0xa7 }, + { 0x3a, 0x47 }, + { 0x91, 0x77 }, + { 0x92, 0x77 }, + { 0x99, 0x52 }, + { 0x9b, 0x5b }, + { 0xa0, 0x55 }, + { 0xa1, 0x50 }, + { 0xa4, 0x9c }, + { 0xa7, 0x02 }, + { 0xa8, 0x01 }, + { 0xa9, 0x01 }, + { 0xaa, 0xfc }, + { 0xab, 0x28 }, + { 0xac, 0x06 }, + { 0xad, 0x06 }, + { 0xae, 0x06 }, + { 0xaf, 0x03 }, + { 0xb0, 0x08 }, + { 0xb1, 0x26 }, + { 0xb2, 0x28 }, + { 0xb3, 0x28 }, + { 0xb4, 0x03 }, + { 0xb5, 0x08 }, + { 0xb6, 0x26 }, + { 0xb7, 0x08 }, + { 0xb8, 0x26 }, + // EXTC Command set enable, select page 2 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x02 }, + // Set gray scale voltage to adjust gamma + { 0xb0, 0x05 }, // PGAMVR0 + { 0xb1, 0x12 }, // PGAMVR1 + { 0xb2, 0x13 }, // PGAMVR2 + { 0xb3, 0x2c }, // PGAMVR3 + { 0xb4, 0x2a }, // PGAMVR4 + { 0xb5, 0x37 }, // PGAMVR5 + { 0xb6, 0x27 }, // PGAMPR0 + { 0xb7, 0x42 }, // PGAMPR1 + { 0xb8, 0x0f }, // PGAMPK0 + { 0xb9, 0x06 }, // PGAMPK1 + { 0xba, 0x12 }, // PGAMPK2 + { 0xbb, 0x12 }, // PGAMPK3 + { 0xbc, 0x13 }, // PGAMPK4 + { 0xbd, 0x15 }, // PGAMPK5 + { 0xbe, 0x1b }, // PGAMPK6 + { 0xbf, 0x14 }, // PGAMPK7 + { 0xc0, 0x1d }, // PGAMPK8 + { 0xc1, 0x09 }, // PGAMPK9 + { 0xd0, 0x02 }, // NGAMVR0 + { 0xd1, 0x1c }, // NGAMVR0 + { 0xd2, 0x1d }, // NGAMVR1 + { 0xd3, 0x36 }, // NGAMVR2 + { 0xd4, 0x34 }, // NGAMVR3 + { 0xd5, 0x32 }, // NGAMVR4 + { 0xd6, 0x25 }, // NGAMPR0 + { 0xd7, 0x40 }, // NGAMPR1 + { 0xd8, 0x0d }, // NGAMPK0 + { 0xd9, 0x04 }, // NGAMPK1 + { 0xda, 0x12 }, // NGAMPK2 + { 0xdb, 0x12 }, // NGAMPK3 + { 0xdc, 0x13 }, // NGAMPK4 + { 0xdd, 0x15 }, // NGAMPK5 + { 0xde, 0x15 }, // NGAMPK6 + { 0xdf, 0x0c }, // NGAMPK7 + { 0xe0, 0x13 }, // NGAMPK8 + { 0xe1, 0x07 }, // NGAMPK9 + // EXTC Command set enable, select page 3 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x03 }, + // Mostly unknown registers + { 0x08, 0x0a }, + { 0x09, 0x0b }, + { 0x30, 0x00 }, + { 0x31, 0x00 }, + { 0x32, 0x00 }, + { 0x33, 0x00 }, + { 0x34, 0x61 }, + { 0x35, 0xd4 }, + { 0x36, 0x24 }, + { 0x37, 0x03 }, + { 0x40, 0x0d }, + { 0x41, 0x0e }, + { 0x42, 0x0f }, + { 0x43, 0x10 }, + { 0x44, 0x11 }, + { 0x45, 0xf4 }, + { 0x46, 0xf5 }, + { 0x47, 0x11 }, + { 0x48, 0xf6 }, + { 0x49, 0xf7 }, + { 0x50, 0x11 }, + { 0x51, 0x12 }, + { 0x52, 0x13 }, + { 0x53, 0x14 }, + { 0x54, 0x11 }, + { 0x55, 0xf8 }, + { 0x56, 0xf9 }, + { 0x57, 0x11 }, + { 0x58, 0xfa }, + { 0x59, 0xfb }, + { 0x60, 0x05 }, + { 0x61, 0x05 }, + { 0x65, 0x0a }, + { 0x66, 0x0a }, + { 0x82, 0x1e }, + { 0x83, 0x1f }, + { 0x84, 0x11 }, + { 0x85, 0x02 }, + { 0x86, 0x1e }, + { 0x87, 0x1e }, + { 0x88, 0x1f }, + { 0x89, 0x0e }, + { 0x8a, 0x0e }, + { 0x8b, 0x10 }, + { 0x8c, 0x10 }, + { 0x8d, 0x0a }, + { 0x8e, 0x0a }, + { 0x8f, 0x0c }, + { 0x90, 0x0c }, + { 0x98, 0x1e }, + { 0x99, 0x1f }, + { 0x9a, 0x11 }, + { 0x9b, 0x01 }, + { 0x9c, 0x1e }, + { 0x9d, 0x1e }, + { 0x9e, 0x1f }, + { 0x9f, 0x0d }, + { 0xa0, 0x0d }, + { 0xa1, 0x0f }, + { 0xa2, 0x0f }, + { 0xa3, 0x09 }, + { 0xa4, 0x09 }, + { 0xa5, 0x0b }, + { 0xa6, 0x0b }, + { 0xb2, 0x1f }, + { 0xb3, 0x1e }, + { 0xb4, 0x11 }, + { 0xb5, 0x01 }, + { 0xb6, 0x1e }, + { 0xb7, 0x1e }, + { 0xb8, 0x1f }, + { 0xb9, 0x0b }, + { 0xba, 0x0b }, + { 0xbb, 0x09 }, + { 0xbc, 0x09 }, + { 0xbd, 0x0f }, + { 0xbe, 0x0f }, + { 0xbf, 0x0d }, + { 0xc0, 0x0d }, + { 0xc8, 0x1f }, + { 0xc9, 0x1e }, + { 0xca, 0x11 }, + { 0xcb, 0x02 }, + { 0xcc, 0x1e }, + { 0xcd, 0x1e }, + { 0xce, 0x1f }, + { 0xcf, 0x0c }, + { 0xd0, 0x0c }, + { 0xd1, 0x0a }, + { 0xd2, 0x0a }, + { 0xd3, 0x10 }, + { 0xd4, 0x10 }, + { 0xd5, 0x0e }, + { 0xd6, 0x0e }, + // EXTC Command set enable, select page 0 + { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x00 }, + // Interface Pixel Format + { 0x3a, 0x77 }, + // Display Access Control + { 0x36, 0x0a }, // bgr =3D 1, ss =3D 1, gs =3D 0 +}; + static inline struct nv3052c *to_nv3052c(struct drm_panel *panel) { return container_of(panel, struct nv3052c, panel); @@ -1045,6 +1228,21 @@ static const struct drm_display_mode ylm_lbv0345001h= _v2_mode[] =3D { }, }; =20 +static const struct drm_display_mode ylm_lbv0400001x_v1_mode[] =3D { + { + .clock =3D 24000, + .hdisplay =3D 640, + .hsync_start =3D 640 + 64, + .hsync_end =3D 640 + 64 + 20, + .htotal =3D 640 + 64 + 20 + 46, + .vdisplay =3D 480, + .vsync_start =3D 480 + 21, + .vsync_end =3D 480 + 21 + 4, + .vtotal =3D 480 + 21 + 4 + 15, + .flags =3D DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, + }, +}; + static const struct nv3052c_panel_info ltk035c5444t_panel_info =3D { .display_modes =3D ltk035c5444t_modes, .num_modes =3D ARRAY_SIZE(ltk035c5444t_modes), @@ -1089,11 +1287,23 @@ static const struct nv3052c_panel_info ylm_lbv03450= 01h_v2_panel_info =3D { .panel_regs_len =3D ARRAY_SIZE(ylm_lbv0345001h_v2_panel_regs), }; =20 +static const struct nv3052c_panel_info ylm_lbv0400001x_v1_panel_info =3D { + .display_modes =3D ylm_lbv0400001x_v1_mode, + .num_modes =3D ARRAY_SIZE(ylm_lbv0400001x_v1_mode), + .width_mm =3D 81, + .height_mm =3D 61, + .bus_format =3D MEDIA_BUS_FMT_RGB888_1X24, + .bus_flags =3D DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, + .panel_regs =3D ylm_lbv0400001x_v1_panel_regs, + .panel_regs_len =3D ARRAY_SIZE(ylm_lbv0400001x_v1_panel_regs), +}; + static const struct spi_device_id nv3052c_ids[] =3D { { "ltk035c5444t", }, { "fs035vg158", }, { "wl-355608-a8", }, { "ylm-lbv0345001h-v2", }, + { "ylm-lbv0400001x-v1", }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(spi, nv3052c_ids); @@ -1103,6 +1313,7 @@ static const struct of_device_id nv3052c_of_match[] = =3D { { .compatible =3D "fascontek,fs035vg158", .data =3D &fs035vg158_panel_inf= o }, { .compatible =3D "anbernic,wl-355608-a8", .data =3D &wl_355608_a8_panel_= info }, { .compatible =3D "anbernic,ylm-lbv0345001h-v2", .data =3D &ylm_lbv034500= 1h_v2_panel_info }, + { .compatible =3D "anbernic,ylm-lbv0400001x-v1", .data =3D &ylm_lbv040000= 1x_v1_panel_info }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, nv3052c_of_match); --=20 2.47.0