From nobody Sun Nov 24 13:50:27 2024 Received: from mx07-00376f01.pphosted.com (mx07-00376f01.pphosted.com [185.132.180.163]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3072015EFB9; Tue, 5 Nov 2024 15:59:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.180.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730822391; cv=none; b=tb8uhm+ZxU10j6Ee13myUE89+oDvxhHswFIc25x/Nt+Gkc6T8vup+B9o/MCYaYu3zhx8bQKFTKk464HLCdjTnCDaAPo7jv/JrcPCRoLB0HUMqc1bsTxOhz9qEncQW+UXCF6rAeyx0Zzk8BTZ9t+2JSSfLAfnNAe1QjvnIxQT3yM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730822391; c=relaxed/simple; bh=T96nTjTV5E0LMA3CCGCYuYZBuIDWL+aH7LYDFcmSYI0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=GHWVLpAcR6dwDIN0GvgEQl7MY+fVgy0DU+f41sp8T/eDWscjTwafA9+K6P+Gvy+2FBJmPopW2ytuniVkuDxtaE1rC122UXRXA4rnvcLtUtF+Ezo2C/uoFkikFZlkL4WPXHXNVVYkY+cYmMVyBpb6Og1s3+f0QiellU+lBCsTQHg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=imgtec.com; spf=pass smtp.mailfrom=imgtec.com; dkim=pass (2048-bit key) header.d=imgtec.com header.i=@imgtec.com header.b=RwO8vRwZ; arc=none smtp.client-ip=185.132.180.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=imgtec.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=imgtec.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=imgtec.com header.i=@imgtec.com header.b="RwO8vRwZ" Received: from pps.filterd (m0168889.ppops.net [127.0.0.1]) by mx07-00376f01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4A5DjjHV028612; Tue, 5 Nov 2024 15:58:29 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=imgtec.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=dk201812; bh=5 pbSSrfjHXefHVKFb3svyxVLRw8pIkOduf2jm/buLkA=; b=RwO8vRwZOqx86GCA0 j/RXyro0++J70P6wCRaJDFmmwH2mHbKQdoaXYce2OKSll1Nb5sBCNsSsyDTH6h0O 5N+mYJjzZieTwczq/C306VuIpSiYxHoY4jiW7rIZvPGzghYB3XbG94m5C9p6d36V +jpfu1ubvH+nbZue62nS4oozgAEqorx+E9y647NrVOz6fjt9eFqphmepoXIyhMUZ TP+nSjoDWkx5XT0T+zzfXlhKYGU2drptIbEqJOxmqaeO1aaaAbwbN2wZOXUZJ1WU yc1IE8ef7mB8UytYdJNvrtnyEfbFMZua9LAEBlwFgmHqbN7PeFBi3Gd7Qgy4cCRP DQDuA== Received: from hhmail05.hh.imgtec.org (83-244-153-141.cust-83.exponential-e.net [83.244.153.141]) by mx07-00376f01.pphosted.com (PPS) with ESMTPS id 42nd212jtx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 05 Nov 2024 15:58:29 +0000 (GMT) Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa (172.25.16.114) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Tue, 5 Nov 2024 15:58:28 +0000 From: Matt Coster Date: Tue, 5 Nov 2024 15:58:12 +0000 Subject: [PATCH 06/21] drm/imagination: Add power domain control Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241105-sets-bxs-4-64-patch-v1-v1-6-4ed30e865892@imgtec.com> References: <20241105-sets-bxs-4-64-patch-v1-v1-0-4ed30e865892@imgtec.com> In-Reply-To: <20241105-sets-bxs-4-64-patch-v1-v1-0-4ed30e865892@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7010; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=T96nTjTV5E0LMA3CCGCYuYZBuIDWL+aH7LYDFcmSYI0=; b=owGbwMvMwCFWuUfy8817WRsYT6slMaRrOcxVV9muEXJUWrn+l27k5SPN/JNY47u4jqlZaH+fw JMhWZLbUcrCIMbBICumyLJjheUKtT9qWhI3fhXDzGFlAhnCwMUpABMRS2FkONnFJmcnv5H1Tjz3 s8qveq/jTcNvbK6/bqfAL3m3ZYbfHIZ/lo+VX8St9px8vd/F4HFlrtFVHrusKIHqbtblzZvbg7k 5AA== X-Developer-Key: i=matt.coster@imgtec.com; a=openpgp; fpr=05A40CFCE7269D61D97100A1747F0A9036F90DFA X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Authority-Analysis: v=2.4 cv=Q9aA4J2a c=1 sm=1 tr=0 ts=672a40a5 cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=hzDjp0mCheYA:10 a=IkcTkHD0fZMA:10 a=VlfZXiiP6vEA:10 a=r_1tXGB3AAAA:8 a=Iu228gY9Y64KKxsXE-4A:9 a=QEXdDO2ut3YA:10 a=t8nPyN_e6usw4ciXM-Pk:22 X-Proofpoint-GUID: De12S55yv_4lGSCwt3f1sYhXxp_5qrFo X-Proofpoint-ORIG-GUID: De12S55yv_4lGSCwt3f1sYhXxp_5qrFo The first supported GPU only used a single power domain so this was automatically handled by the device runtime. In order to support multiple power domains, they must be enumerated from devicetree and linked to both the GPU device and each other to ensure correct power sequencing at start time. For all Imagination Rogue GPUs, power domains are named "a", "b", etc. and the sequence A->B->... is always valid for startup with the reverse true for shutdown. Note this is not always the *only* valid sequence, but it's simple and does not require special-casing for different GPU power topologies. Signed-off-by: Matt Coster --- drivers/gpu/drm/imagination/pvr_device.h | 8 +++ drivers/gpu/drm/imagination/pvr_drv.c | 10 ++- drivers/gpu/drm/imagination/pvr_power.c | 114 +++++++++++++++++++++++++++= ++++ drivers/gpu/drm/imagination/pvr_power.h | 3 + 4 files changed, 134 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/imagination/pvr_device.h b/drivers/gpu/drm/ima= gination/pvr_device.h index b574e23d484ba80785a2220e046dbab3f91f6e15..470945ccfcac7ce91161aa6c70d= 33177fbb3533f 100644 --- a/drivers/gpu/drm/imagination/pvr_device.h +++ b/drivers/gpu/drm/imagination/pvr_device.h @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -130,6 +131,13 @@ struct pvr_device { */ struct clk *mem_clk; =20 + struct pvr_device_power { + struct device **domain_devs; + struct device_link **domain_links; + + u32 domain_count; + } power; + /** @irq: IRQ number. */ int irq; =20 diff --git a/drivers/gpu/drm/imagination/pvr_drv.c b/drivers/gpu/drm/imagin= ation/pvr_drv.c index fbd8802abcf1271e260209957d95ea705dbe7f14..1ab97933e14f20ee3fbf603c23b= 8dde2d33572c2 100644 --- a/drivers/gpu/drm/imagination/pvr_drv.c +++ b/drivers/gpu/drm/imagination/pvr_drv.c @@ -1409,13 +1409,17 @@ pvr_probe(struct platform_device *plat_dev) =20 platform_set_drvdata(plat_dev, drm_dev); =20 + err =3D pvr_power_domains_init(pvr_dev); + if (err) + goto err_context_fini; + init_rwsem(&pvr_dev->reset_sem); =20 pvr_context_device_init(pvr_dev); =20 err =3D pvr_queue_device_init(pvr_dev); if (err) - goto err_context_fini; + goto err_power_domains_fini; =20 devm_pm_runtime_enable(&plat_dev->dev); pm_runtime_mark_last_busy(&plat_dev->dev); @@ -1448,6 +1452,9 @@ pvr_probe(struct platform_device *plat_dev) err_context_fini: pvr_context_device_fini(pvr_dev); =20 +err_power_domains_fini: + pvr_power_domains_fini(pvr_dev); + return err; } =20 @@ -1468,6 +1475,7 @@ static void pvr_remove(struct platform_device *plat_d= ev) pvr_watchdog_fini(pvr_dev); pvr_queue_device_fini(pvr_dev); pvr_context_device_fini(pvr_dev); + pvr_power_domains_fini(pvr_dev); } =20 static const struct of_device_id dt_match[] =3D { diff --git a/drivers/gpu/drm/imagination/pvr_power.c b/drivers/gpu/drm/imag= ination/pvr_power.c index ba7816fd28ec77e6ca5ce408302a413ce1afeb6e..19b079b357df78e8bcdecfa377f= c9c05b6e8e4b0 100644 --- a/drivers/gpu/drm/imagination/pvr_power.c +++ b/drivers/gpu/drm/imagination/pvr_power.c @@ -10,10 +10,13 @@ =20 #include #include +#include #include #include #include +#include #include +#include #include #include #include @@ -431,3 +434,114 @@ pvr_watchdog_fini(struct pvr_device *pvr_dev) { cancel_delayed_work_sync(&pvr_dev->watchdog.work); } + +int pvr_power_domains_init(struct pvr_device *pvr_dev) +{ + struct device *dev =3D from_pvr_device(pvr_dev)->dev; + + struct device_link **domain_links __free(kfree) =3D NULL; + struct device **domain_devs __free(kfree) =3D NULL; + int domain_count; + int link_count; + + char dev_name[2] =3D "a"; + int err; + int i; + + domain_count =3D of_count_phandle_with_args(dev->of_node, "power-domains", + "#power-domain-cells"); + if (domain_count < 0) + return domain_count; + + if (domain_count <=3D 1) + return 0; + + link_count =3D domain_count + (domain_count - 1); + + domain_devs =3D kcalloc(domain_count, sizeof(*domain_devs), GFP_KERNEL); + if (!domain_devs) + return -ENOMEM; + + domain_links =3D kcalloc(link_count, sizeof(*domain_links), GFP_KERNEL); + if (!domain_links) + return -ENOMEM; + + for (i =3D 0; i < domain_count; i++) { + struct device *domain_dev; + + dev_name[0] =3D 'a' + i; + domain_dev =3D dev_pm_domain_attach_by_name(dev, dev_name); + if (IS_ERR_OR_NULL(domain_dev)) { + err =3D domain_dev ? PTR_ERR(domain_dev) : -ENODEV; + goto err_detach; + } + + domain_devs[i] =3D domain_dev; + } + + for (i =3D 0; i < domain_count; i++) { + struct device_link *link; + + link =3D device_link_add(dev, domain_devs[i], DL_FLAG_STATELESS | DL_FLA= G_PM_RUNTIME); + if (!link) { + err =3D -ENODEV; + goto err_unlink; + } + + domain_links[i] =3D link; + } + + for (i =3D domain_count; i < link_count; i++) { + struct device_link *link; + + link =3D device_link_add(domain_devs[i - domain_count + 1], + domain_devs[i - domain_count], + DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME); + if (!link) { + err =3D -ENODEV; + goto err_unlink; + } + + domain_links[i] =3D link; + } + + pvr_dev->power =3D (struct pvr_device_power){ + .domain_devs =3D no_free_ptr(domain_devs), + .domain_links =3D no_free_ptr(domain_links), + .domain_count =3D domain_count, + }; + + return 0; + +err_unlink: + while (--i >=3D 0) + device_link_del(domain_links[i]); + + i =3D domain_count; + +err_detach: + while (--i >=3D 0) + dev_pm_domain_detach(domain_devs[i], true); + + return err; +} + +void pvr_power_domains_fini(struct pvr_device *pvr_dev) +{ + const int domain_count =3D pvr_dev->power.domain_count; + + int i =3D domain_count + (domain_count - 1); + + while (--i >=3D 0) + device_link_del(pvr_dev->power.domain_links[i]); + + i =3D domain_count; + + while (--i >=3D 0) + dev_pm_domain_detach(pvr_dev->power.domain_devs[i], true); + + kfree(pvr_dev->power.domain_links); + kfree(pvr_dev->power.domain_devs); + + pvr_dev->power =3D (struct pvr_device_power){ 0 }; +} diff --git a/drivers/gpu/drm/imagination/pvr_power.h b/drivers/gpu/drm/imag= ination/pvr_power.h index 9a9312dcb2dab7d36ee8ff7f69e69d126c5469a9..ada85674a7ca762dcf92df40424= 230e1c3910342 100644 --- a/drivers/gpu/drm/imagination/pvr_power.h +++ b/drivers/gpu/drm/imagination/pvr_power.h @@ -38,4 +38,7 @@ pvr_power_put(struct pvr_device *pvr_dev) return pm_runtime_put(drm_dev->dev); } =20 +int pvr_power_domains_init(struct pvr_device *pvr_dev); +void pvr_power_domains_fini(struct pvr_device *pvr_dev); + #endif /* PVR_POWER_H */ --=20 2.47.0