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Tue, 05 Nov 2024 15:58:40 +0000 (GMT) Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa (172.25.16.114) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Tue, 5 Nov 2024 15:58:39 +0000 From: Matt Coster Date: Tue, 5 Nov 2024 15:58:27 +0000 Subject: [PATCH 21/21] arm64: dts: ti: k3-j721s2: Add GPU node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241105-sets-bxs-4-64-patch-v1-v1-21-4ed30e865892@imgtec.com> References: <20241105-sets-bxs-4-64-patch-v1-v1-0-4ed30e865892@imgtec.com> In-Reply-To: <20241105-sets-bxs-4-64-patch-v1-v1-0-4ed30e865892@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1576; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=H8DIARHN5LAhn899AhP+EfNJuCgcAkEDx/aJO8V/l9U=; b=owGbwMvMwCFWuUfy8817WRsYT6slMaRrOcy/tSIl2eOW2/xHuTbqlRpc2gol/n0l+jVaK9blT fuZqXG3o5SFQYyDQVZMkWXHCssVan/UtCRu/CqGmcPKBDKEgYtTACbido/hf+D5a+F8zl9zFe7o vnCa7NVxfv06I8vsj9MrItvfLInIL2b4H/I9f56zcx+Pijh7ijN70j5bB/982XrZd/UdK8222Qe yAwA= X-Developer-Key: i=matt.coster@imgtec.com; a=openpgp; fpr=05A40CFCE7269D61D97100A1747F0A9036F90DFA X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Authority-Analysis: v=2.4 cv=Q9aA4J2a c=1 sm=1 tr=0 ts=672a40b0 cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=hzDjp0mCheYA:10 a=IkcTkHD0fZMA:10 a=VlfZXiiP6vEA:10 a=sozttTNsAAAA:8 a=r_1tXGB3AAAA:8 a=rLJv8WYccUdZFC7c5UsA:9 a=QEXdDO2ut3YA:10 a=S-JV1fTmrHgA:10 a=j2-svP0xy3wA:10 a=t8nPyN_e6usw4ciXM-Pk:22 X-Proofpoint-GUID: LOeMeKqUdp1x6fjOdbEc-ZDE_Y0zQzjx X-Proofpoint-ORIG-GUID: LOeMeKqUdp1x6fjOdbEc-ZDE_Y0zQzjx The J721S2 binding is based on the TI downstream binding in 54b0f2a00d92 ("arm64: dts: ti: k3-j721s2-main: add gpu node") from [1] but with updated compatible strings. The clock[2] and power[3] indices were verified from docs, but the source of the interrupt index remains elusive. References for indices: clocks[1], interrupts[2], power[3]. [1]: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel [2]: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/j721s2/clocks.html [3]: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/j721s2/devices.html Signed-off-by: Matt Coster --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index 9ed6949b40e9dfafdaf6861944b0b128b053a44f..b2441ac9847d7e64d847a5cc220= d1a79d0254bc9 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -2047,4 +2047,16 @@ watchdog8: watchdog@23f0000 { /* reserved for MAIN_R5F1_1 */ status =3D "reserved"; }; + + gpu: gpu@4e20000000 { + compatible =3D "ti,j721s2-gpu", "img,img-bxs-4-64", "img,img-rogue"; + reg =3D /bits/ 64 <0x4e20000000 0x80000>; + clocks =3D <&k3_clks 130 1>; + clock-names =3D "core"; + interrupts =3D ; + power-domains =3D <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 373 TI_SCI_PD_EXCLUSIVE>; + power-domain-names =3D "a", "b"; + dma-coherent; + }; }; --=20 2.47.0