From nobody Sun Nov 24 13:46:15 2024 Received: from mx08-00376f01.pphosted.com (mx08-00376f01.pphosted.com [91.207.212.86]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 04EDA1DD0DF; Tue, 5 Nov 2024 15:59:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.86 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730822393; cv=none; b=R7VBlFQw0FuTpskoEzEEw8xpQlQC18e/4gxLF3ZGGd+9ZkaKkYu6NjwluqLM7z48hMteYc6X2kheG4BzksHoKA/Bus/8zUE7wEe8B3Ajv76ok91Mw1xs3cdFEnuGK9powq35ECHhyf18tpjd3DNQNNc/LkVQJ4a1XPAgQAyPRNA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730822393; c=relaxed/simple; bh=7Jh8O6t/depA4EIHEpaCD9RLKpiLBdRO6OyeujP1TNw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=kRi6igIjuXW5wB/vH1VYXRStKuhWRm5GpPQlfjiSUcgdGos5QBJVCFS+supdP/4aBvRyglEreSE37VD7z3dV1vf54zuGKRb3lGeQU9GFMnIYJCSm4m5mQd58b2//FfpQ4+iWdrSFW5TGvk2C7Gdm20n8szGZXns63eA5J2Tjr8I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=imgtec.com; spf=pass smtp.mailfrom=imgtec.com; dkim=pass (2048-bit key) header.d=imgtec.com header.i=@imgtec.com header.b=B+9dEdqs; arc=none smtp.client-ip=91.207.212.86 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=imgtec.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=imgtec.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=imgtec.com header.i=@imgtec.com header.b="B+9dEdqs" Received: from pps.filterd (m0168888.ppops.net [127.0.0.1]) by mx08-00376f01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4A5EF3v6003827; Tue, 5 Nov 2024 15:58:39 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=imgtec.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=dk201812; bh=v TBNXwShOctAnRg444GiJWE4kZLTZvEaedRuNtFLN3I=; b=B+9dEdqsy7ci6naDA rPwVDC9hY6kmM4Rl0iWo97WhAzU1ZulMifDNAKxEUzitpXkfBx1nrrkHkqza0GBv 558F18NAD/cWq1nnd8wWCnhrcWmjebUkiIx21ycl7DlIuIxg34q8X5LqfLGJEUVw ZG/RlUQ8LLMXrqgUyUyR2h5iW5J3HKiZI7IymzBcfPAmeApUZeTbHpjUmMNUJhP1 MjJDzDijs+tFkUZyozFwGPACGOnVuxsXBNkWAKoZOELa3mqmH35D+jMiLXalkXVI EI4aLjiSDW16aHrGf/opKZ2uq+Nbr64AaHIngPBIF/R5CHDpUihvUX9LS1u3LB4U wtE3w== Received: from hhmail05.hh.imgtec.org (83-244-153-141.cust-83.exponential-e.net [83.244.153.141]) by mx08-00376f01.pphosted.com (PPS) with ESMTPS id 42nb7wta0y-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 05 Nov 2024 15:58:39 +0000 (GMT) Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa (172.25.16.114) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Tue, 5 Nov 2024 15:58:37 +0000 From: Matt Coster Date: Tue, 5 Nov 2024 15:58:25 +0000 Subject: [PATCH 19/21] drm/imagination: Add device_memory_force_cpu_cached override Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241105-sets-bxs-4-64-patch-v1-v1-19-4ed30e865892@imgtec.com> References: <20241105-sets-bxs-4-64-patch-v1-v1-0-4ed30e865892@imgtec.com> In-Reply-To: <20241105-sets-bxs-4-64-patch-v1-v1-0-4ed30e865892@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6916; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=7Jh8O6t/depA4EIHEpaCD9RLKpiLBdRO6OyeujP1TNw=; b=owGbwMvMwCFWuUfy8817WRsYT6slMaRrOcwvq71c8PzusrqEjxI2N0/zef164rGpa//6XZcO5 t3yUryd1VHKwiDGwSArpsiyY4XlCrU/aloSN34Vw8xhZQIZwsDFKQATeaDA8M9y4/HkUyaLqn4U 7O1cJPq184xMl/UvDhm9TVu3Vm3Wc6xmZJhxulHKeVvG8rr+hfG2Gi07eZ8trzmd/sTL9OKBowo ee7kB X-Developer-Key: i=matt.coster@imgtec.com; a=openpgp; fpr=05A40CFCE7269D61D97100A1747F0A9036F90DFA X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Authority-Analysis: v=2.4 cv=ddzS3mXe c=1 sm=1 tr=0 ts=672a40af cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=hzDjp0mCheYA:10 a=IkcTkHD0fZMA:10 a=VlfZXiiP6vEA:10 a=r_1tXGB3AAAA:8 a=ZhBkjoDcyXaoxMow2pUA:9 a=QEXdDO2ut3YA:10 a=t8nPyN_e6usw4ciXM-Pk:22 X-Proofpoint-GUID: mursqpEUzF4oJanQnaLTYxiOI0KBYfu0 X-Proofpoint-ORIG-GUID: mursqpEUzF4oJanQnaLTYxiOI0KBYfu0 The TI k3-j721s2 platform has a bug relating to cache snooping on the AXI ACE-Lite interface. Disabling cache snooping altogether would also resolve the issue, but is considered more of a performance hit. Given the platform is dma-coherent, forcing all device-accessible memory allocations through the CPU cache is the preferred solution. Implement this workaround so that it can later be enabled for the TI k3-j721s2 platform. Signed-off-by: Matt Coster --- drivers/gpu/drm/imagination/pvr_device.c | 11 ++++++++++- drivers/gpu/drm/imagination/pvr_device.h | 11 +++++++++++ drivers/gpu/drm/imagination/pvr_drv.c | 2 +- drivers/gpu/drm/imagination/pvr_gem.c | 3 +++ drivers/gpu/drm/imagination/pvr_gem.h | 7 +++++-- drivers/gpu/drm/imagination/pvr_mmu.c | 7 ++++++- 6 files changed, 36 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_device.c b/drivers/gpu/drm/ima= gination/pvr_device.c index 2ce46b9a8ab7609faebeeb4e7820751b00047806..ffc177c383c1be16061eff0290c= 347918b0991f7 100644 --- a/drivers/gpu/drm/imagination/pvr_device.c +++ b/drivers/gpu/drm/imagination/pvr_device.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -635,6 +636,7 @@ bool pvr_device_overrides_validate(struct pvr_device *pvr_dev, const struct pvr_device_overrides *overrides) { + struct drm_device *drm_dev =3D from_pvr_device(pvr_dev); bool ret =3D true; =20 /* @@ -643,7 +645,14 @@ pvr_device_overrides_validate(struct pvr_device *pvr_d= ev, * * Note that this function may be called early during device initializati= on * so it should not be assumed that @pvr_dev is ready for normal use yet. - */ + */ + + if (overrides->device_memory_force_cpu_cached && + device_get_dma_attr(drm_dev->dev) !=3D DEV_DMA_COHERENT) { + drm_err(drm_dev, + "Specifying device_memory_force_cpu_cached override without dma-coheren= t attribute is unsupported."); + ret =3D false; + } =20 return ret; } diff --git a/drivers/gpu/drm/imagination/pvr_device.h b/drivers/gpu/drm/ima= gination/pvr_device.h index ad0a02a37154099542247dfc62f411c10f4e41f4..7ae14899db24f4c747e8cf4d61d= 252eb403713f4 100644 --- a/drivers/gpu/drm/imagination/pvr_device.h +++ b/drivers/gpu/drm/imagination/pvr_device.h @@ -60,8 +60,19 @@ struct pvr_fw_version { /** * struct pvr_device_overrides - Hardware-level overrides loaded from * MODULE_DEVICE_TABLE() or similar. + * + * @device_memory_force_cpu_cached: By default, all device memory buffer o= bjects + * are mapped write-combined on the CPU (see %PVR_BO_CPU_CACHED) including= MMU + * page table backing pages which do not use the regular device memory obj= ects. + * This override forces all CPU mappings to be mapped cached instead. Sinc= e this + * could require additional cache maintenance operations to be performed, + * pvr_device_overrides_validate() ensures that the dma-coherent attribute= is + * set when this override is specified. Required on some TI platforms wher= e a + * bug causes device-to-cpu cache snooping to behave incorrectly when + * interacting with cpu-uncached memory. */ struct pvr_device_overrides { + bool device_memory_force_cpu_cached; }; =20 /** diff --git a/drivers/gpu/drm/imagination/pvr_drv.c b/drivers/gpu/drm/imagin= ation/pvr_drv.c index b56ee2cda9b54c4388a6eef38b0ff81acdb05874..e074cfb0d2055b5387dbb142ca9= 72108977f9854 100644 --- a/drivers/gpu/drm/imagination/pvr_drv.c +++ b/drivers/gpu/drm/imagination/pvr_drv.c @@ -1490,7 +1490,7 @@ static void pvr_remove(struct platform_device *plat_d= ev) pvr_power_domains_fini(pvr_dev); } =20 -static const struct pvr_device_overrides pvr_device_overrides_default =3D = {}; +static const struct pvr_device_overrides pvr_device_overrides_default =3D = { 0 }; =20 /* * Always specify &pvr_device_overrides_default instead of %NULL for &stru= ct of_device_id->data so diff --git a/drivers/gpu/drm/imagination/pvr_gem.c b/drivers/gpu/drm/imagin= ation/pvr_gem.c index 6a8c81fe8c1e85c2130a4fe90fce35b6a2be35aa..c67c30518f89af3de2e617a9b65= e5cd78870fa2c 100644 --- a/drivers/gpu/drm/imagination/pvr_gem.c +++ b/drivers/gpu/drm/imagination/pvr_gem.c @@ -345,6 +345,9 @@ pvr_gem_object_create(struct pvr_device *pvr_dev, size_= t size, u64 flags) if (size =3D=3D 0 || !pvr_gem_object_flags_validate(flags)) return ERR_PTR(-EINVAL); =20 + if (PVR_HAS_OVERRIDE(pvr_dev, device_memory_force_cpu_cached)) + flags |=3D PVR_BO_CPU_CACHED; + shmem_obj =3D drm_gem_shmem_create(from_pvr_device(pvr_dev), size); if (IS_ERR(shmem_obj)) return ERR_CAST(shmem_obj); diff --git a/drivers/gpu/drm/imagination/pvr_gem.h b/drivers/gpu/drm/imagin= ation/pvr_gem.h index e0e5ea509a2e88a437b8d241ea13c7bab2220f56..9b3cbcbe48dfbbc8be211a8a409= 699a43452e178 100644 --- a/drivers/gpu/drm/imagination/pvr_gem.h +++ b/drivers/gpu/drm/imagination/pvr_gem.h @@ -44,8 +44,11 @@ struct pvr_file; * Bits not defined anywhere are "undefined". * * CPU mapping options - * :PVR_BO_CPU_CACHED: By default, all GEM objects are mapped write-com= bined on the CPU. Set this - * flag to override this behaviour and map the object cached. + * :PVR_BO_CPU_CACHED: By default, all GEM objects are mapped write-com= bined on the CPU. Set + * this flag to override this behaviour and map the object cached. If + * &struct pvr_device_overrides->device_memory_force_cpu_cached is s= pecified, all allocations + * will be mapped as if this flag was set. This does not require any= additional consideration + * at allocation time since the override is only valid if the dma-co= herent attribute is set. * * Firmware options * :PVR_BO_FW_NO_CLEAR_ON_RESET: By default, all FW objects are cleared= and reinitialised on hard diff --git a/drivers/gpu/drm/imagination/pvr_mmu.c b/drivers/gpu/drm/imagin= ation/pvr_mmu.c index 4fe70610ed94cf707e631f8148af081a94f97327..7c7deb29b735308eaed26900f2f= 54a838382c255 100644 --- a/drivers/gpu/drm/imagination/pvr_mmu.c +++ b/drivers/gpu/drm/imagination/pvr_mmu.c @@ -259,6 +259,7 @@ pvr_mmu_backing_page_init(struct pvr_mmu_backing_page *= page, struct device *dev =3D from_pvr_device(pvr_dev)->dev; =20 struct page *raw_page; + pgprot_t prot; int err; =20 dma_addr_t dma_addr; @@ -268,7 +269,11 @@ pvr_mmu_backing_page_init(struct pvr_mmu_backing_page = *page, if (!raw_page) return -ENOMEM; =20 - host_ptr =3D vmap(&raw_page, 1, VM_MAP, pgprot_writecombine(PAGE_KERNEL)); + prot =3D PAGE_KERNEL; + if (!PVR_HAS_OVERRIDE(pvr_dev, device_memory_force_cpu_cached)) + prot =3D pgprot_writecombine(prot); + + host_ptr =3D vmap(&raw_page, 1, VM_MAP, prot); if (!host_ptr) { err =3D -ENOMEM; goto err_free_page; --=20 2.47.0