From nobody Sun Nov 24 14:38:11 2024 Received: from mx07-00376f01.pphosted.com (mx07-00376f01.pphosted.com [185.132.180.163]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36FA8166F3D; Tue, 5 Nov 2024 15:59:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.180.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730822391; cv=none; b=KtcO5l9V0/8090TNCZV+EdpGpw1+3p0COteoCvAfCupE8KjPUs5p0sRXBB2SASLMOYc4UhRT2YvRbBU3sk0Grx3Ssh/YduuGgBCnSIbJctBb7kSbjTJItH4Jm7cIaF+MeMacgJ2ttwKm9A2/MJ1BmQWLbAdtKmuF8UhyosCNIz0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730822391; c=relaxed/simple; bh=UIrxOyYskkd2zV7XfHusZkCrqZMoV3h5lYs9UyJn5W0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=fzImplptBLkQ8uXBqkuc12ta1eVbIR8TWh3eThc+Y64Rs73XGlYFWjcdG51HAa4LWZF7E0kyTwC26IhN9yPzTZLZkD1aebY3nhE0VukTBOPErmdL5leZIMU75yb6NLhKOYyUzFXFA8oZYJMCLq8yvJTgY4qBMVafI2y+LqOhmGU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=imgtec.com; spf=pass smtp.mailfrom=imgtec.com; dkim=pass (2048-bit key) header.d=imgtec.com header.i=@imgtec.com header.b=CPFu4gtV; arc=none smtp.client-ip=185.132.180.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=imgtec.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=imgtec.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=imgtec.com header.i=@imgtec.com header.b="CPFu4gtV" Received: from pps.filterd (m0168889.ppops.net [127.0.0.1]) by mx07-00376f01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4A5FtUqF005589; Tue, 5 Nov 2024 15:58:37 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=imgtec.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=dk201812; bh=O yuAtQyhTSA7LS3dSL0vetYnuP2tfqRP4xODv6XglSg=; b=CPFu4gtV3fpBnDk2V G+V92zsH//N2nKZoikGD3vayw13hSM1Hcn2babztnT/nK8WBYdZLQe6nTHvm9863 sGrN9lMoqWkgEzFHG9E9FhltWfmBNPByMRKf8SCoazT6XgQLLljNs+4Tsz9JobCP +QeIB9uSsM/JC3mr5LPF6VAhyLFRu92Tw09mH6CtxK/qoxRFdg4Y211/UXzGqL5+ i9oFk8k888NNnzf6v1U4SYXRObsEGdxtOCgDTv69nXIEv4L74+BRaBLp098Kvurh I/QiDeZZ6GjuUqR58JNQRiJ9EZkK1jldAAXxx4v2VytgA46vad95M+w8fhcRsDgg MLt4w== Received: from hhmail05.hh.imgtec.org (83-244-153-141.cust-83.exponential-e.net [83.244.153.141]) by mx07-00376f01.pphosted.com (PPS) with ESMTPS id 42nd212ju1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 05 Nov 2024 15:58:36 +0000 (GMT) Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa (172.25.16.114) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Tue, 5 Nov 2024 15:58:35 +0000 From: Matt Coster Date: Tue, 5 Nov 2024 15:58:22 +0000 Subject: [PATCH 16/21] drm/imagination: Move ELF fw utils to common file Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241105-sets-bxs-4-64-patch-v1-v1-16-4ed30e865892@imgtec.com> References: <20241105-sets-bxs-4-64-patch-v1-v1-0-4ed30e865892@imgtec.com> In-Reply-To: <20241105-sets-bxs-4-64-patch-v1-v1-0-4ed30e865892@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7100; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=UIrxOyYskkd2zV7XfHusZkCrqZMoV3h5lYs9UyJn5W0=; b=owGbwMvMwCFWuUfy8817WRsYT6slMaRrOczTnfb0pbFk06G9N4687Pxsu4ntC//T3n+lIvkXP QT28X+W6ShlYRDjYJAVU2TZscJyhdofNS2JG7+KYeawMoEMYeDiFICJ/HFnZNgdbbPQ2f9jkvXZ y4w10979u3XiptQl3xqlOs7ZyT+v3Wdi+KepkCDn0Lvj4yPRnr6r0idLw/f9mf36p0TlwcCYKWd 6d7ADAA== X-Developer-Key: i=matt.coster@imgtec.com; a=openpgp; fpr=05A40CFCE7269D61D97100A1747F0A9036F90DFA X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Authority-Analysis: v=2.4 cv=Q9aA4J2a c=1 sm=1 tr=0 ts=672a40ac cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=hzDjp0mCheYA:10 a=IkcTkHD0fZMA:10 a=VlfZXiiP6vEA:10 a=r_1tXGB3AAAA:8 a=nDXPDgtXl5tloLhz4E0A:9 a=QEXdDO2ut3YA:10 a=CMhdClSkCJESED5Bpcyf:22 a=t8nPyN_e6usw4ciXM-Pk:22 X-Proofpoint-GUID: NQ5F50QJAP-3yDJEPQ6WleE3Kb4qEiOe X-Proofpoint-ORIG-GUID: NQ5F50QJAP-3yDJEPQ6WleE3Kb4qEiOe Currently only MIPS firmware processors use ELF-formatted firmware. When adding support for RISC-V firmware processors, it will be useful to have ELF handling functions ready to go. Signed-off-by: Matt Coster --- drivers/gpu/drm/imagination/Makefile | 1 + drivers/gpu/drm/imagination/pvr_fw.h | 5 +++ drivers/gpu/drm/imagination/pvr_fw_mips.c | 59 +-------------------------- drivers/gpu/drm/imagination/pvr_fw_util.c | 67 +++++++++++++++++++++++++++= ++++ 4 files changed, 75 insertions(+), 57 deletions(-) diff --git a/drivers/gpu/drm/imagination/Makefile b/drivers/gpu/drm/imagina= tion/Makefile index 9bc6a3884c2239e44265f3cdebee149841b270de..077e4762c7c383b6e339da1584c= 3865d830ef8d6 100644 --- a/drivers/gpu/drm/imagination/Makefile +++ b/drivers/gpu/drm/imagination/Makefile @@ -16,6 +16,7 @@ powervr-y :=3D \ pvr_fw_mips.o \ pvr_fw_startstop.o \ pvr_fw_trace.o \ + pvr_fw_util.o \ pvr_gem.o \ pvr_hwrt.o \ pvr_job.o \ diff --git a/drivers/gpu/drm/imagination/pvr_fw.h b/drivers/gpu/drm/imagina= tion/pvr_fw.h index ab69f40a7fbc6304171f16dd16d825a68b0362a5..8d3f0ee0aac69373f15ac5919d5= b0f27c67cb284 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.h +++ b/drivers/gpu/drm/imagination/pvr_fw.h @@ -478,4 +478,9 @@ pvr_fw_object_get_fw_addr(struct pvr_fw_object *fw_obj,= u32 *fw_addr_out) pvr_fw_object_get_fw_addr_offset(fw_obj, 0, fw_addr_out); } =20 +/* Util functions defined in pvr_util.c. These are intended for use in pvr= _fw_.c files. */ +int +pvr_fw_process_elf_command_stream(struct pvr_device *pvr_dev, const u8 *fw= , u8 *fw_code_ptr, + u8 *fw_data_ptr, u8 *fw_core_code_ptr, u8 *fw_core_data_ptr); + #endif /* PVR_FW_H */ diff --git a/drivers/gpu/drm/imagination/pvr_fw_mips.c b/drivers/gpu/drm/im= agination/pvr_fw_mips.c index 524a9bd0a20b64c509f5708cc61d93b4c864b835..7f341ceb0661c61ac059654faee= c91e149036467 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_mips.c +++ b/drivers/gpu/drm/imagination/pvr_fw_mips.c @@ -8,7 +8,6 @@ #include "pvr_rogue_mips.h" #include "pvr_vm_mips.h" =20 -#include #include #include =20 @@ -16,60 +15,6 @@ #define ROGUE_FW_HEAP_MIPS_SHIFT 24 /* 16 MB */ #define ROGUE_FW_HEAP_MIPS_RESERVED_SIZE SZ_1M =20 -/** - * process_elf_command_stream() - Process ELF firmware image and populate - * firmware sections - * @pvr_dev: Device pointer. - * @fw: Pointer to firmware image. - * @fw_code_ptr: Pointer to FW code section. - * @fw_data_ptr: Pointer to FW data section. - * @fw_core_code_ptr: Pointer to FW coremem code section. - * @fw_core_data_ptr: Pointer to FW coremem data section. - * - * Returns : - * * 0 on success, or - * * -EINVAL on any error in ELF command stream. - */ -static int -process_elf_command_stream(struct pvr_device *pvr_dev, const u8 *fw, u8 *f= w_code_ptr, - u8 *fw_data_ptr, u8 *fw_core_code_ptr, u8 *fw_core_data_ptr) -{ - struct elf32_hdr *header =3D (struct elf32_hdr *)fw; - struct elf32_phdr *program_header =3D (struct elf32_phdr *)(fw + header->= e_phoff); - struct drm_device *drm_dev =3D from_pvr_device(pvr_dev); - u32 entry; - int err; - - for (entry =3D 0; entry < header->e_phnum; entry++, program_header++) { - void *write_addr; - - /* Only consider loadable entries in the ELF segment table */ - if (program_header->p_type !=3D PT_LOAD) - continue; - - err =3D pvr_fw_find_mmu_segment(pvr_dev, program_header->p_vaddr, - program_header->p_memsz, fw_code_ptr, fw_data_ptr, - fw_core_code_ptr, fw_core_data_ptr, &write_addr); - if (err) { - drm_err(drm_dev, - "Addr 0x%x (size: %d) not found in any firmware segment", - program_header->p_vaddr, program_header->p_memsz); - return err; - } - - /* Write to FW allocation only if available */ - if (write_addr) { - memcpy(write_addr, fw + program_header->p_offset, - program_header->p_filesz); - - memset((u8 *)write_addr + program_header->p_filesz, 0, - program_header->p_memsz - program_header->p_filesz); - } - } - - return 0; -} - static int pvr_mips_init(struct pvr_device *pvr_dev) { @@ -100,8 +45,8 @@ pvr_mips_fw_process(struct pvr_device *pvr_dev, const u8= *fw, u32 page_nr; int err; =20 - err =3D process_elf_command_stream(pvr_dev, fw, fw_code_ptr, fw_data_ptr,= fw_core_code_ptr, - fw_core_data_ptr); + err =3D pvr_fw_process_elf_command_stream(pvr_dev, fw, fw_code_ptr, fw_da= ta_ptr, + fw_core_code_ptr, fw_core_data_ptr); if (err) return err; =20 diff --git a/drivers/gpu/drm/imagination/pvr_fw_util.c b/drivers/gpu/drm/im= agination/pvr_fw_util.c new file mode 100644 index 0000000000000000000000000000000000000000..7bc8a5c48e9b0eed2045607ab2c= fed80a60a32b5 --- /dev/null +++ b/drivers/gpu/drm/imagination/pvr_fw_util.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* Copyright (c) 2024 Imagination Technologies Ltd. */ + +#include "pvr_device.h" +#include "pvr_fw.h" + +#include +#include + +#include +#include +#include + +/** + * pvr_fw_process_elf_command_stream() - Process ELF firmware image and po= pulate + * firmware sections + * @pvr_dev: Device pointer. + * @fw: Pointer to firmware image. + * @fw_code_ptr: Pointer to FW code section. + * @fw_data_ptr: Pointer to FW data section. + * @fw_core_code_ptr: Pointer to FW coremem code section. + * @fw_core_data_ptr: Pointer to FW coremem data section. + * + * Returns : + * * 0 on success, or + * * -EINVAL on any error in ELF command stream. + */ +int +pvr_fw_process_elf_command_stream(struct pvr_device *pvr_dev, const u8 *fw, + u8 *fw_code_ptr, u8 *fw_data_ptr, + u8 *fw_core_code_ptr, u8 *fw_core_data_ptr) +{ + struct elf32_hdr *header =3D (struct elf32_hdr *)fw; + struct elf32_phdr *program_header =3D (struct elf32_phdr *)(fw + header->= e_phoff); + struct drm_device *drm_dev =3D from_pvr_device(pvr_dev); + u32 entry; + int err; + + for (entry =3D 0; entry < header->e_phnum; entry++, program_header++) { + void *write_addr; + + /* Only consider loadable entries in the ELF segment table */ + if (program_header->p_type !=3D PT_LOAD) + continue; + + err =3D pvr_fw_find_mmu_segment(pvr_dev, program_header->p_vaddr, + program_header->p_memsz, fw_code_ptr, fw_data_ptr, + fw_core_code_ptr, fw_core_data_ptr, &write_addr); + if (err) { + drm_err(drm_dev, + "Addr 0x%x (size: %d) not found in any firmware segment", + program_header->p_vaddr, program_header->p_memsz); + return err; + } + + /* Write to FW allocation only if available */ + if (write_addr) { + memcpy(write_addr, fw + program_header->p_offset, + program_header->p_filesz); + + memset((u8 *)write_addr + program_header->p_filesz, 0, + program_header->p_memsz - program_header->p_filesz); + } + } + + return 0; +} --=20 2.47.0