From nobody Sun Nov 24 14:44:46 2024 Received: from mx08-00376f01.pphosted.com (mx08-00376f01.pphosted.com [91.207.212.86]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F4C514E2DF; Tue, 5 Nov 2024 15:59:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.86 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730822388; cv=none; b=GdiexbnsrvJUSKbRNYpEAjV2T/4vKL7mELnf58iGiRxGvMoYBwS3dyLcxjVmXfNe7/u4d8OptuexbFJIYl4wJ4wROMo2jMAMphxrDsjGNysNES1VsXWbm1vjUHjNrEREk8pkky9aknQ5D5l7G9oKUSlqNXkgLhwHRx9mdEEasGo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730822388; c=relaxed/simple; bh=OzT2nD1xXImENRUhHuP4fEL2u4ChLzPFpgFjdOLg6vI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=gZjMgUkqmX/6n7SLtdWweCJ0fekSEWU4nudbRfLnnMGlZAPRA3GCZDSMWutfaUvzXVFPGiFoJ8SgVodGW5SBDWE24VxhYhEi9utSap2BZSyMgxaFk6zKT92x+CLjTfVZTHVSRlXf+tcT2sKdwyj1oXRsh7ROV4zgqJiy3saVRyU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=imgtec.com; spf=pass smtp.mailfrom=imgtec.com; dkim=pass (2048-bit key) header.d=imgtec.com header.i=@imgtec.com header.b=O02TGZQ+; arc=none smtp.client-ip=91.207.212.86 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=imgtec.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=imgtec.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=imgtec.com header.i=@imgtec.com header.b="O02TGZQ+" Received: from pps.filterd (m0168888.ppops.net [127.0.0.1]) by mx08-00376f01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4A5BvcWn014025; Tue, 5 Nov 2024 15:58:35 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=imgtec.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=dk201812; bh=N I2x247CL/w4XtKP0tioWSfErbLdqr9CoH9XKQ6Av6Q=; b=O02TGZQ+htBjbVY0v +EwvzbQJeb67JTo/N04arRoCDosazwMzOueXfruY0ck4I49hoHy7uYaq5y2/+wLu DBWF7JCTlz45Qz83ndmj0BsrmiPn6NeQ53nzbWiXVsTvTxa/JQrDJtpmAZPDNNap ysz6JqIvbWCMkjOsn8Dtg+8DtulyJiwbaaZ4fv8j7CUeL59XgRlqc8BhNXeDa63H MoWXvkYSdPWpmfwe4JgnLX3SpjazNaK768AjlFvD01TbcAOysm2koBr7DIz4Cv6f axLhXD7hpLORusHM15EuRTisOXSHa9FqlQK/zBqkaWKC2OQHDIIAoMYG19oL4pCd 36HCQ== Received: from hhmail05.hh.imgtec.org (83-244-153-141.cust-83.exponential-e.net [83.244.153.141]) by mx08-00376f01.pphosted.com (PPS) with ESMTPS id 42nb7wta0w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 05 Nov 2024 15:58:35 +0000 (GMT) Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa (172.25.16.114) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Tue, 5 Nov 2024 15:58:34 +0000 From: Matt Coster Date: Tue, 5 Nov 2024 15:58:20 +0000 Subject: [PATCH 14/21] drm/imagination: Use callbacks for fw irq handling Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241105-sets-bxs-4-64-patch-v1-v1-14-4ed30e865892@imgtec.com> References: <20241105-sets-bxs-4-64-patch-v1-v1-0-4ed30e865892@imgtec.com> In-Reply-To: <20241105-sets-bxs-4-64-patch-v1-v1-0-4ed30e865892@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6728; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=OzT2nD1xXImENRUhHuP4fEL2u4ChLzPFpgFjdOLg6vI=; b=owGbwMvMwCFWuUfy8817WRsYT6slMaRrOcz7tkmIMf5ZEpMc3/Jkl9ss+xQfPX3oy6O/u/LnF Fu3kpgNHaUsDGIcDLJiiiw7VliuUPujpiVx41cxzBxWJpAhDFycAjARAXGG/159G5WWBwoKVT78 Kikn89KuImztA4cfT5Zc/s7gknPf4AjD/1CZjhvKbvknpjV6VC2aVhi+ZYHCDL/2mLScL1eut5r cYgIA X-Developer-Key: i=matt.coster@imgtec.com; a=openpgp; fpr=05A40CFCE7269D61D97100A1747F0A9036F90DFA X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Authority-Analysis: v=2.4 cv=ddzS3mXe c=1 sm=1 tr=0 ts=672a40ab cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=hzDjp0mCheYA:10 a=IkcTkHD0fZMA:10 a=VlfZXiiP6vEA:10 a=r_1tXGB3AAAA:8 a=9CIW0cMrGHIu6-ODVCQA:9 a=QEXdDO2ut3YA:10 a=t8nPyN_e6usw4ciXM-Pk:22 X-Proofpoint-GUID: 5IyPgHdKP93p2xnn80Rvn8dbbFrnGioJ X-Proofpoint-ORIG-GUID: 5IyPgHdKP93p2xnn80Rvn8dbbFrnGioJ This allows for more versatility in checking and clearing firmware registers used for interrupt handling. Signed-off-by: Matt Coster --- drivers/gpu/drm/imagination/pvr_device.h | 18 +++++++++++++ drivers/gpu/drm/imagination/pvr_fw.h | 45 +++++++++------------------= ---- drivers/gpu/drm/imagination/pvr_fw_meta.c | 22 ++++++++++----- drivers/gpu/drm/imagination/pvr_fw_mips.c | 22 ++++++++++----- 4 files changed, 63 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_device.h b/drivers/gpu/drm/ima= gination/pvr_device.h index ec5eb78af82a3f3c32d6c89b68b7bc0fcee0b9d2..76f79b18af354f0e0070530dfc5= c8fe0f6a41ce1 100644 --- a/drivers/gpu/drm/imagination/pvr_device.h +++ b/drivers/gpu/drm/imagination/pvr_device.h @@ -738,4 +738,22 @@ pvr_ioctl_union_padding_check(void *instance, size_t u= nion_offset, __union_size, __member_size); \ }) =20 +/* + * These utility functions should more properly be placed in pvr_fw.h, but= that + * would cause a dependency cycle between that header and this one. Since + * they're primarily used in pvr_device.c, let's put them in here for now. + */ + +static __always_inline bool +pvr_fw_irq_pending(struct pvr_device *pvr_dev) +{ + return pvr_dev->fw_dev.defs->irq_pending(pvr_dev); +} + +static __always_inline void +pvr_fw_irq_clear(struct pvr_device *pvr_dev) +{ + pvr_dev->fw_dev.defs->irq_clear(pvr_dev); +} + #endif /* PVR_DEVICE_H */ diff --git a/drivers/gpu/drm/imagination/pvr_fw.h b/drivers/gpu/drm/imagina= tion/pvr_fw.h index 88ad713468ce3a1ee459b04dde5363c24791a4f1..ab69f40a7fbc6304171f16dd16d= 825a68b0362a5 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.h +++ b/drivers/gpu/drm/imagination/pvr_fw.h @@ -167,29 +167,22 @@ struct pvr_fw_defs { int (*wrapper_init)(struct pvr_device *pvr_dev); =20 /** - * @irq: FW Interrupt information. + * @irq_pending: Check interrupt status register for pending interrupts. * - * Those are processor dependent, and should be initialized by the - * processor backend in pvr_fw_funcs::init(). + * @pvr_dev: Target PowerVR device. + * + * This function is mandatory. */ - struct { - /** @status_reg: FW interrupt status register. */ - u32 status_reg; + bool (*irq_pending)(struct pvr_device *pvr_dev); =20 - /** - * @clear_reg: FW interrupt clear register. - * - * If @status_reg =3D=3D @clear_reg, we clear by write a bit to zero, - * otherwise we clear by writing a bit to one. - */ - u32 clear_reg; - - /** @status_mask: Bitmask of events to listen for in the status_reg. */ - u32 status_mask; - - /** @clear_mask: Value to write to the clear_reg in order to clear FW IR= Qs. */ - u32 clear_mask; - } irq; + /** + * @irq_clear: Clear pending interrupts. + * + * @pvr_dev: Target PowerVR device. + * + * This function is mandatory. + */ + void (*irq_clear)(struct pvr_device *pvr_dev); =20 /** * @has_fixed_data_addr: Specify whether the firmware fixed data must be = loaded at the @@ -390,18 +383,6 @@ struct pvr_fw_device { } fw_objs; }; =20 -#define pvr_fw_irq_read_reg(pvr_dev, name) \ - pvr_cr_read32((pvr_dev), (pvr_dev)->fw_dev.defs->irq.name ## _reg) - -#define pvr_fw_irq_write_reg(pvr_dev, name, value) \ - pvr_cr_write32((pvr_dev), (pvr_dev)->fw_dev.defs->irq.name ## _reg, value) - -#define pvr_fw_irq_pending(pvr_dev) \ - (pvr_fw_irq_read_reg(pvr_dev, status) & (pvr_dev)->fw_dev.defs->irq.statu= s_mask) - -#define pvr_fw_irq_clear(pvr_dev) \ - pvr_fw_irq_write_reg(pvr_dev, clear, (pvr_dev)->fw_dev.defs->irq.clear_ma= sk) - enum pvr_fw_processor_type { PVR_FW_PROCESSOR_TYPE_META =3D 0, PVR_FW_PROCESSOR_TYPE_MIPS, diff --git a/drivers/gpu/drm/imagination/pvr_fw_meta.c b/drivers/gpu/drm/im= agination/pvr_fw_meta.c index 4433b04e0adb3684b86a4e90f63d670a81ecd826..09de3a30b625013c190196e0207= 4fe72d08629a6 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_meta.c +++ b/drivers/gpu/drm/imagination/pvr_fw_meta.c @@ -531,6 +531,20 @@ pvr_meta_vm_unmap(struct pvr_device *pvr_dev, struct p= vr_fw_object *fw_obj) fw_obj->fw_mm_node.size); } =20 +static bool +pvr_meta_irq_pending(struct pvr_device *pvr_dev) +{ + return pvr_cr_read32(pvr_dev, ROGUE_CR_META_SP_MSLVIRQSTATUS) & + ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN; +} + +static void +pvr_meta_irq_clear(struct pvr_device *pvr_dev) +{ + pvr_cr_write32(pvr_dev, ROGUE_CR_META_SP_MSLVIRQSTATUS, + ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_CLRMSK); +} + const struct pvr_fw_defs pvr_fw_defs_meta =3D { .init =3D pvr_meta_init, .fw_process =3D pvr_meta_fw_process, @@ -538,11 +552,7 @@ const struct pvr_fw_defs pvr_fw_defs_meta =3D { .vm_unmap =3D pvr_meta_vm_unmap, .get_fw_addr_with_offset =3D pvr_meta_get_fw_addr_with_offset, .wrapper_init =3D pvr_meta_wrapper_init, - .irq =3D { - .status_reg =3D ROGUE_CR_META_SP_MSLVIRQSTATUS, - .clear_reg =3D ROGUE_CR_META_SP_MSLVIRQSTATUS, - .status_mask =3D ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN, - .clear_mask =3D ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_CLRMSK, - }, + .irq_pending =3D pvr_meta_irq_pending, + .irq_clear =3D pvr_meta_irq_clear, .has_fixed_data_addr =3D false, }; diff --git a/drivers/gpu/drm/imagination/pvr_fw_mips.c b/drivers/gpu/drm/im= agination/pvr_fw_mips.c index 2c3172841886b70eb7a9992ec3851f18adcad8d5..524a9bd0a20b64c509f5708cc61= d93b4c864b835 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_mips.c +++ b/drivers/gpu/drm/imagination/pvr_fw_mips.c @@ -227,6 +227,20 @@ pvr_mips_get_fw_addr_with_offset(struct pvr_fw_object = *fw_obj, u32 offset) ROGUE_FW_HEAP_MIPS_BASE; } =20 +static bool +pvr_mips_irq_pending(struct pvr_device *pvr_dev) +{ + return pvr_cr_read32(pvr_dev, ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS) & + ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_EN; +} + +static void +pvr_mips_irq_clear(struct pvr_device *pvr_dev) +{ + pvr_cr_write32(pvr_dev, ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR, + ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_EVENT_EN); +} + const struct pvr_fw_defs pvr_fw_defs_mips =3D { .init =3D pvr_mips_init, .fini =3D pvr_mips_fini, @@ -235,11 +249,7 @@ const struct pvr_fw_defs pvr_fw_defs_mips =3D { .vm_unmap =3D pvr_vm_mips_unmap, .get_fw_addr_with_offset =3D pvr_mips_get_fw_addr_with_offset, .wrapper_init =3D pvr_mips_wrapper_init, - .irq =3D { - .status_reg =3D ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS, - .clear_reg =3D ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR, - .status_mask =3D ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_EN, - .clear_mask =3D ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_EVENT_EN, - }, + .irq_pending =3D pvr_mips_irq_pending, + .irq_clear =3D pvr_mips_irq_clear, .has_fixed_data_addr =3D true, }; --=20 2.47.0