From nobody Sun Nov 24 13:49:58 2024 Received: from mx08-00376f01.pphosted.com (mx08-00376f01.pphosted.com [91.207.212.86]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71D291547DB; Tue, 5 Nov 2024 15:59:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.86 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730822388; cv=none; b=layyeVVfXu4kPw91O5mWDSR+2oAnevg8jzq1F2Fo+Kd68oVRQVI9XVCI5FrP9Q0crgaS93jQanGQ8m63BllSg4Rh+JzdjytqiHSFbXBlbPR75eMWF2SXgpjW4U7HcGuRWjyMBAp3rx6vpCgNqiO7gmtjWU+9/nyCJvLtx5pemPc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730822388; c=relaxed/simple; bh=2Z3laMbkgJH4qXm/x7wHPkpXvjQ+QZuwDLaHlpIH+MI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=XmZSZQ+MeH1bApg8NwKRjYa7TN1+bIA1ck59TDP2zsh3K6T7PJSzqIixGhFTfWcXdPczE9fkn3on1rNh6Xp48RILXunU9GPm7iu1nHrMTNjW8PV+Vxce1HS8lbH+n0cMEFOn44vnM2RSPr9fH9+kZ5K+1G0vvNetADXk9IuPYdk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=imgtec.com; spf=pass smtp.mailfrom=imgtec.com; dkim=pass (2048-bit key) header.d=imgtec.com header.i=@imgtec.com header.b=FSxsmyKj; arc=none smtp.client-ip=91.207.212.86 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=imgtec.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=imgtec.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=imgtec.com header.i=@imgtec.com header.b="FSxsmyKj" Received: from pps.filterd (m0168888.ppops.net [127.0.0.1]) by mx08-00376f01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4A5EH6if006936; Tue, 5 Nov 2024 15:58:32 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=imgtec.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=dk201812; bh=C q3ajAQ2kMi2/eED3gh1lxaZHvoIUZJP1/SKXoeTqXo=; b=FSxsmyKjeGhdj9no9 iqImq0hefg7l50/VohINt1e4txf+GG3ELUhtmnyMpmjhrDyhTYJL9fZ6HbIS7lvM AaGcKMomuIdp+mxnNC7stno63wGfR9AJ6h4KZ45RnuHSKh41+1fXti5N6k3r7jXF 92HbIaW9hQthY/gg1XdOM4NjFl9Y7ZCcGDHccG5XT+HYMrtVvb4B3GVe7ruFJCrH yNv1409GmE6Z2QndQM5y57R1IqJLUWtPdmlG/zIRI9uhDL2Fq3n2uZNQrp9yU4ah T7sjaFJdeIOk2KX5BHt89l6366W1S7K60/4y5HIqHahV+fwYYt1/2P52BUwl31Hp eml0Q== Received: from hhmail05.hh.imgtec.org (83-244-153-141.cust-83.exponential-e.net [83.244.153.141]) by mx08-00376f01.pphosted.com (PPS) with ESMTPS id 42nb7wta0u-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 05 Nov 2024 15:58:32 +0000 (GMT) Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa (172.25.16.114) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Tue, 5 Nov 2024 15:58:31 +0000 From: Matt Coster Date: Tue, 5 Nov 2024 15:58:16 +0000 Subject: [PATCH 10/21] drm/imagination: Remove firmware enable_reg Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241105-sets-bxs-4-64-patch-v1-v1-10-4ed30e865892@imgtec.com> References: <20241105-sets-bxs-4-64-patch-v1-v1-0-4ed30e865892@imgtec.com> In-Reply-To: <20241105-sets-bxs-4-64-patch-v1-v1-0-4ed30e865892@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3945; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=2Z3laMbkgJH4qXm/x7wHPkpXvjQ+QZuwDLaHlpIH+MI=; b=owGbwMvMwCFWuUfy8817WRsYT6slMaRrOcy1V92tz5tifZjH4qnLTLajgqpvVvzru6Tc9+mD5 bm7wh5RHaUsDGIcDLJiiiw7VliuUPujpiVx41cxzBxWJpAhDFycAjCRLbcY/kceaVQyytv7x+bc 8YZVy8SlNji5bfSdfL5d7OmJXXd+KkQxMtzOVJpbMS/EIDh6nWmdrOaP9zNn3yl6aJPir9jloqn DzA8A X-Developer-Key: i=matt.coster@imgtec.com; a=openpgp; fpr=05A40CFCE7269D61D97100A1747F0A9036F90DFA X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Authority-Analysis: v=2.4 cv=ddzS3mXe c=1 sm=1 tr=0 ts=672a40a8 cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=hzDjp0mCheYA:10 a=IkcTkHD0fZMA:10 a=VlfZXiiP6vEA:10 a=r_1tXGB3AAAA:8 a=NvQRLi1s1fuHPRDSktsA:9 a=QEXdDO2ut3YA:10 a=t8nPyN_e6usw4ciXM-Pk:22 X-Proofpoint-GUID: VsLPSR_BmbRTHGMT5S6YonmX2_SnQcto X-Proofpoint-ORIG-GUID: VsLPSR_BmbRTHGMT5S6YonmX2_SnQcto After the previous commit ("drm/imagination: Revert to non-threaded IRQs"), this register is now only used to enable firmware interrupts at start-of-day. This is, however, unnecessary since they are enabled by default. In addition, the soon-to-be-added RISC-V firmware processors do not have an equivalent register. Signed-off-by: Matt Coster --- drivers/gpu/drm/imagination/pvr_device.c | 1 - drivers/gpu/drm/imagination/pvr_fw.h | 11 +---------- drivers/gpu/drm/imagination/pvr_fw_meta.c | 1 - drivers/gpu/drm/imagination/pvr_fw_mips.c | 1 - 4 files changed, 1 insertion(+), 13 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_device.c b/drivers/gpu/drm/ima= gination/pvr_device.c index 43411fe64fcecd8f84c0ceabb329f2901d63ed93..52d7641a1a0c62a9c4029092e84= 6472d82950a61 100644 --- a/drivers/gpu/drm/imagination/pvr_device.c +++ b/drivers/gpu/drm/imagination/pvr_device.c @@ -172,7 +172,6 @@ pvr_device_irq_init(struct pvr_device *pvr_dev) =20 /* Clear any pending events before requesting the IRQ line. */ pvr_fw_irq_clear(pvr_dev); - pvr_fw_irq_enable(pvr_dev); =20 return request_irq(pvr_dev->irq, pvr_device_irq_handler, 0, "gpu", pvr_de= v); =20 diff --git a/drivers/gpu/drm/imagination/pvr_fw.h b/drivers/gpu/drm/imagina= tion/pvr_fw.h index b7966bd574a924862b7877c175fa2b5d757d89db..29bae4bc244a243a6a95bcf838d= 924060cc043e2 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.h +++ b/drivers/gpu/drm/imagination/pvr_fw.h @@ -188,9 +188,6 @@ struct pvr_fw_defs { * processor backend in pvr_fw_funcs::init(). */ struct { - /** @enable_reg: FW interrupt enable register. */ - u32 enable_reg; - /** @status_reg: FW interrupt status register. */ u32 status_reg; =20 @@ -202,7 +199,7 @@ struct pvr_fw_defs { */ u32 clear_reg; =20 - /** @event_mask: Bitmask of events to listen for. */ + /** @event_mask: Bitmask of events to listen for in the status_reg. */ u32 event_mask; =20 /** @clear_mask: Value to write to the clear_reg in order to clear FW IR= Qs. */ @@ -412,12 +409,6 @@ struct pvr_fw_device { #define pvr_fw_irq_clear(pvr_dev) \ pvr_fw_irq_write_reg(pvr_dev, clear, (pvr_dev)->fw_dev.defs->irq.clear_ma= sk) =20 -#define pvr_fw_irq_enable(pvr_dev) \ - pvr_fw_irq_write_reg(pvr_dev, enable, (pvr_dev)->fw_dev.defs->irq.event_m= ask) - -#define pvr_fw_irq_disable(pvr_dev) \ - pvr_fw_irq_write_reg(pvr_dev, enable, 0) - extern const struct pvr_fw_defs pvr_fw_defs_meta; extern const struct pvr_fw_defs pvr_fw_defs_mips; =20 diff --git a/drivers/gpu/drm/imagination/pvr_fw_meta.c b/drivers/gpu/drm/im= agination/pvr_fw_meta.c index c39beb70c3173ebdab13b4e810ce5d9a3419f0ba..76b24ad9aa221b6a384dc7b55ed= 2e78d2e761550 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_meta.c +++ b/drivers/gpu/drm/imagination/pvr_fw_meta.c @@ -546,7 +546,6 @@ const struct pvr_fw_defs pvr_fw_defs_meta =3D { .wrapper_init =3D pvr_meta_wrapper_init, .has_fixed_data_addr =3D pvr_meta_has_fixed_data_addr, .irq =3D { - .enable_reg =3D ROGUE_CR_META_SP_MSLVIRQENABLE, .status_reg =3D ROGUE_CR_META_SP_MSLVIRQSTATUS, .clear_reg =3D ROGUE_CR_META_SP_MSLVIRQSTATUS, .event_mask =3D ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN, diff --git a/drivers/gpu/drm/imagination/pvr_fw_mips.c b/drivers/gpu/drm/im= agination/pvr_fw_mips.c index 0bed0257e2ab75f66d8b8966b2ceac6342396fb5..c810a67eeecf1016064e76baf53= 4e31a44c859b5 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_mips.c +++ b/drivers/gpu/drm/imagination/pvr_fw_mips.c @@ -243,7 +243,6 @@ const struct pvr_fw_defs pvr_fw_defs_mips =3D { .wrapper_init =3D pvr_mips_wrapper_init, .has_fixed_data_addr =3D pvr_mips_has_fixed_data_addr, .irq =3D { - .enable_reg =3D ROGUE_CR_MIPS_WRAPPER_IRQ_ENABLE, .status_reg =3D ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS, .clear_reg =3D ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR, .event_mask =3D ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_EN, --=20 2.47.0