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Tue, 05 Nov 2024 06:57:01 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4A56v0ok032635 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 5 Nov 2024 06:57:00 GMT Received: from hu-dikshita-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 4 Nov 2024 22:56:54 -0800 From: Dikshita Agarwal Date: Tue, 5 Nov 2024 12:25:26 +0530 Subject: [PATCH v5 06/28] media: iris: implement boot sequence of the firmware Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20241105-qcom-video-iris-v5-6-a88e7c220f78@quicinc.com> References: <20241105-qcom-video-iris-v5-0-a88e7c220f78@quicinc.com> In-Reply-To: <20241105-qcom-video-iris-v5-0-a88e7c220f78@quicinc.com> To: Vikash Garodia , Abhinav Kumar , Mauro Carvalho Chehab , "Rob Herring" , Krzysztof Kozlowski , "Conor Dooley" , Philipp Zabel CC: Hans Verkuil , Sebastian Fricke , Bryan O'Donoghue , Dmitry Baryshkov , Neil Armstrong , Nicolas Dufresne , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Jianhua Lu , , , , , "Dikshita Agarwal" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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Signed-off-by: Dikshita Agarwal --- drivers/media/platform/qcom/iris/Makefile | 1 + drivers/media/platform/qcom/iris/iris_core.c | 7 ++ .../platform/qcom/iris/iris_platform_common.h | 1 + .../platform/qcom/iris/iris_platform_sm8550.c | 3 + drivers/media/platform/qcom/iris/iris_vpu_common.c | 89 ++++++++++++++++++= ++++ drivers/media/platform/qcom/iris/iris_vpu_common.h | 13 ++++ 6 files changed, 114 insertions(+) diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/plat= form/qcom/iris/Makefile index 6906caa2c481..792f1d6ac8f3 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -6,5 +6,6 @@ iris-objs +=3D iris_core.o \ iris_platform_sm8550.o \ iris_probe.o \ iris_vidc.o \ + iris_vpu_common.o \ =20 obj-$(CONFIG_VIDEO_QCOM_IRIS) +=3D iris.o diff --git a/drivers/media/platform/qcom/iris/iris_core.c b/drivers/media/p= latform/qcom/iris/iris_core.c index 8c7d53c57086..5ad66ac113ae 100644 --- a/drivers/media/platform/qcom/iris/iris_core.c +++ b/drivers/media/platform/qcom/iris/iris_core.c @@ -6,6 +6,7 @@ #include "iris_core.h" #include "iris_firmware.h" #include "iris_state.h" +#include "iris_vpu_common.h" =20 void iris_core_deinit(struct iris_core *core) { @@ -39,10 +40,16 @@ int iris_core_init(struct iris_core *core) if (ret) goto error_queue_deinit; =20 + ret =3D iris_vpu_boot_firmware(core); + if (ret) + goto error_unload_fw; + mutex_unlock(&core->lock); =20 return 0; =20 +error_unload_fw: + iris_fw_unload(core); error_queue_deinit: iris_hfi_queues_deinit(core); error: diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 04bef37b7b77..33ae340052b8 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -44,6 +44,7 @@ struct iris_platform_data { const char *fwname; u32 pas_id; struct tz_cp_config *tz_cp_config_data; + u32 core_arch; }; =20 #endif diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8550.c b/driv= ers/media/platform/qcom/iris/iris_platform_sm8550.c index 96d9d6e816a0..4f40bfeeecf1 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8550.c +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8550.c @@ -7,6 +7,8 @@ #include "iris_hfi_gen2.h" #include "iris_platform_common.h" =20 +#define VIDEO_ARCH_LX 1 + static const struct icc_info sm8550_icc_table[] =3D { { "cpu-cfg", 1000, 1000 }, { "video-mem", 1000, 15000000 }, @@ -47,4 +49,5 @@ struct iris_platform_data sm8550_data =3D { .fwname =3D "qcom/vpu/vpu30_p4.mbn", .pas_id =3D IRIS_PAS_ID, .tz_cp_config_data =3D &tz_cp_config_sm8550, + .core_arch =3D VIDEO_ARCH_LX, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.c new file mode 100644 index 000000000000..959ed46e8f47 --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights res= erved. + */ + +#include + +#include "iris_core.h" +#include "iris_vpu_common.h" + +#define CPU_BASE_OFFS 0x000A0000 + +#define CPU_CS_BASE_OFFS (CPU_BASE_OFFS) + +#define CTRL_INIT (CPU_CS_BASE_OFFS + 0x48) +#define CTRL_STATUS (CPU_CS_BASE_OFFS + 0x4C) + +#define CTRL_ERROR_STATUS__M 0xfe + +#define QTBL_INFO (CPU_CS_BASE_OFFS + 0x50) +#define QTBL_ENABLE BIT(0) + +#define QTBL_ADDR (CPU_CS_BASE_OFFS + 0x54) +#define CPU_CS_SCIACMDARG3 (CPU_CS_BASE_OFFS + 0x58) +#define SFR_ADDR (CPU_CS_BASE_OFFS + 0x5C) +#define UC_REGION_ADDR (CPU_CS_BASE_OFFS + 0x64) +#define UC_REGION_SIZE (CPU_CS_BASE_OFFS + 0x68) + +#define CPU_CS_H2XSOFTINTEN (CPU_CS_BASE_OFFS + 0x148) +#define HOST2XTENSA_INTR_ENABLE BIT(0) + +#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168) + +static void iris_vpu_setup_ucregion_memory_map(struct iris_core *core) +{ + u32 queue_size, value; + + /* Iris hardware requires 4K queue alignment */ + queue_size =3D ALIGN(sizeof(struct iris_hfi_queue_table_header) + + (IFACEQ_QUEUE_SIZE * IFACEQ_NUMQ), SZ_4K); + + value =3D (u32)core->iface_q_table_daddr; + writel(value, core->reg_base + UC_REGION_ADDR); + + /* Iris hardware requires 1M queue alignment */ + value =3D ALIGN(SFR_SIZE + queue_size, SZ_1M); + writel(value, core->reg_base + UC_REGION_SIZE); + + value =3D (u32)core->iface_q_table_daddr; + writel(value, core->reg_base + QTBL_ADDR); + + writel(QTBL_ENABLE, core->reg_base + QTBL_INFO); + + if (core->sfr_daddr) { + value =3D (u32)core->sfr_daddr + core->iris_platform_data->core_arch; + writel(value, core->reg_base + SFR_ADDR); + } +} + +int iris_vpu_boot_firmware(struct iris_core *core) +{ + u32 ctrl_init =3D BIT(0), ctrl_status =3D 0, count =3D 0, max_tries =3D 1= 000; + + iris_vpu_setup_ucregion_memory_map(core); + + writel(ctrl_init, core->reg_base + CTRL_INIT); + writel(0x1, core->reg_base + CPU_CS_SCIACMDARG3); + + while (!ctrl_status && count < max_tries) { + ctrl_status =3D readl(core->reg_base + CTRL_STATUS); + if ((ctrl_status & CTRL_ERROR_STATUS__M) =3D=3D 0x4) { + dev_err(core->dev, "invalid setting for uc_region\n"); + break; + } + + usleep_range(50, 100); + count++; + } + + if (count >=3D max_tries) { + dev_err(core->dev, "error booting up iris firmware\n"); + return -ETIME; + } + + writel(HOST2XTENSA_INTR_ENABLE, core->reg_base + CPU_CS_H2XSOFTINTEN); + writel(0x0, core->reg_base + CPU_CS_X2RPMH); + + return 0; +} diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.h new file mode 100644 index 000000000000..d9b8df6e3f80 --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights res= erved. + */ + +#ifndef _IRIS_VPU_COMMON_H_ +#define _IRIS_VPU_COMMON_H_ + +struct iris_core; + +int iris_vpu_boot_firmware(struct iris_core *core); + +#endif --=20 2.34.1