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charset="utf-8" From: Lad Prabhakar Update `rzv2h_cpg_attach_dev` to prevent external clocks not tied to the power domain from being managed by Runtime PM. This ensures that only clocks originating from the domain are controlled, thereby avoiding unintended handling of external clocks. Additionally, introduce a `no_pm` flag in `mod_clock` and `rzv2h_mod_clk` structures to exclude specific clocks from Runtime PM when needed. Some clocks, such as those in the CRU block, require unique enable/disable sequences that are incompatible with standard Runtime PM. For example, the CSI-2 D-PHY clock initialization requires toggling individual clocks, making Runtime PM unsuitable. The helper function `rzv2h_cpg_is_pm_clk()` checks whether a clock should be managed by Runtime PM based on this `no_pm` flag. New macros, such as `DEF_MOD_NO_PM`, allow straightforward declaration of clocks that bypass PM. Signed-off-by: Lad Prabhakar --- v1->v2 - Updated code to skip external clocks to be controlled from runtime PM - Updated id range check - Updated commit message --- drivers/clk/renesas/rzv2h-cpg.c | 39 +++++++++++++++++++++++++++++++++ drivers/clk/renesas/rzv2h-cpg.h | 12 +++++++--- 2 files changed, 48 insertions(+), 3 deletions(-) diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cp= g.c index b524a9d33610..9645eb84bf9d 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -98,6 +98,7 @@ struct pll_clk { * * @priv: CPG private data * @hw: handle between common and hardware-specific interfaces + * @no_pm: flag to indicate PM is not supported * @on_index: register offset * @on_bit: ON/MON bit * @mon_index: monitor register offset @@ -106,6 +107,7 @@ struct pll_clk { struct mod_clock { struct rzv2h_cpg_priv *priv; struct clk_hw hw; + bool no_pm; u8 on_index; u8 on_bit; s8 mon_index; @@ -541,6 +543,7 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *= mod, clock->on_bit =3D mod->on_bit; clock->mon_index =3D mod->mon_index; clock->mon_bit =3D mod->mon_bit; + clock->no_pm =3D mod->no_pm; clock->priv =3D priv; clock->hw.init =3D &init; =20 @@ -668,8 +671,38 @@ struct rzv2h_cpg_pd { struct generic_pm_domain genpd; }; =20 +static bool rzv2h_cpg_is_pm_clk(struct rzv2h_cpg_pd *pd, + const struct of_phandle_args *clkspec) +{ + if (clkspec->np !=3D pd->genpd.dev.of_node || clkspec->args_count !=3D 2) + return false; + + switch (clkspec->args[0]) { + case CPG_MOD: { + struct rzv2h_cpg_priv *priv =3D pd->priv; + unsigned int id =3D clkspec->args[1]; + struct mod_clock *clock; + + if (id >=3D priv->num_mod_clks) + return true; + + if (priv->clks[priv->num_core_clks + id] =3D=3D ERR_PTR(-ENOENT)) + return true; + + clock =3D to_mod_clock(__clk_get_hw(priv->clks[priv->num_core_clks + id]= )); + + return !clock->no_pm; + } + + case CPG_CORE: + default: + return true; + } +} + static int rzv2h_cpg_attach_dev(struct generic_pm_domain *domain, struct d= evice *dev) { + struct rzv2h_cpg_pd *pd =3D container_of(domain, struct rzv2h_cpg_pd, gen= pd); struct device_node *np =3D dev->of_node; struct of_phandle_args clkspec; bool once =3D true; @@ -679,6 +712,12 @@ static int rzv2h_cpg_attach_dev(struct generic_pm_doma= in *domain, struct device =20 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, &clkspec)) { + if (!rzv2h_cpg_is_pm_clk(pd, &clkspec)) { + of_node_put(clkspec.np); + i++; + continue; + } + if (once) { once =3D false; error =3D pm_clk_create(dev); diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cp= g.h index 819029c81904..0723df4c1134 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -100,6 +100,7 @@ enum clk_types { * @name: handle between common and hardware-specific interfaces * @parent: id of parent clock * @critical: flag to indicate the clock is critical + * @no_pm: flag to indicate PM is not supported * @on_index: control register index * @on_bit: ON bit * @mon_index: monitor register index @@ -109,17 +110,19 @@ struct rzv2h_mod_clk { const char *name; u16 parent; bool critical; + bool no_pm; u8 on_index; u8 on_bit; s8 mon_index; u8 mon_bit; }; =20 -#define DEF_MOD_BASE(_name, _parent, _critical, _onindex, _onbit, _moninde= x, _monbit) \ +#define DEF_MOD_BASE(_name, _parent, _critical, _no_pm, _onindex, _onbit, = _monindex, _monbit) \ { \ .name =3D (_name), \ .parent =3D (_parent), \ .critical =3D (_critical), \ + .no_pm =3D (_no_pm), \ .on_index =3D (_onindex), \ .on_bit =3D (_onbit), \ .mon_index =3D (_monindex), \ @@ -127,10 +130,13 @@ struct rzv2h_mod_clk { } =20 #define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit) \ - DEF_MOD_BASE(_name, _parent, false, _onindex, _onbit, _monindex, _monbit) + DEF_MOD_BASE(_name, _parent, false, false, _onindex, _onbit, _monindex, _= monbit) =20 #define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _mon= bit) \ - DEF_MOD_BASE(_name, _parent, true, _onindex, _onbit, _monindex, _monbit) + DEF_MOD_BASE(_name, _parent, true, false, _onindex, _onbit, _monindex, _m= onbit) + +#define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit= ) \ + DEF_MOD_BASE(_name, _parent, false, true, _onindex, _onbit, _monindex, _m= onbit) =20 /** * struct rzv2h_reset - Reset definitions --=20 2.43.0 From nobody Sun Nov 24 14:23:49 2024 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 578AD1FCC73; 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Mon, 04 Nov 2024 15:24:08 -0800 (PST) Received: from prasmi.Home ([2a06:5906:61b:2d00:b000:5e71:8a91:bce5]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4327d5ab254sm167156675e9.3.2024.11.04.15.24.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Nov 2024 15:24:08 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 2/2] clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets Date: Mon, 4 Nov 2024 23:24:01 +0000 Message-ID: <20241104232401.290423-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241104232401.290423-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20241104232401.290423-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add support for the PLLVDO clock and its related CRU clocks and reset entries in the r9a09g057 CPG driver. Introduce `CLK_PLLVDO` and associated clocks like `CLK_PLLVDO_CRU0`, `CLK_PLLVDO_CRU1`, `CLK_PLLVDO_CRU2`, and `CLK_PLLVDO_CRU3`, along with their corresponding dividers. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v1->v2 - Replaced r9a09g057-cpg with r9a09g057 in commit header - Collected RB tag from Geert --- drivers/clk/renesas/r9a09g057-cpg.c | 45 +++++++++++++++++++++++++++++ drivers/clk/renesas/rzv2h-cpg.h | 6 ++++ 2 files changed, 51 insertions(+) diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a0= 9g057-cpg.c index 7c4507fd34e6..5aa9710aa402 100644 --- a/drivers/clk/renesas/r9a09g057-cpg.c +++ b/drivers/clk/renesas/r9a09g057-cpg.c @@ -28,6 +28,7 @@ enum clk_ids { CLK_PLLCLN, CLK_PLLDTY, CLK_PLLCA55, + CLK_PLLVDO, =20 /* Internal Core Clocks */ CLK_PLLCM33_DIV16, @@ -35,7 +36,13 @@ enum clk_ids { CLK_PLLCLN_DIV8, CLK_PLLCLN_DIV16, CLK_PLLDTY_ACPU, + CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU_DIV4, + CLK_PLLDTY_DIV16, + CLK_PLLVDO_CRU0, + CLK_PLLVDO_CRU1, + CLK_PLLVDO_CRU2, + CLK_PLLVDO_CRU3, =20 /* Module Clocks */ MOD_CLK_BASE, @@ -49,6 +56,12 @@ static const struct clk_div_table dtable_1_8[] =3D { {0, 0}, }; =20 +static const struct clk_div_table dtable_2_4[] =3D { + {0, 2}, + {1, 4}, + {0, 0}, +}; + static const struct clk_div_table dtable_2_64[] =3D { {0, 2}, {1, 4}, @@ -69,6 +82,7 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __= initconst =3D { DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3), DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3), DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)), + DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2), =20 /* Internal Core Clocks */ DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), @@ -78,7 +92,14 @@ static const struct cpg_core_clk r9a09g057_core_clks[] _= _initconst =3D { DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16), =20 DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dta= ble_2_64), + DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, = 2), DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, = 4), + DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16), + + DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dta= ble_2_4), + DEF_DDIV(".pllvdo_cru1", CLK_PLLVDO_CRU1, CLK_PLLVDO, CDDIV4_DIVCTL0, dta= ble_2_4), + DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dta= ble_2_4), + DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dta= ble_2_4), =20 /* Core Clocks */ DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1), @@ -133,6 +154,18 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[]= __initconst =3D { DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12), DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13), DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14), + DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18), + DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19), + DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20), + DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21), + DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22), + DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23), + DEF_MOD("cru_2_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24), + DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25), + DEF_MOD("cru_2_pclk", CLK_PLLDTY_DIV16, 13, 10, 6, 26), + DEF_MOD("cru_3_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27), + DEF_MOD_NO_PM("cru_3_vclk", CLK_PLLVDO_CRU3, 13, 12, 6, 28), + DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29), }; =20 static const struct rzv2h_reset r9a09g057_resets[] __initconst =3D { @@ -162,6 +195,18 @@ static const struct rzv2h_reset r9a09g057_resets[] __i= nitconst =3D { DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */ DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */ DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */ + DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */ + DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */ + DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */ + DEF_RST(12, 8, 5, 25), /* CRU_1_PRESETN */ + DEF_RST(12, 9, 5, 26), /* CRU_1_ARESETN */ + DEF_RST(12, 10, 5, 27), /* CRU_1_S_RESETN */ + DEF_RST(12, 11, 5, 28), /* CRU_2_PRESETN */ + DEF_RST(12, 12, 5, 29), /* CRU_2_ARESETN */ + DEF_RST(12, 13, 5, 30), /* CRU_2_S_RESETN */ + DEF_RST(12, 14, 5, 31), /* CRU_3_PRESETN */ + DEF_RST(12, 15, 6, 0), /* CRU_3_ARESETN */ + DEF_RST(13, 0, 6, 1), /* CRU_3_S_RESETN */ }; =20 const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst =3D { diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cp= g.h index 0723df4c1134..ed8d2cad3260 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -33,12 +33,18 @@ struct ddiv { =20 #define CPG_CDDIV0 (0x400) #define CPG_CDDIV1 (0x404) +#define CPG_CDDIV3 (0x40C) +#define CPG_CDDIV4 (0x410) =20 #define CDDIV0_DIVCTL2 DDIV_PACK(CPG_CDDIV0, 8, 3, 2) #define CDDIV1_DIVCTL0 DDIV_PACK(CPG_CDDIV1, 0, 2, 4) #define CDDIV1_DIVCTL1 DDIV_PACK(CPG_CDDIV1, 4, 2, 5) #define CDDIV1_DIVCTL2 DDIV_PACK(CPG_CDDIV1, 8, 2, 6) #define CDDIV1_DIVCTL3 DDIV_PACK(CPG_CDDIV1, 12, 2, 7) +#define CDDIV3_DIVCTL3 DDIV_PACK(CPG_CDDIV3, 12, 1, 15) +#define CDDIV4_DIVCTL0 DDIV_PACK(CPG_CDDIV4, 0, 1, 16) +#define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17) +#define CDDIV4_DIVCTL2 DDIV_PACK(CPG_CDDIV4, 8, 1, 18) =20 /** * Definitions of CPG Core Clocks --=20 2.43.0