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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ1PEPF00002312.mail.protection.outlook.com (10.167.242.166) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8137.17 via Frontend Transport; Mon, 4 Nov 2024 17:54:40 +0000 Received: from AUS-P9-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 4 Nov 2024 11:54:38 -0600 From: Mario Limonciello To: Borislav Petkov , Hans de Goede , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= CC: , "Gautham R . Shenoy" , "Mario Limonciello" , Perry Yuan , , , , , "Shyam Sundar S K" , Perry Yuan , "Bagas Sanjaya" Subject: [PATCH v6 01/12] Documentation: x86: Add AMD Hardware Feedback Interface documentation Date: Mon, 4 Nov 2024 11:53:56 -0600 Message-ID: <20241104175407.19546-2-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241104175407.19546-1-mario.limonciello@amd.com> References: <20241104175407.19546-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002312:EE_|CY8PR12MB7635:EE_ X-MS-Office365-Filtering-Correlation-Id: 0e83046c-28d5-44bb-f52b-08dcfcf9c1ac X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?2D/kVzNb0tIcZ6UX7FZ+6fdE9ePrU248kvt8tKqwdxvHzuYXFKKz+/qf0FDc?= =?us-ascii?Q?1vWPrsY4Dop8Zo66ojHwyhr4q4SaCPyAlPXjGdBt2tJAdHOeD50KdWBdIcOS?= =?us-ascii?Q?nlZRSXnjTuL+6Uz5V64ZMFrVDI4GS9fq2+nr9wUKvqIkbFbFbDikkpSeOv1w?= =?us-ascii?Q?1ZlXDjO7jyIl8N8YUm5Sv9zQjE5VGt49lms6MQmz+42Dsgjia25scsP/+0EV?= =?us-ascii?Q?IgiyliqaT84nQRXoJGKWKBMNaCGes088RSij2Z0GcCgfEUSa1vegY5voXLDy?= =?us-ascii?Q?F3jvPjNFD78ZT978Zwtseb8HrVjVNoP8W1qO2zfEZvnqpZ/NAnjbeJtP/yYK?= =?us-ascii?Q?nHqrBQzJYKVwp/v+IlozHq0LkdGbcmiRERMUvIYF0+dVBiCeng3VeQUIMQpw?= =?us-ascii?Q?fc7Z5vckqkt9YnYqTqPvZR+yzCagcqz1jeTWK5xjW5guYXyHb+cAiJ/qWqD+?= =?us-ascii?Q?9z5jArFc0Zkilw9yL0yKCZHPGfxJDuHZt1v0rwzRXTkiHgrr4RIaGTftD2Pe?= =?us-ascii?Q?5hC3sycEhToDZH83b8cK4TRLW30TgSnbY0qdW6FmCJ6ddliF/JDceWEOX88K?= =?us-ascii?Q?7jF35Vx4aG7Hv6bP33sxNusN5vkvRgVkaiWZlYvc7XmK8TjzFIQHgieypTRt?= =?us-ascii?Q?w6YDbyFTQiOu7tA2ixI1SkxSnizOGAYl/IXJvSldcoE7yBR/e9hnXrolRY1T?= =?us-ascii?Q?Sg51lxbDCgAF4cjPfZazfhGoHb/Avg/mzqrCedkvy+r2DcH+i3ADlfPwVXp6?= =?us-ascii?Q?nUHQAAuINJu+v4F+bxdwnKpfugpulifxjrs1nuFlObm50Xem16spIJEYuO//?= =?us-ascii?Q?3F7Zw44Urx2LwKoDuVAwzNt+5Flh9a4f/SIVN1R4Q28OgGTxLgC0q3vwF0KX?= =?us-ascii?Q?1a6CauPdjSKQMMj9LxtehTTXATNGdKBf5BPIRnsyANeSIHn0zHvrIPR5N4nc?= =?us-ascii?Q?GtIGn0MkS15ui0HcGoJS3Rha7uh9rAAgA1DgnKkAotvtrLf/MZqXG4vcqUWN?= =?us-ascii?Q?qU5LGRukkm+tjmTmtdex1sMjLiDkD4BrGsYdZjvkAiewyoba6a2TQZ/0zlFR?= =?us-ascii?Q?iKAduhDZy8uO6U17YD+m42I8IBwaZU5N1dOHEU84RqxfA/Gt8F+ZC9Vh5OO3?= =?us-ascii?Q?0oLaLjlllH9Mb1kDdKmSyDRyHlpNq4TIYvAt6yiajKl1y1IXBzLz+j+I8dJH?= =?us-ascii?Q?U4fQ1gG4BU1QkGvNjPM9i6PDoZgzo/4tDiXvDtFhxyVWWPW53W86Lcz98UKL?= =?us-ascii?Q?ZZwZVa4nMXN9iXljMzffMu6lj/N4EKw5dSKlXhqYS/pxPjppqQs5QdMJfX6V?= =?us-ascii?Q?fveKgG4h7Kg7JOaQcZnbmj8fTU8D743jpHwK8hmk1drOjXsvr8JgBKNryDZF?= =?us-ascii?Q?V8ZPtYldc7zrdEtUtx4HtcI5Qq7YSW4llLALiQMhJyg80SXAxQ=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2024 17:54:40.4599 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0e83046c-28d5-44bb-f52b-08dcfcf9c1ac X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002312.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7635 Content-Type: text/plain; charset="utf-8" From: Perry Yuan Introduce a new documentation file, `amd_hfi.rst`, which delves into the implementation details of the AMD Hardware Feedback Interface and its associated driver, `amd_hfi`. This documentation describes how the driver provides hint to the OS scheduling which depends on the capability of core performance and efficiency ranking data. This documentation describes * The design of the driver * How the driver provides hints to the OS scheduling * How the driver interfaces with the kernel for efficiency ranking data. Reviewed-by: Bagas Sanjaya Signed-off-by: Perry Yuan Reviewed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- v6: * Fix EOF newline --- Documentation/arch/x86/amd-hfi.rst | 127 +++++++++++++++++++++++++++++ Documentation/arch/x86/index.rst | 1 + 2 files changed, 128 insertions(+) create mode 100644 Documentation/arch/x86/amd-hfi.rst diff --git a/Documentation/arch/x86/amd-hfi.rst b/Documentation/arch/x86/am= d-hfi.rst new file mode 100644 index 0000000000000..5d204688470e3 --- /dev/null +++ b/Documentation/arch/x86/amd-hfi.rst @@ -0,0 +1,127 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Hardware Feedback Interface For Hetero Core Scheduling On AMD Platform +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +:Copyright: 2024 Advanced Micro Devices, Inc. All Rights Reserved. + +:Author: Perry Yuan +:Author: Mario Limonciello + +Overview +-------- + +AMD Heterogeneous Core implementations are comprised of more than one +architectural class and CPUs are comprised of cores of various efficiency = and +power capabilities: performance-oriented *classic cores* and power-efficie= nt +*dense cores*. As such, power management strategies must be designed to +accommodate the complexities introduced by incorporating different core ty= pes. +Heterogeneous systems can also extend to more than two architectural class= es as +well. The purpose of the scheduling feedback mechanism is to provide +information to the operating system scheduler in real time such that the +scheduler can direct threads to the optimal core. + +The goal of AMD's heterogeneous architecture is to attain power benefit by= sending +background thread to the dense cores while sending high priority threads t= o the classic +cores. From a performance perspective, sending background threads to dense= cores can free +up power headroom and allow the classic cores to optimally service demandi= ng threads. +Furthermore, the area optimized nature of the dense cores allows for an in= creasing +number of physical cores. This improved core density will have positive mu= ltithreaded +performance impact. + +AMD Heterogeneous Core Driver +----------------------------- + +The ``amd_hfi`` driver delivers the operating system a performance and ene= rgy efficiency +capability data for each CPU in the system. The scheduler can use the rank= ing data +from the HFI driver to make task placement decisions. + +Thread Classification and Ranking Table Interaction +---------------------------------------------------- + +The thread classification is used to select into a ranking table that desc= ribes +an efficiency and performance ranking for each classification. + +Threads are classified during runtime into enumerated classes. The classes= represent +thread performance/power characteristics that may benefit from special sch= eduling behaviors. +The below table depicts an example of thread classification and a preferen= ce where a given thread +should be scheduled based on its thread class. The real time thread classi= fication is consumed +by the operating system and is used to inform the scheduler of where the t= hread should be placed. + +Thread Classification Example Table +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ++----------+----------------+-------------------------------+-------------= --------+---------+ +| class ID | Classification | Preferred scheduling behavior | Preemption p= riority | Counter | ++----------+----------------+-------------------------------+-------------= --------+---------+ +| 0 | Default | Performant | Highest = | | ++----------+----------------+-------------------------------+-------------= --------+---------+ +| 1 | Non-scalable | Efficient | Lowest = | PMCx1A1 | ++----------+----------------+-------------------------------+-------------= --------+---------+ +| 2 | I/O bound | Efficient | Lowest = | PMCx044 | ++----------+----------------+-------------------------------+-------------= --------+---------+ + +Thread classification is performed by the hardware each time that the thre= ad is switched out. +Threads that don't meet any hardware specified criteria will be classified= as "default". + +AMD Hardware Feedback Interface +-------------------------------- + +The Hardware Feedback Interface provides to the operating system informati= on +about the performance and energy efficiency of each CPU in the system. Each +capability is given as a unit-less quantity in the range [0-255]. A higher +performance value indicates higher performance capability, and a higher +efficiency value indicates more efficiency. Energy efficiency and performa= nce +are reported in separate capabilities in the shared memory based ranking t= able. + +These capabilities may change at runtime as a result of changes in the +operating conditions of the system or the action of external factors. +Power Management FW is responsible for detecting events that would require +a reordering of the performance and efficiency ranking. Table updates would +happen relatively infrequently and occur on the time scale of seconds or m= ore. + +The following events trigger a table update: + * Thermal Stress Events + * Silent Compute + * Extreme Low Battery Scenarios + +The kernel or a userspace policy daemon can use these capabilities to modi= fy +task placement decisions. For instance, if either the performance or energy +capabilities of a given logical processor becomes zero, it is an indicatio= n that +the hardware recommends to the operating system to not schedule any tasks = on +that processor for performance or energy efficiency reasons, respectively. + +Implementation details for Linux +-------------------------------- + +The implementation of threads scheduling consists of the following steps: + +1. A thread is spawned and scheduled to the ideal core using the default + heterogeneous scheduling policy. +2. The processor profiles thread execution and assigns an enumerated class= ification ID. + This classification is communicated to the OS via logical processor sco= pe MSR. +3. During the thread context switch out the operating system consumes the = workload(WL) + classification which resides in a logical processor scope MSR. +4. The OS triggers the hardware to clear its history by writing to an MSR, + after consuming the WL classification and before switching in the new t= hread. +5. If due to the classification, ranking table, and processor availability, + the thread is not on its ideal processor, the OS will then consider sch= eduling + the thread on its ideal processor (if available). + +Ranking Table +------------- +The ranking table is a shared memory region that is used to communicate the +performance and energy efficiency capabilities of each CPU in the system. + +The ranking table design includes rankings for each APIC ID in the system = and +rankings both for performance and efficiency for each workload classificat= ion. + +.. kernel-doc:: drivers/platform/x86/amd/hfi/hfi.c + :doc: amd_shmem_info + +Ranking Table update +--------------------------- +The power management firmware issues an platform interrupt after updating = the ranking +table and is ready for the operating system to consume it. CPUs receive su= ch interrupt +and read new ranking table from shared memory which PCCT table has provide= d, then +``amd_hfi`` driver parse the new table to provide new consume data for sch= eduling decisions. diff --git a/Documentation/arch/x86/index.rst b/Documentation/arch/x86/inde= x.rst index 8ac64d7de4dc9..56f2923f52597 100644 --- a/Documentation/arch/x86/index.rst +++ b/Documentation/arch/x86/index.rst @@ -43,3 +43,4 @@ x86-specific Documentation features elf_auxvec xstate + amd-hfi base-commit: 110213b8f0e7021819d4db273facb27701bc3381 --=20 2.43.0