From nobody Sun Nov 24 16:42:44 2024 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA7901B218D; Mon, 4 Nov 2024 10:38:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730716711; cv=none; b=ios150jtFi+8bW4ZPpfVeTEJ7Ra6bRvNHsvLM8dw8XcJLZx8p/zguj6UP1glawcq4tjBEHjLfJc9MPUC4P8RKitK9BxBkLRCV/XAQyGxiah+73OLIDFz1wqvgqwK2kqUwlm1m+7mAyHXU8OUxh42AxBzFS2BMxwNvRNYC9csaXQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730716711; c=relaxed/simple; bh=vsEVitYVDMPQzYHhzzt87qZt//TgH2xF8Dsmgp1BRZ0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VBw719dJPNNuLYhFv++NhXYjfFR2YUHs9gz1XtGBpl8TRXgonqVBfdCZbbIym2xRTfEZ1n9u7HdVNM1eiHbLQIryerDYnT3QQWuwHFFlhJ7Dbmylpf5IrLhlivTqBjLx7gw04yFRQz7UzblXos3zqoDBu+bU6YYsjuVu+yNfAh0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.helo=mgamail.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Z1LVi84e; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.helo=mgamail.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Z1LVi84e" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730716710; x=1762252710; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vsEVitYVDMPQzYHhzzt87qZt//TgH2xF8Dsmgp1BRZ0=; b=Z1LVi84eFyiWZ6HAOfpanU/c8ap47ACvKU0cyNWTQ9UCo3AK/3HnpZda +7/E0/KlMZ4QIQukKfyvdxFACmd5SZuM59wAs9v3mIcVzDsw6XYCt0Tex rBQXALQz6oJBPtXfMZ4GXNZJWdVPnHQP80516T+FI+DJsXtOLuRF4GmbB MNWrZ01snnGlTx86DksVKPFrENi1elauf6zQbAwhGcSsIjBCUdXhgDYtO v5+Tqna1S6OpQe8IenbyVT+5Ztq4AFsgliPKxs2XtJG2DKnXTvnKWsKeN 3UOjGUC9tl6XT4GdysM9uJ+mSglTcWGWHq14Zfy+Qkptvb7bsGD03pRFg A==; X-CSE-ConnectionGUID: VDjkvv78TVKBSc1DfVSu7A== X-CSE-MsgGUID: THrUGAV6T0eSVK5idyIB5Q== X-IronPort-AV: E=McAfee;i="6700,10204,11245"; a="18024547" X-IronPort-AV: E=Sophos;i="6.11,256,1725346800"; d="scan'208";a="18024547" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2024 02:38:27 -0800 X-CSE-ConnectionGUID: UWXFlgrpTVu4sxNNczPDQg== X-CSE-MsgGUID: UqKSmIsHQ1S1g38d4wGB6w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,256,1725346800"; d="scan'208";a="88438974" Received: from black.fi.intel.com ([10.237.72.28]) by orviesa005.jf.intel.com with ESMTP; 04 Nov 2024 02:38:24 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id 9BF54FD; Mon, 04 Nov 2024 12:38:23 +0200 (EET) From: "Kirill A. Shutemov" To: "Kirill A. Shutemov" , Dave Hansen , Thomas Gleixner , Ingo Molnar , Borislav Petkov , x86@kernel.org, "H. Peter Anvin" Cc: linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, Kai Huang , Kuppuswamy Sathyanarayanan , stable@vger.kernel.org Subject: [PATCHv6, RESEND 1/4] x86/tdx: Introduce wrappers to read and write TD metadata Date: Mon, 4 Nov 2024 12:38:00 +0200 Message-ID: <20241104103803.195705-2-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104103803.195705-1-kirill.shutemov@linux.intel.com> References: <20241104103803.195705-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The TDG_VM_WR TDCALL is used to ask the TDX module to change some TD-specific VM configuration. There is currently only one user in the kernel of this TDCALL leaf. More will be added shortly. Refactor to make way for more users of TDG_VM_WR who will need to modify other TD configuration values. Add a wrapper for the TDG_VM_RD TDCALL that requests TD-specific metadata from the TDX module. There are currently no users for TDG_VM_RD. Mark it as __maybe_unused until the first user appears. This is preparation for enumeration and enabling optional TD features. Signed-off-by: Kirill A. Shutemov Reviewed-by: Kai Huang Reviewed-by: Kuppuswamy Sathyanarayanan Cc: stable@vger.kernel.org --- arch/x86/coco/tdx/tdx.c | 32 ++++++++++++++++++++++++++----- arch/x86/include/asm/shared/tdx.h | 1 + 2 files changed, 28 insertions(+), 5 deletions(-) diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c index 327c45c5013f..c74bb9e7d7a3 100644 --- a/arch/x86/coco/tdx/tdx.c +++ b/arch/x86/coco/tdx/tdx.c @@ -78,6 +78,32 @@ static inline void tdcall(u64 fn, struct tdx_module_args= *args) panic("TDCALL %lld failed (Buggy TDX module!)\n", fn); } =20 +/* Read TD-scoped metadata */ +static inline u64 __maybe_unused tdg_vm_rd(u64 field, u64 *value) +{ + struct tdx_module_args args =3D { + .rdx =3D field, + }; + u64 ret; + + ret =3D __tdcall_ret(TDG_VM_RD, &args); + *value =3D args.r8; + + return ret; +} + +/* Write TD-scoped metadata */ +static inline u64 tdg_vm_wr(u64 field, u64 value, u64 mask) +{ + struct tdx_module_args args =3D { + .rdx =3D field, + .r8 =3D value, + .r9 =3D mask, + }; + + return __tdcall(TDG_VM_WR, &args); +} + /** * tdx_mcall_get_report0() - Wrapper to get TDREPORT0 (a.k.a. TDREPORT * subtype 0) using TDG.MR.REPORT TDCALL. @@ -929,10 +955,6 @@ static void tdx_kexec_finish(void) =20 void __init tdx_early_init(void) { - struct tdx_module_args args =3D { - .rdx =3D TDCS_NOTIFY_ENABLES, - .r9 =3D -1ULL, - }; u64 cc_mask; u32 eax, sig[3]; =20 @@ -951,7 +973,7 @@ void __init tdx_early_init(void) cc_set_mask(cc_mask); =20 /* Kernel does not use NOTIFY_ENABLES and does not need random #VEs */ - tdcall(TDG_VM_WR, &args); + tdg_vm_wr(TDCS_NOTIFY_ENABLES, 0, -1ULL); =20 /* * All bits above GPA width are reserved and kernel treats shared bit diff --git a/arch/x86/include/asm/shared/tdx.h b/arch/x86/include/asm/share= d/tdx.h index fdfd41511b02..7e12cfa28bec 100644 --- a/arch/x86/include/asm/shared/tdx.h +++ b/arch/x86/include/asm/shared/tdx.h @@ -16,6 +16,7 @@ #define TDG_VP_VEINFO_GET 3 #define TDG_MR_REPORT 4 #define TDG_MEM_PAGE_ACCEPT 6 +#define TDG_VM_RD 7 #define TDG_VM_WR 8 =20 /* TDCS fields. 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Shutemov" To: "Kirill A. Shutemov" , Dave Hansen , Thomas Gleixner , Ingo Molnar , Borislav Petkov , x86@kernel.org, "H. Peter Anvin" Cc: linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, Kuppuswamy Sathyanarayanan , Kai Huang , stable@vger.kernel.org Subject: [PATCHv6, RESEND 2/4] x86/tdx: Rename tdx_parse_tdinfo() to tdx_setup() Date: Mon, 4 Nov 2024 12:38:01 +0200 Message-ID: <20241104103803.195705-3-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104103803.195705-1-kirill.shutemov@linux.intel.com> References: <20241104103803.195705-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rename tdx_parse_tdinfo() to tdx_setup() and move setting NOTIFY_ENABLES there. The function will be extended to adjust TD configuration. Signed-off-by: Kirill A. Shutemov Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Kai Huang Cc: stable@vger.kernel.org --- arch/x86/coco/tdx/tdx.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c index c74bb9e7d7a3..28b321a95a5e 100644 --- a/arch/x86/coco/tdx/tdx.c +++ b/arch/x86/coco/tdx/tdx.c @@ -194,7 +194,7 @@ static void __noreturn tdx_panic(const char *msg) __tdx_hypercall(&args); } =20 -static void tdx_parse_tdinfo(u64 *cc_mask) +static void tdx_setup(u64 *cc_mask) { struct tdx_module_args args =3D {}; unsigned int gpa_width; @@ -219,6 +219,9 @@ static void tdx_parse_tdinfo(u64 *cc_mask) gpa_width =3D args.rcx & GENMASK(5, 0); *cc_mask =3D BIT_ULL(gpa_width - 1); =20 + /* Kernel does not use NOTIFY_ENABLES and does not need random #VEs */ + tdg_vm_wr(TDCS_NOTIFY_ENABLES, 0, -1ULL); + /* * The kernel can not handle #VE's when accessing normal kernel * memory. Ensure that no #VE will be delivered for accesses to @@ -969,11 +972,11 @@ void __init tdx_early_init(void) setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); =20 cc_vendor =3D CC_VENDOR_INTEL; - tdx_parse_tdinfo(&cc_mask); - cc_set_mask(cc_mask); =20 - /* Kernel does not use NOTIFY_ENABLES and does not need random #VEs */ - tdg_vm_wr(TDCS_NOTIFY_ENABLES, 0, -1ULL); + /* Configure the TD */ + tdx_setup(&cc_mask); + + cc_set_mask(cc_mask); =20 /* * All bits above GPA width are reserved and kernel treats shared bit --=20 2.45.2 From nobody Sun Nov 24 16:42:44 2024 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72A691B21A2; Mon, 4 Nov 2024 10:38:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730716712; cv=none; b=cj9mf7CV+ROX402v+YKqlTzvpJZ5aIwvfbDM8z3YxBU//SkIyGNYcUzwUoSl5ryByt2Pz9QiDRF8nqO4Q+122X9eGRRWasnOP5i63jNjwMKnrrQa03O5jpUMS84cecHnk4zq/GlPuPi/jCX0+UVyr1Jk5CcOwA+EwxdT0F0/FiQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730716712; c=relaxed/simple; bh=l+TS1pXiFC0pP44t5itMQoE5V6ZudBm4Q2SlnkjMAt0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uQPrsryr6qI1zPxT1ihAoX8hQgQ7+/KCxGtpThIQy8L1haeCTv5izKxQagD3gM6RU5n1zq/4q3zHegBMBpxEYQ7CREzN6N4HfmOqfC5bB7AhGPhUVa63npxOpCbaTGx2IQwnQ2z2ymAnICNk1zo0M2meX8owgWo6BFJQCtSD36A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.helo=mgamail.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=hfIJwcu2; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.helo=mgamail.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="hfIJwcu2" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730716710; x=1762252710; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=l+TS1pXiFC0pP44t5itMQoE5V6ZudBm4Q2SlnkjMAt0=; b=hfIJwcu2hctLB4BmqvfZiuUVjDQqIuA1jRJINeRS+oOOlkfXPMsq3fyY RML5KdjqwjU9Shvl8L8qSFHUDVP8hgy186TPCaJIq9qGnwSqLaMFFYVQq gPjIl4iT8YEZneTWqjn5s9yZROL7KRq7isWrZugDPTWSJ/Ix6glm+1UlP nFsYtToGBKmaCG8WdVi6YxZj2F4FbVVd/KlNbEKoRbLN1K08nBJ8fMafU hMDqGHAqLGSVNhkk7h4Ugo11+ZWszAflteHab2fCQ89Y26lvvCPHbVTQn eNbfY55+wtP1WhQWqcUhvWJxpNDEqi20fQLauy4q6EkY836PsHjkvC3vE A==; X-CSE-ConnectionGUID: oLnq4DamTLi8xhsMm08LIw== X-CSE-MsgGUID: isd+dTYQTB6CW5vwoL+7KA== X-IronPort-AV: E=McAfee;i="6700,10204,11245"; a="18024554" X-IronPort-AV: E=Sophos;i="6.11,256,1725346800"; d="scan'208";a="18024554" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2024 02:38:28 -0800 X-CSE-ConnectionGUID: tpidT9t0QVS+G8kbFH9S2A== X-CSE-MsgGUID: GPbCIITURs23w9XJDG8Cbw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,256,1725346800"; d="scan'208";a="88438976" Received: from black.fi.intel.com ([10.237.72.28]) by orviesa005.jf.intel.com with ESMTP; 04 Nov 2024 02:38:24 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id BE0176CE; Mon, 04 Nov 2024 12:38:23 +0200 (EET) From: "Kirill A. Shutemov" To: "Kirill A. Shutemov" , Dave Hansen , Thomas Gleixner , Ingo Molnar , Borislav Petkov , x86@kernel.org, "H. Peter Anvin" Cc: linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Kai Huang Subject: [PATCHv6, RESEND 3/4] x86/tdx: Dynamically disable SEPT violations from causing #VEs Date: Mon, 4 Nov 2024 12:38:02 +0200 Message-ID: <20241104103803.195705-4-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104103803.195705-1-kirill.shutemov@linux.intel.com> References: <20241104103803.195705-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Memory access #VEs are hard for Linux to handle in contexts like the entry code or NMIs. But other OSes need them for functionality. There's a static (pre-guest-boot) way for a VMM to choose one or the other. But VMMs don't always know which OS they are booting, so they choose to deliver those #VEs so the "other" OSes will work. That, unfortunately has left us in the lurch and exposed to these hard-to-handle #VEs. The TDX module has introduced a new feature. Even if the static configuration is set to "send nasty #VEs", the kernel can dynamically request that they be disabled. Once they are disabled, access to private memory that is not in the Mapped state in the Secure-EPT (SEPT) will result in an exit to the VMM rather than injecting a #VE. Check if the feature is available and disable SEPT #VE if possible. If the TD is allowed to disable/enable SEPT #VEs, the ATTR_SEPT_VE_DISABLE attribute is no longer reliable. It reflects the initial state of the control for the TD, but it will not be updated if someone (e.g. bootloader) changes it before the kernel starts. Kernel must check TDCS_TD_CTLS bit to determine if SEPT #VEs are enabled or disabled. Signed-off-by: Kirill A. Shutemov Fixes: 373e715e31bf ("x86/tdx: Panic on bad configs that #VE on "private" m= emory access") Cc: stable@vger.kernel.org Acked-by: Kai Huang --- arch/x86/coco/tdx/tdx.c | 76 ++++++++++++++++++++++++------- arch/x86/include/asm/shared/tdx.h | 10 +++- 2 files changed, 69 insertions(+), 17 deletions(-) diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c index 28b321a95a5e..a27230c44cc2 100644 --- a/arch/x86/coco/tdx/tdx.c +++ b/arch/x86/coco/tdx/tdx.c @@ -79,7 +79,7 @@ static inline void tdcall(u64 fn, struct tdx_module_args = *args) } =20 /* Read TD-scoped metadata */ -static inline u64 __maybe_unused tdg_vm_rd(u64 field, u64 *value) +static inline u64 tdg_vm_rd(u64 field, u64 *value) { struct tdx_module_args args =3D { .rdx =3D field, @@ -194,6 +194,62 @@ static void __noreturn tdx_panic(const char *msg) __tdx_hypercall(&args); } =20 +/* + * The kernel cannot handle #VEs when accessing normal kernel memory. Ensu= re + * that no #VE will be delivered for accesses to TD-private memory. + * + * TDX 1.0 does not allow the guest to disable SEPT #VE on its own. The VMM + * controls if the guest will receive such #VE with TD attribute + * ATTR_SEPT_VE_DISABLE. + * + * Newer TDX modules allow the guest to control if it wants to receive SEPT + * violation #VEs. + * + * Check if the feature is available and disable SEPT #VE if possible. + * + * If the TD is allowed to disable/enable SEPT #VEs, the ATTR_SEPT_VE_DISA= BLE + * attribute is no longer reliable. It reflects the initial state of the + * control for the TD, but it will not be updated if someone (e.g. bootloa= der) + * changes it before the kernel starts. Kernel must check TDCS_TD_CTLS bit= to + * determine if SEPT #VEs are enabled or disabled. + */ +static void disable_sept_ve(u64 td_attr) +{ + const char *msg =3D "TD misconfiguration: SEPT #VE has to be disabled"; + bool debug =3D td_attr & ATTR_DEBUG; + u64 config, controls; + + /* Is this TD allowed to disable SEPT #VE */ + tdg_vm_rd(TDCS_CONFIG_FLAGS, &config); + if (!(config & TDCS_CONFIG_FLEXIBLE_PENDING_VE)) { + /* No SEPT #VE controls for the guest: check the attribute */ + if (td_attr & ATTR_SEPT_VE_DISABLE) + return; + + /* Relax SEPT_VE_DISABLE check for debug TD for backtraces */ + if (debug) + pr_warn("%s\n", msg); + else + tdx_panic(msg); + return; + } + + /* Check if SEPT #VE has been disabled before us */ + tdg_vm_rd(TDCS_TD_CTLS, &controls); + if (controls & TD_CTLS_PENDING_VE_DISABLE) + return; + + /* Keep #VEs enabled for splats in debugging environments */ + if (debug) + return; + + /* Disable SEPT #VEs */ + tdg_vm_wr(TDCS_TD_CTLS, TD_CTLS_PENDING_VE_DISABLE, + TD_CTLS_PENDING_VE_DISABLE); + + return; +} + static void tdx_setup(u64 *cc_mask) { struct tdx_module_args args =3D {}; @@ -219,24 +275,12 @@ static void tdx_setup(u64 *cc_mask) gpa_width =3D args.rcx & GENMASK(5, 0); *cc_mask =3D BIT_ULL(gpa_width - 1); =20 + td_attr =3D args.rdx; + /* Kernel does not use NOTIFY_ENABLES and does not need random #VEs */ tdg_vm_wr(TDCS_NOTIFY_ENABLES, 0, -1ULL); =20 - /* - * The kernel can not handle #VE's when accessing normal kernel - * memory. Ensure that no #VE will be delivered for accesses to - * TD-private memory. Only VMM-shared memory (MMIO) will #VE. - */ - td_attr =3D args.rdx; - if (!(td_attr & ATTR_SEPT_VE_DISABLE)) { - const char *msg =3D "TD misconfiguration: SEPT_VE_DISABLE attribute must= be set."; - - /* Relax SEPT_VE_DISABLE check for debug TD. */ - if (td_attr & ATTR_DEBUG) - pr_warn("%s\n", msg); - else - tdx_panic(msg); - } + disable_sept_ve(td_attr); } =20 /* diff --git a/arch/x86/include/asm/shared/tdx.h b/arch/x86/include/asm/share= d/tdx.h index 7e12cfa28bec..fecb2a6e864b 100644 --- a/arch/x86/include/asm/shared/tdx.h +++ b/arch/x86/include/asm/shared/tdx.h @@ -19,9 +19,17 @@ #define TDG_VM_RD 7 #define TDG_VM_WR 8 =20 -/* TDCS fields. To be used by TDG.VM.WR and TDG.VM.RD module calls */ +/* TDX TD-Scope Metadata. To be used by TDG.VM.WR and TDG.VM.RD */ +#define TDCS_CONFIG_FLAGS 0x1110000300000016 +#define TDCS_TD_CTLS 0x1110000300000017 #define TDCS_NOTIFY_ENABLES 0x9100000000000010 =20 +/* TDCS_CONFIG_FLAGS bits */ +#define TDCS_CONFIG_FLEXIBLE_PENDING_VE BIT_ULL(1) + +/* TDCS_TD_CTLS bits */ +#define TD_CTLS_PENDING_VE_DISABLE BIT_ULL(0) + /* TDX hypercall Leaf IDs */ #define TDVMCALL_MAP_GPA 0x10001 #define TDVMCALL_GET_QUOTE 0x10002 --=20 2.45.2 From nobody Sun Nov 24 16:42:44 2024 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29B6F155392 for ; Mon, 4 Nov 2024 10:38:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730716709; cv=none; b=C0No/xiAY8+4zeHD4/WXiQHjfaotmGpiZ+ZUFnIGmYZ1n9cYDX2N7zRvdT84hmFTQXyBIVOis9S171EXQ2Y021WFVGioT8f0rBmqJvxggbLkcoHVBBQh1iAn0bYPQ3xenGXqPzmSyPtuCmtmShH3YobZfxSZ5WuSEW6207f1DP8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730716709; c=relaxed/simple; bh=J8QklsU7QHCmDXyMhd1EXmVaokxVmahaaMJYtP38qBc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dSu1OvsWN/feBlBysDhHlJyr0MmoC2xGPaeufkjgPKyvMFgWf2tFl4fBzNNxRGbIeCx+eM8+aHl41x+Hn0fV8nROt3abK7XAdFBF5Wpb/zaHgVzRyBynHS6EuF0Lm0A8XIarmBJtI0m45yHZ+byJbAOaAhnoriwoPcY5coySg9o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.helo=mgamail.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=H0CSRAas; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.helo=mgamail.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="H0CSRAas" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730716708; x=1762252708; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=J8QklsU7QHCmDXyMhd1EXmVaokxVmahaaMJYtP38qBc=; b=H0CSRAassU3Vn0IlYsNJh5+hhU80KfL9L13EL8PtKaCkeUn7WEPj4PTr e9G8TZxVf0XJcOQciG7xbmsf5lwrdsLk/XTr8gtTNPCeT1B473p+WiJYS zFEG646nidUIpbKyH+wIgqXtk9MWxnqg6DqqEbFoVeeko3GC/eYluOqLh Ci8TiEmsjuh1G8pghmLAoIylHtglgmr1jeFqmUhXGIx/yBq2uKKfA9Phd SgUP05dHuOVtN1qU7bCNUj9m4VfnRsxOyTEx6Gqdx9VJ25nXEZvXjVBN2 tqhZimcYWV3CP0qzBX4XJ6uCLk+VfS27CmdtQJVUNkkg/x9IS9lbtilul A==; X-CSE-ConnectionGUID: c3NFPYm1Q8mNOcuglemUyA== X-CSE-MsgGUID: Xd24ZacaTI+EDfcXZEWjkg== X-IronPort-AV: E=McAfee;i="6700,10204,11245"; a="18024543" X-IronPort-AV: E=Sophos;i="6.11,256,1725346800"; d="scan'208";a="18024543" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2024 02:38:27 -0800 X-CSE-ConnectionGUID: 8bLgu44xShG2V0eBw4Keqw== X-CSE-MsgGUID: vCdi5/OHSA+Nmu8Rx8mTGg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,256,1725346800"; d="scan'208";a="88438972" Received: from black.fi.intel.com ([10.237.72.28]) by orviesa005.jf.intel.com with ESMTP; 04 Nov 2024 02:38:25 -0800 Received: by black.fi.intel.com (Postfix, from userid 1000) id C387F320; Mon, 04 Nov 2024 12:38:23 +0200 (EET) From: "Kirill A. Shutemov" To: "Kirill A. Shutemov" , Dave Hansen , Thomas Gleixner , Ingo Molnar , Borislav Petkov , x86@kernel.org, "H. Peter Anvin" Cc: linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, Kai Huang Subject: [PATCHv6, RESEND 4/4] x86/tdx: Enable CPU topology enumeration Date: Mon, 4 Nov 2024 12:38:03 +0200 Message-ID: <20241104103803.195705-5-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241104103803.195705-1-kirill.shutemov@linux.intel.com> References: <20241104103803.195705-1-kirill.shutemov@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" TDX 1.0 defines baseline behaviour of TDX guest platform. TDX 1.0 generates a #VE when accessing topology-related CPUID leafs (0xB and 0x1F) and the X2APIC_APICID MSR. The kernel returns all zeros on CPUID topology. In practice, this means that the kernel can only boot with a plain topology. Any complications will cause problems. The ENUM_TOPOLOGY feature allows the VMM to provide topology information to the guest. Enabling the feature eliminates topology-related #VEs: the TDX module virtualizes accesses to the CPUID leafs and the MSR. Enable ENUM_TOPOLOGY if it is available. Signed-off-by: Kirill A. Shutemov Acked-by: Kai Huang --- arch/x86/coco/tdx/tdx.c | 27 +++++++++++++++++++++++++++ arch/x86/include/asm/shared/tdx.h | 2 ++ 2 files changed, 29 insertions(+) diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c index a27230c44cc2..d4e7504aec19 100644 --- a/arch/x86/coco/tdx/tdx.c +++ b/arch/x86/coco/tdx/tdx.c @@ -250,6 +250,32 @@ static void disable_sept_ve(u64 td_attr) return; } =20 +/* + * TDX 1.0 generates a #VE when accessing topology-related CPUID leafs (0x= B and + * 0x1F) and the X2APIC_APICID MSR. The kernel returns all zeros on CPUID = #VEs. + * In practice, this means that the kernel can only boot with a plain topo= logy. + * Any complications will cause problems. + * + * The ENUM_TOPOLOGY feature allows the VMM to provide topology informatio= n. + * Enabling the feature eliminates topology-related #VEs: the TDX module + * virtualizes accesses to the CPUID leafs and the MSR. + * + * Enable ENUM_TOPOLOGY if it is available. + */ +static void enable_cpu_topology_enumeration(void) +{ + u64 configured; + + /* Has the VMM provided a valid topology configuration? */ + tdg_vm_rd(TDCS_TOPOLOGY_ENUM_CONFIGURED, &configured); + if (!configured) { + pr_err("VMM did not configure X2APIC_IDs properly\n"); + return; + } + + tdg_vm_wr(TDCS_TD_CTLS, TD_CTLS_ENUM_TOPOLOGY, TD_CTLS_ENUM_TOPOLOGY); +} + static void tdx_setup(u64 *cc_mask) { struct tdx_module_args args =3D {}; @@ -281,6 +307,7 @@ static void tdx_setup(u64 *cc_mask) tdg_vm_wr(TDCS_NOTIFY_ENABLES, 0, -1ULL); =20 disable_sept_ve(td_attr); + enable_cpu_topology_enumeration(); } =20 /* diff --git a/arch/x86/include/asm/shared/tdx.h b/arch/x86/include/asm/share= d/tdx.h index fecb2a6e864b..89f7fcade8ae 100644 --- a/arch/x86/include/asm/shared/tdx.h +++ b/arch/x86/include/asm/shared/tdx.h @@ -23,12 +23,14 @@ #define TDCS_CONFIG_FLAGS 0x1110000300000016 #define TDCS_TD_CTLS 0x1110000300000017 #define TDCS_NOTIFY_ENABLES 0x9100000000000010 +#define TDCS_TOPOLOGY_ENUM_CONFIGURED 0x9100000000000019 =20 /* TDCS_CONFIG_FLAGS bits */ #define TDCS_CONFIG_FLEXIBLE_PENDING_VE BIT_ULL(1) =20 /* TDCS_TD_CTLS bits */ #define TD_CTLS_PENDING_VE_DISABLE BIT_ULL(0) +#define TD_CTLS_ENUM_TOPOLOGY BIT_ULL(1) =20 /* TDX hypercall Leaf IDs */ #define TDVMCALL_MAP_GPA 0x10001 --=20 2.45.2