From nobody Thu Nov 28 11:04:08 2024 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AFB241AA7BE; Mon, 4 Nov 2024 09:08:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730711313; cv=none; b=Xo6O2rzZdozX4zYc1YEZmqkxXX0/ri//V07xBA6nOZPES41MICabNo8auFR3G/d9/kneJrKwIeKtDySa7BW80rhcvFHIv4FsQxYFfc5/RwDPznyKl9rL9MBt46zMCy0KEl4E8UEqBtMZGgXssp1cbDTwjC/scItvwCHVyn9QyRc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730711313; c=relaxed/simple; bh=F3D3XEVw6M/iBwfhcpsVw1ETCoilcXoJrcXSsKxL8zY=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MnqFEWb2/NLfIEWgtFzm8pL2urljtIYK9/Xf/V6Lwl+m62cX+tZXrPIRB4EULU2fLiBSxFqdAAYmXeEhAdGXonYv9xpBkmbfTXNWj14XJQRdye61Kj4Ms3YrXA/AlpSRGaoOugi00QeKBrSHFAaH7VZiv4uIkJgI2jGiPjRij70= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=qILZgofb; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="qILZgofb" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1730711312; x=1762247312; h=from:to:subject:date:message-id:in-reply-to:references: mime-version; bh=F3D3XEVw6M/iBwfhcpsVw1ETCoilcXoJrcXSsKxL8zY=; b=qILZgofb+/Lh4Z6sNH+KdfVRpSTtu5JZOma599Jj0QLKuBZLWDxHr16R oBcoXkOItT5EXe+QYdfvIvu1IwXW5OenvNu75h9FmK+NdKd0Tcq3QOaqt UkYekRa3skKSLrA3C8bydoBQwasIbpeK3L/Frb0t2D1ExdR7JWQU9g42E 24GQJT9VpIneyUriAxA+KuYoRkVkA67hVALAVc9ENdasCdkOhEf/MMAw+ /qw3Qspzs/CXh1kYTLCnnI27+B1xr4cLrHXaoLHxliGKGs3rretDk6/xM ChRyb1x2UZ+si1QuzXm9tgOjNZQbX3mxbnx6EIW0CEQXjPqS3qftei98q Q==; X-CSE-ConnectionGUID: C3Qhg4IRR+O+O4w6DPDpdQ== X-CSE-MsgGUID: zb1DgidETUqXVZijPrGsFQ== X-IronPort-AV: E=Sophos;i="6.11,256,1725346800"; d="scan'208";a="33830816" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 04 Nov 2024 02:08:25 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 4 Nov 2024 02:08:00 -0700 Received: from training-HP-280-G1-MT-PC.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 4 Nov 2024 02:07:57 -0700 From: Divya Koppera To: , , , , , , , , , , , Subject: [PATCH net-next 1/5] net: phy: microchip_ptp : Add header file for Microchip ptp library Date: Mon, 4 Nov 2024 14:37:46 +0530 Message-ID: <20241104090750.12942-2-divya.koppera@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241104090750.12942-1-divya.koppera@microchip.com> References: <20241104090750.12942-1-divya.koppera@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This ptp header file library will cover ptp macros for future phys in Micro= chip where addresses will be same but base offset and mmd address may changes. Signed-off-by: Divya Koppera --- drivers/net/phy/microchip_ptp.h | 217 ++++++++++++++++++++++++++++++++ 1 file changed, 217 insertions(+) create mode 100644 drivers/net/phy/microchip_ptp.h diff --git a/drivers/net/phy/microchip_ptp.h b/drivers/net/phy/microchip_pt= p.h new file mode 100644 index 000000000000..617418bf9abb --- /dev/null +++ b/drivers/net/phy/microchip_ptp.h @@ -0,0 +1,217 @@ +/* SPDX-License-Identifier: GPL-2.0 + * Copyright (C) 2024 Microchip Technology + */ + +#ifndef _MICROCHIP_PTP_H +#define _MICROCHIP_PTP_H + +#ifdef CONFIG_NETWORK_PHY_TIMESTAMPING + +#include +#include +#include +#include +#include +#include + +#define MCHP_PTP_CMD_CTL(b) ((b) + 0x0) +#define MCHP_PTP_CMD_CTL_LTC_STEP_NSEC BIT(6) +#define MCHP_PTP_CMD_CTL_LTC_STEP_SEC BIT(5) +#define MCHP_PTP_CMD_CTL_CLOCK_LOAD BIT(4) +#define MCHP_PTP_CMD_CTL_CLOCK_READ BIT(3) +#define MCHP_PTP_CMD_CTL_EN BIT(1) +#define MCHP_PTP_CMD_CTL_DIS BIT(0) + +#define MCHP_PTP_REF_CLK_CFG(b) ((b) + 0x2) +#define MCHP_PTP_REF_CLK_SRC_250MHZ 0x0 +#define MCHP_PTP_REF_CLK_PERIOD_OVERRIDE BIT(9) +#define MCHP_PTP_REF_CLK_PERIOD 4 +#define MCHP_PTP_REF_CLK_CFG_SET (MCHP_PTP_REF_CLK_SRC_250MHZ |\ + MCHP_PTP_REF_CLK_PERIOD_OVERRIDE |\ + MCHP_PTP_REF_CLK_PERIOD) + +#define MCHP_PTP_LTC_SEC_HI(b) ((b) + 0x5) +#define MCHP_PTP_LTC_SEC_MID(b) ((b) + 0x6) +#define MCHP_PTP_LTC_SEC_LO(b) ((b) + 0x7) +#define MCHP_PTP_LTC_NS_HI(b) ((b) + 0x8) +#define MCHP_PTP_LTC_NS_LO(b) ((b) + 0x9) +#define MCHP_PTP_LTC_RATE_ADJ_HI(b) ((b) + 0xc) +#define MCHP_PTP_LTC_RATE_ADJ_HI_DIR BIT(15) +#define MCHP_PTP_LTC_RATE_ADJ_LO(b) ((b) + 0xd) +#define MCHP_PTP_LTC_STEP_ADJ_HI(b) ((b) + 0x12) +#define MCHP_PTP_LTC_STEP_ADJ_HI_DIR BIT(15) +#define MCHP_PTP_LTC_STEP_ADJ_LO(b) ((b) + 0x13) +#define MCHP_PTP_LTC_READ_SEC_HI(b) ((b) + 0x29) +#define MCHP_PTP_LTC_READ_SEC_MID(b) ((b) + 0x2a) +#define MCHP_PTP_LTC_READ_SEC_LO(b) ((b) + 0x2b) +#define MCHP_PTP_LTC_READ_NS_HI(b) ((b) + 0x2c) +#define MCHP_PTP_LTC_READ_NS_LO(b) ((b) + 0x2d) +#define MCHP_PTP_OP_MODE(b) ((b) + 0x41) +#define MCHP_PTP_OP_MODE_DIS 0 +#define MCHP_PTP_OP_MODE_STANDALONE 1 +#define MCHP_PTP_LATENCY_CORRECTION_CTL(b) ((b) + 0x44) +#define MCHP_PTP_PREDICTOR_EN BIT(6) +#define MCHP_PTP_TX_PRED_DIS BIT(1) +#define MCHP_PTP_RX_PRED_DIS BIT(0) +#define MCHP_PTP_LATENCY_SETTING (MCHP_PTP_PREDICTOR_EN | \ + MCHP_PTP_TX_PRED_DIS | \ + MCHP_PTP_RX_PRED_DIS) + +#define MCHP_PTP_INT_EN(b) ((b) + 0x0) +#define MCHP_PTP_INT_STS(b) ((b) + 0x01) +#define MCHP_PTP_INT_TX_TS_OVRFL_EN BIT(3) +#define MCHP_PTP_INT_TX_TS_EN BIT(2) +#define MCHP_PTP_INT_RX_TS_OVRFL_EN BIT(1) +#define MCHP_PTP_INT_RX_TS_EN BIT(0) +#define MCHP_PTP_INT_ALL_MSK (MCHP_PTP_INT_TX_TS_OVRFL_EN | \ + MCHP_PTP_INT_TX_TS_EN | \ + MCHP_PTP_INT_RX_TS_OVRFL_EN |\ + MCHP_PTP_INT_RX_TS_EN) + +#define MCHP_PTP_CAP_INFO(b) ((b) + 0x2e) +#define MCHP_PTP_TX_TS_CNT(v) (((v) & GENMASK(11, 8)) >> 8) +#define MCHP_PTP_RX_TS_CNT(v) ((v) & GENMASK(3, 0)) + +#define MCHP_PTP_RX_PARSE_CONFIG(b) ((b) + 0x42) +#define MCHP_PTP_RX_PARSE_L2_ADDR_EN(b) ((b) + 0x44) +#define MCHP_PTP_RX_PARSE_IPV4_ADDR_EN(b) ((b) + 0x45) + +#define MCHP_PTP_RX_TIMESTAMP_CONFIG(b) ((b) + 0x4e) +#define MCHP_PTP_RX_TIMESTAMP_CONFIG_PTP_FCS_DIS BIT(0) + +#define MCHP_PTP_RX_VERSION(b) ((b) + 0x48) +#define MCHP_PTP_RX_TIMESTAMP_EN(b) ((b) + 0x4d) + +#define MCHP_PTP_RX_INGRESS_NS_HI(b) ((b) + 0x54) +#define MCHP_PTP_RX_INGRESS_NS_HI_TS_VALID BIT(15) + +#define MCHP_PTP_RX_INGRESS_NS_LO(b) ((b) + 0x55) +#define MCHP_PTP_RX_INGRESS_SEC_HI(b) ((b) + 0x56) +#define MCHP_PTP_RX_INGRESS_SEC_LO(b) ((b) + 0x57) +#define MCHP_PTP_RX_MSG_HEADER2(b) ((b) + 0x59) + +#define MCHP_PTP_TX_PARSE_CONFIG(b) ((b) + 0x82) +#define MCHP_PTP_PARSE_CONFIG_LAYER2_EN BIT(0) +#define MCHP_PTP_PARSE_CONFIG_IPV4_EN BIT(1) +#define MCHP_PTP_PARSE_CONFIG_IPV6_EN BIT(2) + +#define MCHP_PTP_TX_PARSE_L2_ADDR_EN(b) ((b) + 0x84) +#define MCHP_PTP_TX_PARSE_IPV4_ADDR_EN(b) ((b) + 0x85) + +#define MCHP_PTP_TX_VERSION(b) ((b) + 0x88) +#define MCHP_PTP_MAX_VERSION(x) (((x) & GENMASK(7, 0)) << 8) +#define MCHP_PTP_MIN_VERSION(x) ((x) & GENMASK(7, 0)) + +#define MCHP_PTP_TX_TIMESTAMP_EN(b) ((b) + 0x8d) +#define MCHP_PTP_TIMESTAMP_EN_SYNC BIT(0) +#define MCHP_PTP_TIMESTAMP_EN_DREQ BIT(1) +#define MCHP_PTP_TIMESTAMP_EN_PDREQ BIT(2) +#define MCHP_PTP_TIMESTAMP_EN_PDRES BIT(3) +#define MCHP_PTP_TIMESTAMP_EN_ALL (MCHP_PTP_TIMESTAMP_EN_SYNC |\ + MCHP_PTP_TIMESTAMP_EN_DREQ |\ + MCHP_PTP_TIMESTAMP_EN_PDREQ |\ + MCHP_PTP_TIMESTAMP_EN_PDRES) + +#define MCHP_PTP_TX_TIMESTAMP_CONFIG(b) ((b) + 0x8e) +#define MCHP_PTP_TX_TIMESTAMP_CONFIG_PTP_FCS_DIS BIT(0) + +#define MCHP_PTP_TX_MOD(b) ((b) + 0x8f) +#define MCHP_PTP_TX_MOD_PTP_SYNC_TS_INSERT BIT(12) +#define MCHP_PTP_TX_MOD_PTP_FU_TS_INSERT BIT(11) + +#define MCHP_PTP_TX_EGRESS_NS_HI(b) ((b) + 0x94) +#define MCHP_PTP_TX_EGRESS_NS_HI_TS_VALID BIT(15) + +#define MCHP_PTP_TX_EGRESS_NS_LO(b) ((b) + 0x95) +#define MCHP_PTP_TX_EGRESS_SEC_HI(b) ((b) + 0x96) +#define MCHP_PTP_TX_EGRESS_SEC_LO(b) ((b) + 0x97) +#define MCHP_PTP_TX_MSG_HEADER2(b) ((b) + 0x99) + +#define MCHP_PTP_TSU_GEN_CONFIG(b) ((b) + 0xc0) +#define MCHP_PTP_TSU_GEN_CFG_TSU_EN BIT(0) + +#define MCHP_PTP_TSU_HARD_RESET(b) ((b) + 0xc1) +#define MCHP_PTP_TSU_HARDRESET BIT(0) + +/* Represents 1ppm adjustment in 2^32 format with + * each nsec contains 4 clock cycles in 250MHz. + * The value is calculated as following: (1/1000000)/((2^-32)/4) + */ +#define MCHP_PTP_1PPM_FORMAT 17179 +#define MCHP_PTP_FIFO_SIZE 8 +#define MCHP_PTP_MAX_ADJ 31249999 + +#define BASE_CLK(p) ((p)->clk_base_addr) +#define BASE_PORT(p) ((p)->port_base_addr) +#define PTP_MMD(p) ((p)->mmd) + +enum ptp_fifo_dir { + PTP_INGRESS_FIFO, + PTP_EGRESS_FIFO +}; + +struct mchp_ptp_clock { + struct mii_timestamper mii_ts; + struct phy_device *phydev; + + struct sk_buff_head tx_queue; + struct sk_buff_head rx_queue; + + struct list_head rx_ts_list; + /* Lock for Rx ts fifo */ + spinlock_t rx_ts_lock; + + int hwts_tx_type; + enum hwtstamp_rx_filters rx_filter; + int layer; + int version; + + struct ptp_clock *ptp_clock; + struct ptp_clock_info caps; + + /* Lock for phc */ + struct mutex ptp_lock; + + u16 port_base_addr; + u16 clk_base_addr; + u8 mmd; +}; + +struct mchp_ptp_rx_ts { + struct list_head list; + u32 seconds; + u32 nsec; + u16 seq_id; +}; + +struct mchp_ptp_clock *mchp_ptp_probe(struct phy_device *phydev, u8 mmd, + u16 clk_base, u16 port_base); + +int mchp_config_ptp_intr(struct mchp_ptp_clock *ptp_clock, + u16 reg, u16 val, bool enable); + +irqreturn_t mchp_ptp_handle_interrupt(struct mchp_ptp_clock *ptp_clock); + +#else + +static inline struct mchp_ptp_clock *mchp_ptp_probe(struct phy_device *phy= dev, + u8 mmd, u16 clk_base, + u16 port_base) +{ + return 0; +} + +static inline int mchp_config_ptp_intr(struct mchp_ptp_clock *ptp_clock, + u16 reg, u16 val, bool enable) +{ + return 0; +} + +static inline irqreturn_t mchp_ptp_handle_interrupt(struct mchp_ptp_clock = *ptp_clock) +{ + return IRQ_NONE; +} + +#endif //CONFIG_NETWORK_PHY_TIMESTAMPING + +#endif //_MICROCHIP_PTP_H --=20 2.17.1