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(87-94-132-183.rev.dnainternet.fi. [87.94.132.183]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2fdef8a6070sm15829991fa.89.2024.11.04.01.07.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Nov 2024 01:07:27 -0800 (PST) From: Abdiel Janulgue To: rust-for-linux@vger.kernel.org Cc: daniel.almeida@collabora.com, a.hindborg@kernel.org, linux-kernel@vger.kernel.org, dakr@redhat.com, airlied@redhat.com, miguel.ojeda.sandonis@gmail.com, wedsonaf@gmail.com, Abdiel Janulgue , Andreas Hindborg Subject: [PATCH v3 2/2] rust: add dma coherent allocator abstraction. Date: Mon, 4 Nov 2024 11:06:34 +0200 Message-ID: <20241104090711.3000818-3-abdiel.janulgue@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241104090711.3000818-1-abdiel.janulgue@gmail.com> References: <20241104090711.3000818-1-abdiel.janulgue@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a simple dma coherent allocator rust abstraction. Based on Andreas Hindborg's dma abstractions from the rnvme driver. Co-developed-by: Wedson Almeida Filho Signed-off-by: Wedson Almeida Filho Co-developed-by: Andreas Hindborg Signed-off-by: Andreas Hindborg Signed-off-by: Abdiel Janulgue --- rust/bindings/bindings_helper.h | 1 + rust/kernel/dma.rs | 165 ++++++++++++++++++++++++++++++++ rust/kernel/lib.rs | 1 + 3 files changed, 167 insertions(+) create mode 100644 rust/kernel/dma.rs diff --git a/rust/bindings/bindings_helper.h b/rust/bindings/bindings_helpe= r.h index a80783fcbe04..3ff2abbfaef6 100644 --- a/rust/bindings/bindings_helper.h +++ b/rust/bindings/bindings_helper.h @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include diff --git a/rust/kernel/dma.rs b/rust/kernel/dma.rs new file mode 100644 index 000000000000..75a304d612f0 --- /dev/null +++ b/rust/kernel/dma.rs @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Direct memory access (DMA). +//! +//! C header: [`include/linux/dma-mapping.h`](srctree/include/linux/dma-ma= pping.h) + +use crate::{ + bindings, + device::Device, + error::code::*, + error::Result, + types::ARef, +}; +use core::ops::Add; + +/// Abstraction of dma_alloc_coherent +/// +/// # Invariants +/// +/// For the lifetime of an instance of CoherentAllocation, the cpu address= is a valid pointer +/// to an allocated region of consistent memory and we hold a reference to= the device. +pub struct CoherentAllocation { + dev: ARef, + dma_handle: bindings::dma_addr_t, + count: usize, + cpu_addr: *mut T, +} + +impl CoherentAllocation { + /// Allocates a region of `size_of:: * count` of consistent memory. + /// + /// Returns a CoherentAllocation object which contains a pointer to th= e allocated region + /// (in the processor's virtual address space) and the device address = which can be + /// given to the device as the DMA address base of the region. The reg= ion is released once + /// [`CoherentAllocation`] is dropped. + /// + /// # Examples + /// + /// ``` + /// use kernel::device::Device; + /// use kernel::dma::CoherentAllocation; + /// + /// # fn dox(dev: &Device) -> Result<()> { + /// let c: CoherentAllocation =3D CoherentAllocation::alloc_coher= ent(dev, 4, GFP_KERNEL)?; + /// # Ok(()) } + /// ``` + pub fn alloc_coherent( + dev: &Device, + count: usize, + flags: kernel::alloc::Flags, + ) -> Result> { + let t_size =3D core::mem::size_of::(); + let size =3D count.checked_mul(t_size).ok_or(EOVERFLOW)?; + let mut dma_handle =3D 0; + // SAFETY: device pointer is guaranteed as valid by invariant on `= Device`. + // We ensure that we catch the failure on this function and throw = an ENOMEM + let ret =3D unsafe { + bindings::dma_alloc_attrs( + dev.as_raw(), + size, + &mut dma_handle, flags.as_raw(), + 0, + ) + }; + if ret.is_null() { + return Err(ENOMEM) + } + + Ok(Self { + dev: dev.into(), + dma_handle, + count, + cpu_addr: ret as _, + }) + } + + /// Reads a value on a location specified by index. + pub fn read(&self, index: usize) -> Result + where + T: Copy + { + if let Some(val) =3D self.cpu_buf().get(index) { + Ok(*val) + } else { + Err(EINVAL) + } + } + + /// Write a value on the memory location specified by index. + pub fn write(&mut self, index: usize, value: &T) -> Result + where + T: Copy, + { + if let Some(elem) =3D self.cpu_buf_mut().get_mut(index) { + *elem =3D *value; + Ok(()) + } else { + Err(EINVAL) + } + } + + /// Performs a read and then a write of a value on a location specifie= d by index. + pub fn read_write(&mut self, index: usize, value: &T) -> Result + where + T: Copy, + { + if let Some(elem) =3D self.cpu_buf_mut().get_mut(index) { + let val =3D *elem; + *elem =3D *value; + Ok(val) + } else { + Err(EINVAL) + } + } + + /// Returns the base address to the allocated region and the dma handl= e. + /// Caller takes ownership of returned resources. + pub fn into_parts(self) -> (usize, bindings::dma_addr_t) { + let ret =3D (self.cpu_addr as _, self.dma_handle); + core::mem::forget(self); + ret + } + + /// Returns the base address to the allocated region in the CPU's virt= ual address space. + pub fn start_ptr(&self) -> *const T { + self.cpu_addr as _ + } + + /// Returns the base address to the allocated region in the CPU's virt= ual address space as + /// a mutable pointer. + pub fn start_ptr_mut(&mut self) -> *mut T { + self.cpu_addr + } + + /// Returns a DMA handle which may given to the device as the DMA addr= ess base of + /// the region. + pub fn dma_handle(&self) -> bindings::dma_addr_t { + self.dma_handle + } + + fn cpu_buf(&self) -> &[T] + { + // SAFETY: The pointer is valid due to type invariant on `Coherent= Allocation` and + // is valid for reads for `self.count * size_of::` bytes. + unsafe { core::slice::from_raw_parts(self.cpu_addr, self.count) } + } + + fn cpu_buf_mut(&mut self) -> &mut [T] + { + // SAFETY: The pointer is valid due to type invariant on `Coherent= Allocation` and + // is valid for reads for `self.count * size_of::` bytes. + unsafe { core::slice::from_raw_parts_mut(self.cpu_addr, self.count= ) } + } +} + +impl Drop for CoherentAllocation { + fn drop(&mut self) { + let size =3D self.count * core::mem::size_of::(); + // SAFETY: the device, cpu address, and the dma handle is valid du= e to the + // type invariants on `CoherentAllocation`. + unsafe { bindings::dma_free_attrs(self.dev.as_raw(), size, + self.cpu_addr as _, + self.dma_handle, 0) } + } +} diff --git a/rust/kernel/lib.rs b/rust/kernel/lib.rs index b62451f64f6e..b713c92eb1ef 100644 --- a/rust/kernel/lib.rs +++ b/rust/kernel/lib.rs @@ -32,6 +32,7 @@ pub mod block; mod build_assert; pub mod device; +pub mod dma; pub mod error; #[cfg(CONFIG_RUST_FW_LOADER_ABSTRACTIONS)] pub mod firmware; --=20 2.43.0