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Since there are a large number of them, let's put them in a separate file to include. Acked-by: Hector Martin Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/s8000-pmgr.dtsi | 757 +++++++++++++++++++++ arch/arm64/boot/dts/apple/s8000.dtsi | 22 + arch/arm64/boot/dts/apple/s800x-6s.dtsi | 4 + arch/arm64/boot/dts/apple/s800x-ipad5.dtsi | 4 + arch/arm64/boot/dts/apple/s800x-se.dtsi | 4 + 5 files changed, 791 insertions(+) create mode 100644 arch/arm64/boot/dts/apple/s8000-pmgr.dtsi diff --git a/arch/arm64/boot/dts/apple/s8000-pmgr.dtsi b/arch/arm64/boot/dt= s/apple/s8000-pmgr.dtsi new file mode 100644 index 000000000000..196b8e745a95 --- /dev/null +++ b/arch/arm64/boot/dts/apple/s8000-pmgr.dtsi @@ -0,0 +1,757 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple S8000/3 "A9" SoC + * + * Copyright (c) 2024 Nick Chan + */ + +&pmgr { + ps_cpu0: power-controller@80000 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpu0"; + apple,always-on; /* Core device */ + }; + + ps_cpu1: power-controller@80008 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80008 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpu1"; + apple,always-on; /* Core device */ + }; + + ps_cpm: power-controller@80040 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80040 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "cpm"; + apple,always-on; /* Core device */ + }; + + ps_sio_busif: power-controller@80150 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80150 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sio_busif"; + }; + + ps_sio_p: power-controller@80158 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80158 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sio_p"; + power-domains =3D <&ps_sio_busif>; + }; + + ps_sbr: power-controller@80100 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80100 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sbr"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_aic: power-controller@80108 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80108 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aic"; + apple,always-on; /* Core device */ + }; + + ps_dwi: power-controller@80110 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80110 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dwi"; + }; + + ps_gpio: power-controller@80118 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80118 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "gpio"; + }; + + ps_pms: power-controller@80120 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80120 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pms"; + apple,always-on; /* Core device */ + }; + + ps_pcie_ref: power-controller@80148 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80148 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_ref"; + }; + + ps_mca0: power-controller@80168 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80168 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca1: power-controller@80170 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80170 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca2: power-controller@80178 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80178 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca3: power-controller@80180 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80180 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mca4: power-controller@80188 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80188 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mca4"; + power-domains =3D <&ps_sio_p>; + }; + + ps_pwm0: power-controller@80190 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80190 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pwm0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c0: power-controller@80198 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80198 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c1: power-controller@801a0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801a0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c2: power-controller@801a8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801a8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_i2c3: power-controller@801b0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801b0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "i2c3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi0: power-controller@801b8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801b8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi1: power-controller@801c0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801c0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi2: power-controller@801c8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801c8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_spi3: power-controller@801d0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801d0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart0: power-controller@801d8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801d8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart1: power-controller@801e0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801e0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart1"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart2: power-controller@801e8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801e8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart2"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart3: power-controller@801f0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801f0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart3"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart4: power-controller@801f8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x801f8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart4"; + power-domains =3D <&ps_sio_p>; + }; + + ps_sio: power-controller@80160 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80160 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sio"; + power-domains =3D <&ps_sio_p>; + apple,always-on; /* Core device */ + }; + + ps_hsic0_phy: power-controller@80128 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80128 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "hsic0_phy"; + power-domains =3D <&ps_usb2host1>; + }; + + ps_hsic1_phy: power-controller@80130 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80130 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "hsic1_phy"; + power-domains =3D <&ps_usb2host2>; + }; + + ps_isp_sens0: power-controller@80138 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80138 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_sens0"; + }; + + ps_isp_sens1: power-controller@80140 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80140 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp_sens1"; + }; + + ps_usb: power-controller@80250 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80250 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb"; + }; + + ps_usbctrl: power-controller@80258 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80258 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usbctrl"; + power-domains =3D <&ps_usb>; + }; + + ps_usb2host0: power-controller@80260 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80260 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host0"; + power-domains =3D <&ps_usbctrl>; + }; + + ps_usb2host1: power-controller@80270 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80270 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host1"; + power-domains =3D <&ps_usbctrl>; + }; + + ps_usb2host2: power-controller@80280 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80280 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host2"; + power-domains =3D <&ps_usbctrl>; + }; + + ps_rtmux: power-controller@802a8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802a8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "rtmux"; + }; + + ps_media: power-controller@802d0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802d0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "media"; + }; + + ps_isp: power-controller@802c8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802c8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "isp"; + power-domains =3D <&ps_rtmux>; + }; + + ps_msr: power-controller@802e0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802e0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "msr"; + power-domains =3D <&ps_media>; + }; + + ps_jpg: power-controller@802d8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802d8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "jpg"; + power-domains =3D <&ps_media>; + }; + + ps_disp0: power-controller@802b0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802b0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "disp0"; + power-domains =3D <&ps_rtmux>; + }; + + ps_pmp: power-controller@802e8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802e8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pmp"; + }; + + ps_pms_sram: power-controller@802f0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802f0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pms_sram"; + }; + + ps_uart5: power-controller@80200 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80200 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart5"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart6: power-controller@80208 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80208 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart6"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart7: power-controller@80210 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80210 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart7"; + power-domains =3D <&ps_sio_p>; + }; + + ps_uart8: power-controller@80218 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80218 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "uart8"; + power-domains =3D <&ps_sio_p>; + }; + + ps_aes0: power-controller@80220 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80220 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aes0"; + power-domains =3D <&ps_sio_p>; + }; + + ps_mcc: power-controller@80228 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80228 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mcc"; + apple,always-on; /* Memory cache controller */ + }; + + ps_dcs0: power-controller@80230 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80230 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs0"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs1: power-controller@80238 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80238 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs1"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs2: power-controller@80240 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80240 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs2"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs3: power-controller@80248 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80248 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dcs3"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_usb2host0_ohci: power-controller@80268 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80268 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host0_ohci"; + power-domains =3D <&ps_usb2host0>; + }; + + ps_usb2host1_ohci: power-controller@80278 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80278 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host1_ohci"; + power-domains =3D <&ps_usb2host1>; + }; + + ps_usb2host2_ohci: power-controller@80288 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80288 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usb2host2_ohci"; + power-domains =3D <&ps_usb2host2>; + }; + + ps_usbotg: power-controller@80290 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80290 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "usbotg"; + power-domains =3D <&ps_usbctrl>; + }; + + ps_smx: power-controller@80298 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80298 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "smx"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_sf: power-controller@802a0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802a0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sf"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_mipi_dsi: power-controller@802b8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802b8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "mipi_dsi"; + power-domains =3D <&ps_rtmux>; + }; + + ps_dp: power-controller@802c0 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802c0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "dp"; + power-domains =3D <&ps_disp0>; + }; + + ps_vdec: power-controller@802f8 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x802f8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "vdec"; + power-domains =3D <&ps_media>; + }; + + ps_venc: power-controller@80308 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80308 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc"; + power-domains =3D <&ps_media>; + }; + + ps_pcie: power-controller@80310 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80310 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie"; + }; + + ps_pcie_aux: power-controller@80318 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80318 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_aux"; + }; + + ps_pcie_link0: power-controller@80320 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80320 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_link0"; + power-domains =3D <&ps_pcie>; + }; + + ps_pcie_link1: power-controller@80328 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80328 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_link1"; + power-domains =3D <&ps_pcie>; + }; + + ps_pcie_link2: power-controller@80330 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80330 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_link2"; + power-domains =3D <&ps_pcie>; + }; + + ps_pcie_link3: power-controller@80338 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80338 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "pcie_link3"; + power-domains =3D <&ps_pcie>; + }; + + ps_gfx: power-controller@80340 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80340 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "gfx"; + }; + + ps_sep: power-controller@80400 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80400 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "sep"; + apple,always-on; /* Locked on */ + }; + + ps_venc_pipe: power-controller@88000 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x88000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_pipe"; + power-domains =3D <&ps_venc>; + }; + + ps_venc_me0: power-controller@88008 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x88008 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_me0"; + }; + + ps_venc_me1: power-controller@88010 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x88010 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "venc_me1"; + }; +}; + +&pmgr_mini { + ps_aop: power-controller@80000 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aop"; + power-domains =3D <&ps_aop_busif &ps_aop_cpu &ps_aop_filter>; + apple,always-on; /* Always on processor */ + }; + + ps_debug: power-controller@80008 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80008 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "debug"; + }; + + ps_aop_gpio: power-controller@80010 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80010 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aop_gpio"; + power-domains =3D <&ps_aop>; + }; + + ps_aop_cpu: power-controller@80040 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80040 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aop_cpu"; + }; + + ps_aop_filter: power-controller@80048 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80048 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aop_filter"; + }; + + ps_aop_busif: power-controller@80050 { + compatible =3D "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x80050 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "aop_busif"; + }; +}; diff --git a/arch/arm64/boot/dts/apple/s8000.dtsi b/arch/arm64/boot/dts/app= le/s8000.dtsi index 6e9046ea106c..84d6b4939ac4 100644 --- a/arch/arm64/boot/dts/apple/s8000.dtsi +++ b/arch/arm64/boot/dts/apple/s8000.dtsi @@ -61,19 +61,30 @@ serial0: serial@20a0c0000 { /* Use the bootloader-enabled clocks for now. */ clocks =3D <&clkref>, <&clkref>; clock-names =3D "uart", "clk_uart_baud0"; + power-domains =3D <&ps_uart0>; status =3D "disabled"; }; =20 + pmgr: power-management@20e000000 { + compatible =3D "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + reg =3D <0x2 0xe000000 0 0x8c000>; + }; + aic: interrupt-controller@20e100000 { compatible =3D "apple,s8000-aic", "apple,aic"; reg =3D <0x2 0x0e100000 0x0 0x100000>; #interrupt-cells =3D <3>; interrupt-controller; + power-domains =3D <&ps_aic>; }; =20 pinctrl_ap: pinctrl@20f100000 { compatible =3D "apple,s8000-pinctrl", "apple,pinctrl"; reg =3D <0x2 0x0f100000 0x0 0x100000>; + power-domains =3D <&ps_gpio>; =20 gpio-controller; #gpio-cells =3D <2>; @@ -95,6 +106,7 @@ pinctrl_ap: pinctrl@20f100000 { pinctrl_aop: pinctrl@2100f0000 { compatible =3D "apple,s8000-pinctrl", "apple,pinctrl"; reg =3D <0x2 0x100f0000 0x0 0x100000>; + power-domains =3D <&ps_aop_gpio>; =20 gpio-controller; #gpio-cells =3D <2>; @@ -113,6 +125,14 @@ pinctrl_aop: pinctrl@2100f0000 { ; }; =20 + pmgr_mini: power-management@210200000 { + compatible =3D "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + reg =3D <0x2 0x10200000 0 0x84000>; + }; + wdt: watchdog@2102b0000 { compatible =3D "apple,s8000-wdt", "apple,wdt"; reg =3D <0x2 0x102b0000 0x0 0x4000>; @@ -132,6 +152,8 @@ timer { }; }; =20 +#include "s8000-pmgr.dtsi" + /* * The A9 was made by two separate fabs on two different process * nodes: Samsung made the S8000 (APL0898) on 14nm and TSMC made diff --git a/arch/arm64/boot/dts/apple/s800x-6s.dtsi b/arch/arm64/boot/dts/= apple/s800x-6s.dtsi index 49b04db310c6..1dcf80cc2920 100644 --- a/arch/arm64/boot/dts/apple/s800x-6s.dtsi +++ b/arch/arm64/boot/dts/apple/s800x-6s.dtsi @@ -47,3 +47,7 @@ switch-mute { }; }; }; + +&framebuffer0 { + power-domains =3D <&ps_disp0 &ps_mipi_dsi>; +}; diff --git a/arch/arm64/boot/dts/apple/s800x-ipad5.dtsi b/arch/arm64/boot/d= ts/apple/s800x-ipad5.dtsi index 32570ed3cdf0..c1701e81f0c1 100644 --- a/arch/arm64/boot/dts/apple/s800x-ipad5.dtsi +++ b/arch/arm64/boot/dts/apple/s800x-ipad5.dtsi @@ -41,3 +41,7 @@ button-volup { }; }; }; + +&framebuffer0 { + power-domains =3D <&ps_disp0 &ps_dp>; +}; diff --git a/arch/arm64/boot/dts/apple/s800x-se.dtsi b/arch/arm64/boot/dts/= apple/s800x-se.dtsi index a1a5690e8371..deb7c7cc90f6 100644 --- a/arch/arm64/boot/dts/apple/s800x-se.dtsi +++ b/arch/arm64/boot/dts/apple/s800x-se.dtsi @@ -47,3 +47,7 @@ switch-mute { }; }; }; + +&framebuffer0 { + power-domains =3D <&ps_disp0 &ps_mipi_dsi>; +}; --=20 2.47.0