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Sat, 2 Nov 2024 11:34:23 +0000 (UTC) From: Janne Grunau via B4 Relay Date: Sat, 02 Nov 2024 12:34:20 +0100 Subject: [PATCH 1/5] arm64: dts: apple: t8103: Fix spi4 power domain sort order Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241102-asahi-spi-dt-v1-1-7ac44c0a88f9@jannau.net> References: <20241102-asahi-spi-dt-v1-0-7ac44c0a88f9@jannau.net> In-Reply-To: <20241102-asahi-spi-dt-v1-0-7ac44c0a88f9@jannau.net> To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1456; i=j@jannau.net; s=yk2024; h=from:subject:message-id; bh=dM/GrGK9N/5tAToyLPPTWx70HidhWtGG6XOo893Pexw=; b=owGbwMvMwCW2UNrmdq9+ahrjabUkhnQ1Ptvp6+cnpq9tM70WkXdTq6l03hTzE/Nj0s2OFi5Rt 4z1bK7oKGVhEONikBVTZEnSftnBsLpGMab2QRjMHFYmkCEMXJwCMJELpYwMy2VeOE7e8ENw+Re/ ZKat79iT9+5eNve/c/HMG4GymzLlqhn+uye9YdflnfXw4HvOJTMl5MzLIjILV8oW3VBZtbhEulO BDQA= X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 X-Endpoint-Received: by B4 Relay for j@jannau.net/yk2024 with auth_id=264 X-Original-From: Janne Grunau Reply-To: j@jannau.net From: Hector Martin Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/t8103-pmgr.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi b/arch/arm64/boot/dt= s/apple/t8103-pmgr.dtsi index 9645861a858c1a7c46c25a614c2cc4b03083bf46..c41c57d63997a59a9fe3c88de31= fddb31781398e 100644 --- a/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi +++ b/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi @@ -387,6 +387,15 @@ ps_spi3: power-controller@258 { power-domains =3D <&ps_sio>, <&ps_spi_p>; }; =20 + ps_spi4: power-controller@260 { + compatible =3D "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg =3D <0x260 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D "spi4"; + power-domains =3D <&ps_sio>, <&ps_spi_p>; + }; + ps_uart_n: power-controller@268 { compatible =3D "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; reg =3D <0x268 4>; @@ -558,15 +567,6 @@ ps_mcc: power-controller@2f8 { apple,always-on; /* Memory controller */ }; =20 - ps_spi4: power-controller@260 { - compatible =3D "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg =3D <0x260 4>; - #power-domain-cells =3D <0>; - #reset-cells =3D <0>; - label =3D "spi4"; - power-domains =3D <&ps_sio>, <&ps_spi_p>; - }; - ps_dcs0: power-controller@300 { compatible =3D "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; reg =3D <0x300 4>; --=20 2.47.0 From nobody Sun Nov 24 19:25:20 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DAADF170A0B; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241102-asahi-spi-dt-v1-2-7ac44c0a88f9@jannau.net> References: <20241102-asahi-spi-dt-v1-0-7ac44c0a88f9@jannau.net> In-Reply-To: <20241102-asahi-spi-dt-v1-0-7ac44c0a88f9@jannau.net> To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3356; i=j@jannau.net; s=yk2024; h=from:subject:message-id; bh=b1UDB+1sljglElFujEd7C6cEIDOAyC8En801j5/oUGU=; b=owGbwMvMwCW2UNrmdq9+ahrjabUkhnQ1Ptsl+TUfG5k0lHbvXWbAcKq+27eV83jxqSMrP7xLP 5bdV2zbUcrCIMbFICumyJKk/bKDYXWNYkztgzCYOaxMIEMYuDgFYCKC6xgZ3qho6r+Kr1xbrWil fa81y1rsVN8f/wOhF6Q3/FHsibknxvBP7f8+f1M1FcG6w6Zb3tb8vPp9KZdX15eYIrspefGfr3J zAAA= X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 X-Endpoint-Received: by B4 Relay for j@jannau.net/yk2024 with auth_id=264 X-Original-From: Janne Grunau Reply-To: j@jannau.net From: Janne Grunau Apple silicon devices have one or more SPI devices. Add device tree nodes for all known controllers. The missing ones could be guessed and tested with a little effort but since the devices expose no pins and no new devices are expected there is no point in spending the effort. SPI is used for spi-nor and input devices like keyboard, trackpad, touchscreen and fingerprint reader. Only the spi-nor flash has upstream drivers. Support for it will be added in a following commit. Signed-off-by: Janne Grunau --- arch/arm64/boot/dts/apple/t8103.dtsi | 68 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/app= le/t8103.dtsi index 9b0dad6b618444ac6b1c9735c50cccfc3965f947..9b2d32059c3542f12fedd7f4dca= 309baa66c1bd4 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -326,6 +326,20 @@ clkref: clock-ref { clock-output-names =3D "clkref"; }; =20 + clk_120m: clock-120m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <120000000>; + clock-output-names =3D "clk_120m"; + }; + + clk_200m: clock-200m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <200000000>; + clock-output-names =3D "clk_200m"; + }; + /* * This is a fabulated representation of the input clock * to NCO since we don't know the true clock tree. @@ -441,6 +455,46 @@ fpwm1: pwm@235044000 { status =3D "disabled"; }; =20 + spi0: spi@235100000 { + compatible =3D "apple,t8103-spi", "apple,spi"; + reg =3D <0x2 0x35100000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + clocks =3D <&clk_200m>; + power-domains =3D <&ps_spi0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi1: spi@235104000 { + compatible =3D "apple,t8103-spi", "apple,spi"; + reg =3D <0x2 0x35104000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + clocks =3D <&clk_200m>; + pinctrl-0 =3D <&spi1_pins>; + pinctrl-names =3D "default"; + power-domains =3D <&ps_spi1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi3: spi@23510c000 { + compatible =3D "apple,t8103-spi", "apple,spi"; + reg =3D <0x2 0x3510c000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + clocks =3D <&clk_120m>; + pinctrl-0 =3D <&spi3_pins>; + pinctrl-names =3D "default"; + power-domains =3D <&ps_spi3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + serial0: serial@235200000 { compatible =3D "apple,s5l-uart"; reg =3D <0x2 0x35200000 0x0 0x1000>; @@ -597,6 +651,20 @@ i2c4_pins: i2c4-pins { ; }; =20 + spi1_pins: spi1-pins { + pinmux =3D , + , + , + ; + }; + + spi3_pins: spi3-pins { + pinmux =3D , + , + , + ; + }; + pcie_pins: pcie-pins { pinmux =3D , , --=20 2.47.0 From nobody Sun Nov 24 19:25:20 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 041C3175D5A; Sat, 2 Nov 2024 11:34:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730547264; cv=none; b=iGxg1N31IGLurxDDC6nJRjMMP4yThdZrG92zBdSm/SqHkz1Pgv7MaxOiY8imF/JQbqYvoneqwt4ofQx/hzY1SpixTOB5Y5b+Ut5Y/FYoNbe+StR+tqYTLue3z4maYJ9shtbgPVGPLqdqOxe2t093wR4Tb/WkiXhAL8GJGh9+r6k= ARC-Message-Signature: i=1; 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b=byXb0RlCU1ovoD6dqU3kW+bI+i8AQUzt3ZnjsZs3czu9SHznPOqSrNY9YhBn2Q5xM TbjhQoEX7BUXsvRgfAM2pcfPGY0AjK9SEtIsAQQHbiSNli3LIu1hObBlNJ+gty3NPM fVjikVtbNCEdIbPDtVAYj/DMe9aKwwYKl0bcYY2ATih9aIjteUIZNFMCdc/UOr2+lz dlGBZGx1M/52INhZ1+wDumHtQCypJmOmN4a06MCnWn6jD+U3SkdbFK6fb3wlOeFTBc D8PttPZQaz5/TWdfACyDNXEqyQ0EMd3K4E153PJ7iZFg4lNnlf36HPvMKU91Xirocz Byoz7LhNfwpCA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92671E677FC; Sat, 2 Nov 2024 11:34:23 +0000 (UTC) From: Janne Grunau via B4 Relay Date: Sat, 02 Nov 2024 12:34:22 +0100 Subject: [PATCH 3/5] arm64: dts: apple: t8112: Add spi controller nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241102-asahi-spi-dt-v1-3-7ac44c0a88f9@jannau.net> References: <20241102-asahi-spi-dt-v1-0-7ac44c0a88f9@jannau.net> In-Reply-To: <20241102-asahi-spi-dt-v1-0-7ac44c0a88f9@jannau.net> To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2887; i=j@jannau.net; s=yk2024; h=from:subject:message-id; bh=qBexsIdH/GqhHy7brZ1sYsseqom1YJB59+/UbwP2L/Y=; b=owGbwMvMwCW2UNrmdq9+ahrjabUkhnQ1PttALc9N5sx7r1dfUKhVN3diCbv356Wprs+WmZ63/ jetcWrpKGVhEONikBVTZEnSftnBsLpGMab2QRjMHFYmkCEMXJwCMJGK94wMHWWvHT6zfS8yKd73 QbCNS6dz36Zl80pPPO/y180z9S3awMjwJ167fG9t/74pHXlLdGf1njZuSPM+foMxe5nInDlPmaa zAwA= X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 X-Endpoint-Received: by B4 Relay for j@jannau.net/yk2024 with auth_id=264 X-Original-From: Janne Grunau Reply-To: j@jannau.net From: Janne Grunau Apple silicon devices have one or more SPI devices. Add device tree nodes for all known controllers. The missing ones could be guessed and tested with a little effort but since the devices expose no pins and no new devices are expected there is no point in spending the effort. SPI is used for spi-nor and input devices like keyboard, trackpad, touchscreen and fingerprint reader. Only the spi-nor flash has upstream drivers. Support for it will be added in a following commit. Signed-off-by: Janne Grunau --- arch/arm64/boot/dts/apple/t8112.dtsi | 44 ++++++++++++++++++++++++++++++++= +++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/apple/t8112.dtsi b/arch/arm64/boot/dts/app= le/t8112.dtsi index 1666e6ab250bc0be9b8318e3c8fc903ccd3f3760..58d88f1ef92a32061765bd3b569= fdae0255dcd7e 100644 --- a/arch/arm64/boot/dts/apple/t8112.dtsi +++ b/arch/arm64/boot/dts/apple/t8112.dtsi @@ -349,6 +349,13 @@ clkref: clock-ref { clock-output-names =3D "clkref"; }; =20 + clk_200m: clock-200m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <200000000>; + clock-output-names =3D "clk_200m"; + }; + /* * This is a fabulated representation of the input clock * to NCO since we don't know the true clock tree. @@ -467,6 +474,34 @@ fpwm1: pwm@235044000 { status =3D "disabled"; }; =20 + spi1: spi@235104000 { + compatible =3D "apple,t8112-spi", "apple,spi"; + reg =3D <0x2 0x35104000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + clocks =3D <&clk_200m>; + pinctrl-0 =3D <&spi1_pins>; + pinctrl-names =3D "default"; + power-domains =3D <&ps_spi1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi3: spi@23510c000 { + compatible =3D "apple,t8112-spi", "apple,spi"; + reg =3D <0x2 0x3510c000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + clocks =3D <&clkref>; + pinctrl-0 =3D <&spi3_pins>; + pinctrl-names =3D "default"; + power-domains =3D <&ps_spi3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + serial0: serial@235200000 { compatible =3D "apple,s5l-uart"; reg =3D <0x2 0x35200000 0x0 0x1000>; @@ -626,13 +661,20 @@ i2c4_pins: i2c4-pins { ; }; =20 - spi3_pins: spi3-pins { + spi1_pins: spi1-pins { pinmux =3D , , , ; }; =20 + spi3_pins: spi3-pins { + pinmux =3D , + , + , + ; + }; + pcie_pins: pcie-pins { pinmux =3D , , --=20 2.47.0 From nobody Sun Nov 24 19:25:20 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 04171175D54; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241102-asahi-spi-dt-v1-4-7ac44c0a88f9@jannau.net> References: <20241102-asahi-spi-dt-v1-0-7ac44c0a88f9@jannau.net> In-Reply-To: <20241102-asahi-spi-dt-v1-0-7ac44c0a88f9@jannau.net> To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3545; i=j@jannau.net; s=yk2024; h=from:subject:message-id; bh=+9ZFqpJ8nwSbJAAJz7hiOfMfbrOzc9lBaAhTOBlh010=; b=owGbwMvMwCW2UNrmdq9+ahrjabUkhnQ1PttSvgvvgpYZsPw5X/f7gOnUebLcFxf13zjr7LNmq bu23JSojlIWBjEuBlkxRZYk7ZcdDKtrFGNqH4TBzGFlAhnCwMUpABM5kM7IsPfT483WK2r9/HLa Tri9dF3GqWYSUiifkuXQvc7r6tnAFYwMNyJ8XKIuXVm8Iy3x/SulnX6TtEofCkQ+b3xapaO2JTG IBwA= X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 X-Endpoint-Received: by B4 Relay for j@jannau.net/yk2024 with auth_id=264 X-Original-From: Janne Grunau Reply-To: j@jannau.net From: Janne Grunau Apple silicon devices have one or more SPI devices. Add device tree nodes for all known controllers. The missing ones could be guessed and tested with a little effort but since the devices expose no pins and no new devices are expected there is no point in spending the effort. SPI is used for spi-nor and input devices like keyboard, trackpad, touchscreen and fingerprint reader. Only the spi-nor flash has upstream drivers. Support for it will be added in a following commit. Signed-off-by: Janne Grunau --- arch/arm64/boot/dts/apple/t600x-common.dtsi | 7 +++++++ arch/arm64/boot/dts/apple/t600x-die0.dtsi | 28 ++++++++++++++++++++++= ++++ arch/arm64/boot/dts/apple/t600x-gpio-pins.dtsi | 14 +++++++++++++ 3 files changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t600x-common.dtsi b/arch/arm64/boot/= dts/apple/t600x-common.dtsi index fa8ead69936366999786cdd4910266ee08b5ca7a..87dfc13d74171f62bf308740191= 8d9d41eaac560 100644 --- a/arch/arm64/boot/dts/apple/t600x-common.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-common.dtsi @@ -362,6 +362,13 @@ clkref: clock-ref { clock-output-names =3D "clkref"; }; =20 + clk_200m: clock-200m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <200000000>; + clock-output-names =3D "clk_200m"; + }; + /* * This is a fabulated representation of the input clock * to NCO since we don't know the true clock tree. diff --git a/arch/arm64/boot/dts/apple/t600x-die0.dtsi b/arch/arm64/boot/dt= s/apple/t600x-die0.dtsi index b1c875e692c8fb9c0af46a23568a7b0cd720141b..e9b3140ba1a996eeb91b3f60470= 833060b632bd2 100644 --- a/arch/arm64/boot/dts/apple/t600x-die0.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-die0.dtsi @@ -163,6 +163,34 @@ i2c5: i2c@39b054000 { status =3D "disabled"; }; =20 + spi1: spi@39b104000 { + compatible =3D "apple,t6000-spi", "apple,spi"; + reg =3D <0x3 0x9b104000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk_200m>; + pinctrl-0 =3D <&spi1_pins>; + pinctrl-names =3D "default"; + power-domains =3D <&ps_spi1>; + status =3D "disabled"; + }; + + spi3: spi@39b10c000 { + compatible =3D "apple,t6000-spi", "apple,spi"; + reg =3D <0x3 0x9b10c000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clkref>; + pinctrl-0 =3D <&spi3_pins>; + pinctrl-names =3D "default"; + power-domains =3D <&ps_spi3>; + status =3D "disabled"; + }; + serial0: serial@39b200000 { compatible =3D "apple,s5l-uart"; reg =3D <0x3 0x9b200000 0x0 0x1000>; diff --git a/arch/arm64/boot/dts/apple/t600x-gpio-pins.dtsi b/arch/arm64/bo= ot/dts/apple/t600x-gpio-pins.dtsi index b31f1a7a2b3fc36e7dfa480d27012d6d0fd56f97..1a994c3c1b79f088d685e13d1dc= 16e7d1e6546f4 100644 --- a/arch/arm64/boot/dts/apple/t600x-gpio-pins.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-gpio-pins.dtsi @@ -36,6 +36,20 @@ i2c5_pins: i2c5-pins { ; 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Sat, 2 Nov 2024 11:34:23 +0000 (UTC) From: Janne Grunau via B4 Relay Date: Sat, 02 Nov 2024 12:34:24 +0100 Subject: [PATCH 5/5] arm64: dts: apple: Add SPI NOR nvram partition to all devices Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241102-asahi-spi-dt-v1-5-7ac44c0a88f9@jannau.net> References: <20241102-asahi-spi-dt-v1-0-7ac44c0a88f9@jannau.net> In-Reply-To: <20241102-asahi-spi-dt-v1-0-7ac44c0a88f9@jannau.net> To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3506; i=j@jannau.net; s=yk2024; h=from:subject:message-id; bh=4sH2FvtVOU7J6ZD/GsHPG804yvHnrTdh0gHvxrTVtvc=; b=owGbwMvMwCW2UNrmdq9+ahrjabUkhnQ1PrvyhtB54ap732lO8opJM52R+f/D5FkNsoGxHWksx +wqDt/pKGVhEONikBVTZEnSftnBsLpGMab2QRjMHFYmkCEMXJwCMJH10YwMR55PusaXVe8n5XBh Jqvmi6X3HwnWcxaqPZLuPqRQ7laTxMjwjb09Sa9la9eqb9+XvDPIMT0xK+7G9qk8gW1XQyw2N6m zAQA= X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 X-Endpoint-Received: by B4 Relay for j@jannau.net/yk2024 with auth_id=264 X-Original-From: Janne Grunau Reply-To: j@jannau.net From: Janne Grunau All known M1* and M2* devices use an identical SPI NOR flash configuration with a partition containing a non-volatile key:value storage. Use a .dtsi and include it for every device. The nvram partition parameters itself depend on the version of the installed Apple iboot boot loader. m1n1 will fill in the current values provided by Apple's iboot. Signed-off-by: Janne Grunau --- arch/arm64/boot/dts/apple/spi1-nvram.dtsi | 39 ++++++++++++++++++++++= ++++ arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi | 2 ++ arch/arm64/boot/dts/apple/t600x-j375.dtsi | 2 ++ arch/arm64/boot/dts/apple/t8103-jxxx.dtsi | 2 ++ arch/arm64/boot/dts/apple/t8112-jxxx.dtsi | 2 ++ 5 files changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/apple/spi1-nvram.dtsi b/arch/arm64/boot/dt= s/apple/spi1-nvram.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..3df2fd3993b52884d7c00b65099= c88d830a7a4c3 --- /dev/null +++ b/arch/arm64/boot/dts/apple/spi1-nvram.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Devicetree include for common spi-nor nvram flash. +// +// Apple uses a consistent configiguration for the nvram on all known M1* = and +// M2* devices. +// +// Copyright The Asahi Linux Contributors + +/ { + aliases { + nvram =3D &nvram; + }; +}; + +&spi1 { + status =3D "okay"; + + flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0x0>; + spi-max-frequency =3D <25000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + nvram: partition@700000 { + label =3D "nvram"; + /* To be filled by the loader */ + reg =3D <0x0 0x0>; + status =3D "disabled"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi b/arch/arm64/bo= ot/dts/apple/t600x-j314-j316.dtsi index 2e471dfe43cf885c1234d36bf0e0acfdc4904621..22ebc78e120bf8f0f71fd532e9d= ce4dcd117bbc6 100644 --- a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi @@ -119,3 +119,5 @@ sdhci0: mmc@0,0 { &fpwm0 { status =3D "okay"; }; + +#include "spi1-nvram.dtsi" diff --git a/arch/arm64/boot/dts/apple/t600x-j375.dtsi b/arch/arm64/boot/dt= s/apple/t600x-j375.dtsi index 1e5a19e49b089d4b3c5e12828b682d1993e35e75..d5b985ad567936111ee5cccc9ca= 9fc23d01d9edf 100644 --- a/arch/arm64/boot/dts/apple/t600x-j375.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-j375.dtsi @@ -126,3 +126,5 @@ &pcie0_dart_2 { &pcie0_dart_3 { status =3D "okay"; }; + +#include "spi1-nvram.dtsi" diff --git a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi b/arch/arm64/boot/dt= s/apple/t8103-jxxx.dtsi index 5988a4eb6efaa008c290b1842e0da2aae8052ba4..8e82231acab59ca0bffdcecfb66= 81f59661fcd96 100644 --- a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi +++ b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi @@ -90,3 +90,5 @@ bluetooth0: bluetooth@0,1 { &nco_clkref { clock-frequency =3D <900000000>; }; + +#include "spi1-nvram.dtsi" diff --git a/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi b/arch/arm64/boot/dt= s/apple/t8112-jxxx.dtsi index f5edf61113e7aa869613d672b281f7b7e84efb79..6da35496a4c88dbaba125ebbe8c= 5a4a428c647c3 100644 --- a/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi +++ b/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi @@ -79,3 +79,5 @@ &i2c3 { &nco_clkref { clock-frequency =3D <900000000>; }; + +#include "spi1-nvram.dtsi" --=20 2.47.0